Abstract

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our “zero-change” silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a “sweet-spot” for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

© 2018 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

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2018 (1)

S. Chung, H. Abediasl, and H. Hashemi, “A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS,” IEEE Journal of Solid-State Circuits 53(1), 275–296 (2018).
[Crossref]

2017 (2)

S. Moazeni, S. Lin, M. Wade, L. Alloatti, R. Ram, M. Popović, and V. Stojanović, “A 40Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45nm SOI CMOS,” IEEE Journal of Solid-State Circuits 52(12), 3503–3516 (2017).
[Crossref]

S. Lin, S. Moazeni, K. T. Settaluri, and V. Stojanović, “Electronic-Photonic Co-Optimization of High-Speed Silicon Photonic Transmitters,” IEEE Journal of Lightwave Technology 35(21), 4766–4780 (2017).
[Crossref]

2016 (5)

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
[Crossref]

A. H. Atabaki, H. Meng, L. Alloatti, and R. J. Ram, “High-speed polysilicon CMOS photodetector for telecom and datacom,” Appl. Phys. Lett. 109(11), 111106 (2016).
[Crossref]

K. Yu, C. Li, H. Li, A. Titriku, A. Shafik, B. Wang, Z. Wang, R. Bai, C. H. Chen, M. Fiorentino, P. Y. Chiang, and S. Palermo, “A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization,” IEEE Journal of Solid-State Circuits 51(9), 2129–2141 (2016).
[Crossref]

L. Alloatti, D. Cheian, and R. J. Ram, “High-speed modulator with interleaved junctions in zero-change CMOS photonics,” Appl. Phys. Lett. 108(13), 131101 (2016).
[Crossref]

K. K. Mehta, C. D. Bruzewicz, R. McConnell, R. J. Ram, J. M. Sage, and J. Chiaverini, “Integrated optical addressing of an ion qubit,” Nature Nanotechnology 11(12), 1066–1070 (2016).
[PubMed]

2015 (5)

C. M. Gentry, J. M. Shainline, M. T. Wade, M. J. Stevens, S. D. Dyer, X. Zeng, F. Pavanello, T. Gerrits, S. W. Nam, R. P. Mirin, and M. A. Popović, “Quantum-correlated photon pairs generated in a commercial 45 nm complementary metal-oxide semiconductor microelectronic chip,” Optica 2, 1065–1071 (2015).
[Crossref]

H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. Baehr-Jones, M. Fiorentino, M. Hochberg, S. Palermo, and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE Journal of Solid-State Circuits 50(12), 3145–3159 (2015).
[Crossref]

L. Alloatti, M. Wade, V. Stojanović, M. Popović, and R. J. Ram, “Photonics design tool for advanced CMOS nodes,” IET Optoelectronics 9(4), 163–167 (2015).
[Crossref]

C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
[Crossref]

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
[Crossref] [PubMed]

2013 (1)

2012 (3)

J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Li, J. Sun, M. Weaver, S. Urošević, M. Popović, R. J. Ram, and V. Stojanović, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20(11), 12222–12232 (2012).
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J. F. Buckwalter, X. Zheng, G. Li, K. Raj, and A. V. Krishnamoorthy, “A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process,” IEEE Journal of Solid-State Circuits 47(6), 1309–1322 (2012).
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2005 (1)

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A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

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S. Chung, H. Abediasl, and H. Hashemi, “A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS,” IEEE Journal of Solid-State Circuits 53(1), 275–296 (2018).
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M. Pantouvaki, P. De Heyn, R. Michal, P. Verheyen, S. Brad, A. Srinivasan, H. Chen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “50Gb/s Silicon Photonics Platform for Short-Reach Optical Interconnects,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2016), paper Th4H.4.

M. Rakowski, M. Pantouvaki, P. Verheyen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “A 50Gb/s, 610fJ/bit hybrid CMOS-Si photonics ring-based NRZ-OOK transmitter,” in Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

Adam, T.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Agnello, P.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Agrawal, A.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Ahsan, I.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Akhter, M. S.

M. S. Akhter, P. Somogyi, C. Sun, M. Wade, R. Meade, P. Bhargava, S. Lin, and N. Mehta, “WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers,” in, Proceedings of IEEE Symposium on High-Performance Interconnects, (IEEE, 2017), pp. 25–28.

Alavi, M.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Alloatti, L.

S. Moazeni, S. Lin, M. Wade, L. Alloatti, R. Ram, M. Popović, and V. Stojanović, “A 40Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45nm SOI CMOS,” IEEE Journal of Solid-State Circuits 52(12), 3503–3516 (2017).
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L. Alloatti, D. Cheian, and R. J. Ram, “High-speed modulator with interleaved junctions in zero-change CMOS photonics,” Appl. Phys. Lett. 108(13), 131101 (2016).
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A. H. Atabaki, H. Meng, L. Alloatti, and R. J. Ram, “High-speed polysilicon CMOS photodetector for telecom and datacom,” Appl. Phys. Lett. 109(11), 111106 (2016).
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C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
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L. Alloatti, M. Wade, V. Stojanović, M. Popović, and R. J. Ram, “Photonics design tool for advanced CMOS nodes,” IET Optoelectronics 9(4), 163–167 (2015).
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C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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J. Notaros, F. Pavanello, M. T. Wade, C. M. Gentry, A. Atabaki, L. Alloatti, R. J. Ram, and M. A. Popović, “Ultra-efficient CMOS fiber-to-chip grating couplers,” in Proceedings of Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

M. De Cea Falco, A. Atabaki, L. Alloatti, M. Wade, M. Popovic, and R. Ram, “A Thin Silicon Photonic Platform for Telecommunication Wavelengths,” in European Conference on Optical Communication, (2017), pp. SC2.25.

L. Alloatti and R. J. Ram, “Resonance-enhanced waveguide-coupled silicon-germanium detector,” arXiv preprint arXiv:1601.00542 (2016).

Analui, B.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Anderson, F. G.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Ando, T.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Armijo, G.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Armstrong, M.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Asanovic, K.

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun, V. Stojanović, and K. Asanović, “A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators,” in, Proceedings of IEEE European Solid State Circuits Conference, (IEEE, 2014), pp. 199–202.

Atabaki, A.

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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J. Notaros, F. Pavanello, M. T. Wade, C. M. Gentry, A. Atabaki, L. Alloatti, R. J. Ram, and M. A. Popović, “Ultra-efficient CMOS fiber-to-chip grating couplers,” in Proceedings of Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

S. Moazeni, A. Atabaki, D. Cheian, S. Lin, R. J. Ram, and V. Stojanović, “Monolithic Integration of O-band Photonic Transceivers in a “Zero-change” 32nm SOI CMOS,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 24.3.

M. T. Wade, F. Pavanello, R. Kumar, C. M. Gentry, A. Atabaki, R. Ram, V. Stojanović, and M. A. Popović, “75% efficient wide bandwidth grating couplers in a 45nm microelectronics CMOS process,” in Proceedings of IEEE Optical Interconnects Conference (IEEE, 2015), pp. 46–47.

M. De Cea Falco, A. Atabaki, L. Alloatti, M. Wade, M. Popovic, and R. Ram, “A Thin Silicon Photonic Platform for Telecommunication Wavelengths,” in European Conference on Optical Communication, (2017), pp. SC2.25.

Atabaki, A. H.

A. H. Atabaki, H. Meng, L. Alloatti, and R. J. Ram, “High-speed polysilicon CMOS photodetector for telecom and datacom,” Appl. Phys. Lett. 109(11), 111106 (2016).
[Crossref]

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
[Crossref]

Augur, R.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Auth, C.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
[Crossref]

Avizienis, R.

Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun, V. Stojanović, and K. Asanović, “A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators,” in, Proceedings of IEEE European Solid State Circuits Conference, (IEEE, 2014), pp. 199–202.

Avizienis, R. R.

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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Ayazi, A.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Baehr-Jones, T.

H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. Baehr-Jones, M. Fiorentino, M. Hochberg, S. Palermo, and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE Journal of Solid-State Circuits 50(12), 3145–3159 (2015).
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Bafrali, R.

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Bai, R.

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Bailey, R. C.

M. Iqbal, M. A. Gleeson, B. Spaugh, F. Tybor, W. G. Gunn, M. Hochberg, T. Baehr-Jones, R. C. Bailey, and L. C. Gunn, “Label-Free Biosensor Arrays Based on Silicon Ring Resonators and High-Speed Optical Scanning Instrumentation,” IEEE Journal of Selected Topics in Quantum Electronics 16(3), 654–661 (2010).
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Baker, F.

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Baks, C. W.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Balardeta, J.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Baldi, D.

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Balmater, E.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Barla, K.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Baron, F.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Barwicz, T.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Batail, E.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Battegay, F.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Bedell, S.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Belyansky, M.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Beneyton, R.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Bennett, B.

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Bhargava, P.

M. S. Akhter, P. Somogyi, C. Sun, M. Wade, R. Meade, P. Bhargava, S. Lin, and N. Mehta, “WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers,” in, Proceedings of IEEE Symposium on High-Performance Interconnects, (IEEE, 2017), pp. 25–28.

Black, L.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Boeuf, F.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Bohr, M.

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Brad, S.

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Brandli, M.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Broussous, L.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Brown, D.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Bruck, R.

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S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

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S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Chowdhury, M.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Chudzik, M.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Chung, S.

S. Chung, H. Abediasl, and H. Hashemi, “A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS,” IEEE Journal of Solid-State Circuits 53(1), 275–296 (2018).
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Clark, A.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Cook, H.

Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun, V. Stojanović, and K. Asanović, “A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators,” in, Proceedings of IEEE European Solid State Circuits Conference, (IEEE, 2014), pp. 199–202.

Cook, H. M.

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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Corliss, D.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Costrini, G.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Cremer, S.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Crouse, M.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Cucci, B.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Dahl, A.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Dai, M.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Dang, D.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

De Cea Falco, M.

M. De Cea Falco, A. Atabaki, L. Alloatti, M. Wade, M. Popovic, and R. Ram, “A Thin Silicon Photonic Platform for Telecommunication Wavelengths,” in European Conference on Optical Communication, (2017), pp. SC2.25.

De Coster, J.

M. Pantouvaki, P. De Heyn, R. Michal, P. Verheyen, S. Brad, A. Srinivasan, H. Chen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “50Gb/s Silicon Photonics Platform for Short-Reach Optical Interconnects,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2016), paper Th4H.4.

M. Rakowski, M. Pantouvaki, P. Verheyen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “A 50Gb/s, 610fJ/bit hybrid CMOS-Si photonics ring-based NRZ-OOK transmitter,” in Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

De Dobbelaere, P.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

De Heyn, P.

M. Pantouvaki, P. De Heyn, R. Michal, P. Verheyen, S. Brad, A. Srinivasan, H. Chen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “50Gb/s Silicon Photonics Platform for Short-Reach Optical Interconnects,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2016), paper Th4H.4.

De Koninck, Y.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Delpech, P.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Denton, S.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Dimitrakopoulos, C.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Ding, R.

H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. Baehr-Jones, M. Fiorentino, M. Hochberg, S. Palermo, and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE Journal of Solid-State Circuits 50(12), 3145–3159 (2015).
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Ding, Y.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Divakaruni, R.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Doan, T.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Doany, F.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Domenicucci, A.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Donaton, R.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Dotson, J.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Durand, C.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Dyer, S. D.

Edelstein, D.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Edge, L.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Eker, M.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Ellis-Monaghan, J.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

El-Mansy, Y.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
[Crossref]

Engelmann, S.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Farcy, A.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Fathpour, S.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Feilchenfeld, N. B.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Ferrario, J.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Fiorentino, M.

K. Yu, C. Li, H. Li, A. Titriku, A. Shafik, B. Wang, Z. Wang, R. Bai, C. H. Chen, M. Fiorentino, P. Y. Chiang, and S. Palermo, “A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization,” IEEE Journal of Solid-State Circuits 51(9), 2129–2141 (2016).
[Crossref]

H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. Baehr-Jones, M. Fiorentino, M. Hochberg, S. Palermo, and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE Journal of Solid-State Circuits 50(12), 3145–3159 (2015).
[Crossref]

Fisher, P.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Foltz, D.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Fonseca, C.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Fourel, M.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Francese, P. A.

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S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Frye, A.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Gabor, A.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Gal, T.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Gates, S.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Gentry, C. M.

C. M. Gentry, J. M. Shainline, M. T. Wade, M. J. Stevens, S. D. Dyer, X. Zeng, F. Pavanello, T. Gerrits, S. W. Nam, R. P. Mirin, and M. A. Popović, “Quantum-correlated photon pairs generated in a commercial 45 nm complementary metal-oxide semiconductor microelectronic chip,” Optica 2, 1065–1071 (2015).
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M. T. Wade, F. Pavanello, R. Kumar, C. M. Gentry, A. Atabaki, R. Ram, V. Stojanović, and M. A. Popović, “75% efficient wide bandwidth grating couplers in a 45nm microelectronics CMOS process,” in Proceedings of IEEE Optical Interconnects Conference (IEEE, 2015), pp. 46–47.

Georgas, M.

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Georgas, M. S.

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Ghani, T.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Ghilioni, A.

E. Temporiti, G. Minoia, M. Repossi, D. Baldi, A. Ghilioni, and F. Svelto, “A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies,” in, Proceedings of IEEE International Solid-State Circuits Conference, (IEEE, 2016), pp. 404–405.

Gill, D. M.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Glass, G.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Gleeson, M. A.

M. Iqbal, M. A. Gleeson, B. Spaugh, F. Tybor, W. G. Gunn, M. Hochberg, T. Baehr-Jones, R. C. Bailey, and L. C. Gunn, “Label-Free Biosensor Arrays Based on Silicon Ring Resonators and High-Speed Optical Scanning Instrumentation,” IEEE Journal of Selected Topics in Quantum Electronics 16(3), 654–661 (2010).
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Gloeckner, S.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Gloria, D.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Gordon, M.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Gourhant, O.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Gourvest, E.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Greco, S.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Green, W. M. J.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Greene, B.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Gribelyuk, M.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Grill, A.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Grunow, S.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Guckenberger, D.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Guillermet, M.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Gunn, C.

C. Gunn, “CMOS Photonics for High-Speed Interconnects,” IEEE Micro 26(2), 58–66 (2006).
[Crossref]

Gunn, L. C.

M. Iqbal, M. A. Gleeson, B. Spaugh, F. Tybor, W. G. Gunn, M. Hochberg, T. Baehr-Jones, R. C. Bailey, and L. C. Gunn, “Label-Free Biosensor Arrays Based on Silicon Ring Resonators and High-Speed Optical Scanning Instrumentation,” IEEE Journal of Selected Topics in Quantum Electronics 16(3), 654–661 (2010).
[Crossref]

Gunn, W. G.

M. Iqbal, M. A. Gleeson, B. Spaugh, F. Tybor, W. G. Gunn, M. Hochberg, T. Baehr-Jones, R. C. Bailey, and L. C. Gunn, “Label-Free Biosensor Arrays Based on Silicon Ring Resonators and High-Speed Optical Scanning Instrumentation,” IEEE Journal of Selected Topics in Quantum Electronics 16(3), 654–661 (2010).
[Crossref]

Guo, D.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Gutierrez, S.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Haensch, W.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Han, J. P.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Hargrove, M.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Harley, E. C. T.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Harrison, M.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Hashemi, H.

S. Chung, H. Abediasl, and H. Hashemi, “A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS,” IEEE Journal of Solid-State Circuits 53(1), 275–296 (2018).
[Crossref]

Haxaire, K.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Hedges, C.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Henson, W.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Hochberg, M.

H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. Baehr-Jones, M. Fiorentino, M. Hochberg, S. Palermo, and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE Journal of Solid-State Circuits 50(12), 3145–3159 (2015).
[Crossref]

M. Iqbal, M. A. Gleeson, B. Spaugh, F. Tybor, W. G. Gunn, M. Hochberg, T. Baehr-Jones, R. C. Bailey, and L. C. Gunn, “Label-Free Biosensor Arrays Based on Silicon Ring Resonators and High-Speed Optical Scanning Instrumentation,” IEEE Journal of Selected Topics in Quantum Electronics 16(3), 654–661 (2010).
[Crossref]

Hoffman, T.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
[Crossref]

Hofrichter, J.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Holt, J.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Hon, K.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Hon, N. K.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Horst, F.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Hu, Y.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Iijima, R.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Ingram, R.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Inumiya, S.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Ioannou, D.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Iqbal, M.

M. Iqbal, M. A. Gleeson, B. Spaugh, F. Tybor, W. G. Gunn, M. Hochberg, T. Baehr-Jones, R. C. Bailey, and L. C. Gunn, “Label-Free Biosensor Arrays Based on Silicon Ring Resonators and High-Speed Optical Scanning Instrumentation,” IEEE Journal of Selected Topics in Quantum Electronics 16(3), 654–661 (2010).
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Ivers, T.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Jackson, S.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Jaeger, D.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Jagannathan, H.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Jan, C. H.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
[Crossref]

Jan, S.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Jeng, S. J.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Johnson, J.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Joseph, E.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Karve, G.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Kelling, M.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Kenyon, C.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
[Crossref]

Kerber, A.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Khare, M.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Khater, M.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Khauv, K.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Kiewra, E.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Kim, B.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Klaus, J.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Knoll, D.

L. Zimmermann, D. Knoll, M. Kroh, S. Lischke, D. Petousi, G. Winzer, and Y. Yamamoto, “BiCMOS Silicon Photonics Platform,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2015), paper Th4E.5.

Kossel, M.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Koumans, R.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Krishnamoorthy, A. V.

J. F. Buckwalter, X. Zheng, G. Li, K. Raj, and A. V. Krishnamoorthy, “A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process,” IEEE Journal of Solid-State Circuits 47(6), 1309–1322 (2012).
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Krishnan, S.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Kroh, M.

L. Zimmermann, D. Knoll, M. Kroh, S. Lischke, D. Petousi, G. Winzer, and Y. Yamamoto, “BiCMOS Silicon Photonics Platform,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2015), paper Th4E.5.

Kucharski, D.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Kuchta, D.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Kuhn, K.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Kull, L.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Kumar, R.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
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C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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M. T. Wade, F. Pavanello, R. Kumar, C. M. Gentry, A. Atabaki, R. Ram, V. Stojanović, and M. A. Popović, “75% efficient wide bandwidth grating couplers in a 45nm microelectronics CMOS process,” in Proceedings of IEEE Optical Interconnects Conference (IEEE, 2015), pp. 46–47.

M. T. Wade, F. Pavanello, J. Orcutt, R. Kumar, J. M. Shainline, V. Stojanović, R. Ram, and M. A. Popović, “Scaling zero-change photonics: An active photonics platform in a 32nm microelectronics SOI CMOS process,” in Proceedings of Conference on Lasers and Electro-Optics (2015), pp. 1–2.

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanović, and M. A. Popović, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2014), pp. 1–3.

Kwon, U.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Landers, W.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Larosa, G.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Lea, D.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Leap, K.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Leblebici, Y.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Lee, B.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Lee, J. H.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Lee, M. H.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Lee, Y.

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun, V. Stojanović, and K. Asanović, “A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators,” in, Proceedings of IEEE European Solid State Circuits Conference, (IEEE, 2014), pp. 199–202.

Le-Friec, Y.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Leidy, R.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Lepage, G.

M. Pantouvaki, P. De Heyn, R. Michal, P. Verheyen, S. Brad, A. Srinivasan, H. Chen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “50Gb/s Silicon Photonics Platform for Short-Reach Optical Interconnects,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2016), paper Th4H.4.

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Leu, J.

C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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Leu, J. C.

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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Leverd, F.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Li, C.

K. Yu, C. Li, H. Li, A. Titriku, A. Shafik, B. Wang, Z. Wang, R. Bai, C. H. Chen, M. Fiorentino, P. Y. Chiang, and S. Palermo, “A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization,” IEEE Journal of Solid-State Circuits 51(9), 2129–2141 (2016).
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H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. Baehr-Jones, M. Fiorentino, M. Hochberg, S. Palermo, and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE Journal of Solid-State Circuits 50(12), 3145–3159 (2015).
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Li, G.

J. F. Buckwalter, X. Zheng, G. Li, K. Raj, and A. V. Krishnamoorthy, “A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process,” IEEE Journal of Solid-State Circuits 47(6), 1309–1322 (2012).
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Li, H.

K. Yu, C. Li, H. Li, A. Titriku, A. Shafik, B. Wang, Z. Wang, R. Bai, C. H. Chen, M. Fiorentino, P. Y. Chiang, and S. Palermo, “A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization,” IEEE Journal of Solid-State Circuits 51(9), 2129–2141 (2016).
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H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. Baehr-Jones, M. Fiorentino, M. Hochberg, S. Palermo, and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE Journal of Solid-State Circuits 50(12), 3145–3159 (2015).
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J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Li, J. Sun, M. Weaver, S. Urošević, M. Popović, R. J. Ram, and V. Stojanović, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20(11), 12222–12232 (2012).
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Li, Y.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Liang, Y.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Libsch, F.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Lin, S.

S. Moazeni, S. Lin, M. Wade, L. Alloatti, R. Ram, M. Popović, and V. Stojanović, “A 40Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45nm SOI CMOS,” IEEE Journal of Solid-State Circuits 52(12), 3503–3516 (2017).
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S. Lin, S. Moazeni, K. T. Settaluri, and V. Stojanović, “Electronic-Photonic Co-Optimization of High-Speed Silicon Photonic Transmitters,” IEEE Journal of Lightwave Technology 35(21), 4766–4780 (2017).
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C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
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C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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N. Mehta, C. Sun, M. Wade, S. Lin, M. Popović, and V. Stojanović, “A 12Gb/s, 8.6 µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process,” in Proceedings of IEEE European Solid-State Circuits Conference (IEEE, 2016), pp. 491–494.

M. S. Akhter, P. Somogyi, C. Sun, M. Wade, R. Meade, P. Bhargava, S. Lin, and N. Mehta, “WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers,” in, Proceedings of IEEE Symposium on High-Performance Interconnects, (IEEE, 2017), pp. 25–28.

S. Moazeni, A. Atabaki, D. Cheian, S. Lin, R. J. Ram, and V. Stojanović, “Monolithic Integration of O-band Photonic Transceivers in a “Zero-change” 32nm SOI CMOS,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 24.3.

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Liu, X.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Liu, Y.

H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. Baehr-Jones, M. Fiorentino, M. Hochberg, S. Palermo, and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE Journal of Solid-State Circuits 50(12), 3145–3159 (2015).
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Luning, S.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Lustig, N.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Luu, D.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Ma, Zhiyong

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Mack, M.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Maling, J.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Manouvrier, J. R.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Martin, Y.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Masini, G.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

McConnell, R.

K. K. Mehta, C. D. Bruzewicz, R. McConnell, R. J. Ram, J. M. Sage, and J. Chiaverini, “Integrated optical addressing of an ion qubit,” Nature Nanotechnology 11(12), 1066–1070 (2016).
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McGee, G.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Mcintyre, B.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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McKnight, A.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

McLean, K.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Mcstay, K.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Meade, R.

C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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M. S. Akhter, P. Somogyi, C. Sun, M. Wade, R. Meade, P. Bhargava, S. Lin, and N. Mehta, “WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers,” in, Proceedings of IEEE Symposium on High-Performance Interconnects, (IEEE, 2017), pp. 25–28.

Meer, H. Van

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Meghelli, M.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Mehta, K.

C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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Mehta, K. K.

K. K. Mehta, C. D. Bruzewicz, R. McConnell, R. J. Ram, J. M. Sage, and J. Chiaverini, “Integrated optical addressing of an ion qubit,” Nature Nanotechnology 11(12), 1066–1070 (2016).
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Mehta, N.

M. S. Akhter, P. Somogyi, C. Sun, M. Wade, R. Meade, P. Bhargava, S. Lin, and N. Mehta, “WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers,” in, Proceedings of IEEE Symposium on High-Performance Interconnects, (IEEE, 2017), pp. 25–28.

N. Mehta, C. Sun, M. Wade, S. Lin, M. Popović, and V. Stojanović, “A 12Gb/s, 8.6 µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process,” in Proceedings of IEEE European Solid-State Circuits Conference (IEEE, 2016), pp. 491–494.

Mekis, A.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Meng, H.

A. H. Atabaki, H. Meng, L. Alloatti, and R. J. Ram, “High-speed polysilicon CMOS photodetector for telecom and datacom,” Appl. Phys. Lett. 109(11), 111106 (2016).
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Menolfi, C.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Michal, R.

M. Pantouvaki, P. De Heyn, R. Michal, P. Verheyen, S. Brad, A. Srinivasan, H. Chen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “50Gb/s Silicon Photonics Platform for Short-Reach Optical Interconnects,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2016), paper Th4H.4.

Miller, D.

C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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Milton, P.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Minoia, G.

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Mirsaidi, S.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Mistry, K.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Moazeni, S.

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Moss, B.

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Moss, B. R.

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Moumen, N.

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Murthy, A.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Na, M. H.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Nagisetty, R.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Nair, D.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Nam, S. W.

Nammari, K.

C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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Narasimha, A.

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Narasimha, S.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Narayanan, V.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Nayfeh, H. M.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Nguyen, Phi

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Nicewicz, M.

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Nicholson, L.

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Nielsen, D.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Norum, J.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Notaros, J.

J. Notaros, F. Pavanello, M. T. Wade, C. M. Gentry, A. Atabaki, L. Alloatti, R. J. Ram, and M. A. Popović, “Ultra-efficient CMOS fiber-to-chip grating couplers,” in Proceedings of Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

Nummy, K.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Obradovic, B.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Offrein, B.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Onishi, K.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Ontalus, V.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Orcutt, J.

C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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Orcutt, J. S.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
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Orlando, B.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Ostermayr, M.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Ou, A. J.

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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Ouyang, C.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Ouyang, X.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Ozkaya, I.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

Pal, R.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

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Palermo, S.

K. Yu, C. Li, H. Li, A. Titriku, A. Shafik, B. Wang, Z. Wang, R. Bai, C. H. Chen, M. Fiorentino, P. Y. Chiang, and S. Palermo, “A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization,” IEEE Journal of Solid-State Circuits 51(9), 2129–2141 (2016).
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P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Pantouvaki, M.

M. Rakowski, M. Pantouvaki, P. Verheyen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “A 50Gb/s, 610fJ/bit hybrid CMOS-Si photonics ring-based NRZ-OOK transmitter,” in Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

M. Pantouvaki, P. De Heyn, R. Michal, P. Verheyen, S. Brad, A. Srinivasan, H. Chen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “50Gb/s Silicon Photonics Platform for Short-Reach Optical Interconnects,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2016), paper Th4H.4.

Park, D. G.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Paruchuri, V.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Pavanello, F.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
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C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
[Crossref] [PubMed]

C. M. Gentry, J. M. Shainline, M. T. Wade, M. J. Stevens, S. D. Dyer, X. Zeng, F. Pavanello, T. Gerrits, S. W. Nam, R. P. Mirin, and M. A. Popović, “Quantum-correlated photon pairs generated in a commercial 45 nm complementary metal-oxide semiconductor microelectronic chip,” Optica 2, 1065–1071 (2015).
[Crossref]

M. T. Wade, F. Pavanello, J. Orcutt, R. Kumar, J. M. Shainline, V. Stojanović, R. Ram, and M. A. Popović, “Scaling zero-change photonics: An active photonics platform in a 32nm microelectronics SOI CMOS process,” in Proceedings of Conference on Lasers and Electro-Optics (2015), pp. 1–2.

J. Notaros, F. Pavanello, M. T. Wade, C. M. Gentry, A. Atabaki, L. Alloatti, R. J. Ram, and M. A. Popović, “Ultra-efficient CMOS fiber-to-chip grating couplers,” in Proceedings of Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

M. T. Wade, F. Pavanello, R. Kumar, C. M. Gentry, A. Atabaki, R. Ram, V. Stojanović, and M. A. Popović, “75% efficient wide bandwidth grating couplers in a 45nm microelectronics CMOS process,” in Proceedings of IEEE Optical Interconnects Conference (IEEE, 2015), pp. 46–47.

Pelissier-Tanon, D.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Peterson, M.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Petiton, H.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Petousi, D.

L. Zimmermann, D. Knoll, M. Kroh, S. Lischke, D. Petousi, G. Winzer, and Y. Yamamoto, “BiCMOS Silicon Photonics Platform,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2015), paper Th4E.5.

Pham, T.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Pinguet, T.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Pinzelli, L.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Planchon, L.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Popovic, M.

S. Moazeni, S. Lin, M. Wade, L. Alloatti, R. Ram, M. Popović, and V. Stojanović, “A 40Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45nm SOI CMOS,” IEEE Journal of Solid-State Circuits 52(12), 3503–3516 (2017).
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C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
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C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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L. Alloatti, M. Wade, V. Stojanović, M. Popović, and R. J. Ram, “Photonics design tool for advanced CMOS nodes,” IET Optoelectronics 9(4), 163–167 (2015).
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J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Li, J. Sun, M. Weaver, S. Urošević, M. Popović, R. J. Ram, and V. Stojanović, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20(11), 12222–12232 (2012).
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N. Mehta, C. Sun, M. Wade, S. Lin, M. Popović, and V. Stojanović, “A 12Gb/s, 8.6 µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process,” in Proceedings of IEEE European Solid-State Circuits Conference (IEEE, 2016), pp. 491–494.

M. De Cea Falco, A. Atabaki, L. Alloatti, M. Wade, M. Popovic, and R. Ram, “A Thin Silicon Photonic Platform for Telecommunication Wavelengths,” in European Conference on Optical Communication, (2017), pp. SC2.25.

Popovic, M. A.

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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C. M. Gentry, J. M. Shainline, M. T. Wade, M. J. Stevens, S. D. Dyer, X. Zeng, F. Pavanello, T. Gerrits, S. W. Nam, R. P. Mirin, and M. A. Popović, “Quantum-correlated photon pairs generated in a commercial 45 nm complementary metal-oxide semiconductor microelectronic chip,” Optica 2, 1065–1071 (2015).
[Crossref]

J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanović, and M. A. Popović, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38(15), 2657–2659 (2013).
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M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanović, and M. A. Popović, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2014), pp. 1–3.

J. Notaros, F. Pavanello, M. T. Wade, C. M. Gentry, A. Atabaki, L. Alloatti, R. J. Ram, and M. A. Popović, “Ultra-efficient CMOS fiber-to-chip grating couplers,” in Proceedings of Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

M. T. Wade, F. Pavanello, J. Orcutt, R. Kumar, J. M. Shainline, V. Stojanović, R. Ram, and M. A. Popović, “Scaling zero-change photonics: An active photonics platform in a 32nm microelectronics SOI CMOS process,” in Proceedings of Conference on Lasers and Electro-Optics (2015), pp. 1–2.

M. T. Wade, F. Pavanello, R. Kumar, C. M. Gentry, A. Atabaki, R. Ram, V. Stojanović, and M. A. Popović, “75% efficient wide bandwidth grating couplers in a 45nm microelectronics CMOS process,” in Proceedings of IEEE Optical Interconnects Conference (IEEE, 2015), pp. 46–47.

Porth, B.

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Prakash, D. P.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

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Proesel, J.

A. Cevrero, I. Ozkaya, P. A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, and T. Toifl, “A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2017), pp. 482–483.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Qi, N.

H. Li, Z. Xuan, A. Titriku, C. Li, K. Yu, B. Wang, A. Shafik, N. Qi, Y. Liu, R. Ding, T. Baehr-Jones, M. Fiorentino, M. Hochberg, S. Palermo, and P. Y. Chiang, “A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS,” IEEE Journal of Solid-State Circuits 50(12), 3145–3159 (2015).
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Quemerais, T.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Raj, K.

J. F. Buckwalter, X. Zheng, G. Li, K. Raj, and A. V. Krishnamoorthy, “A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process,” IEEE Journal of Solid-State Circuits 47(6), 1309–1322 (2012).
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Rakowski, M.

M. Rakowski, M. Pantouvaki, P. Verheyen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “A 50Gb/s, 610fJ/bit hybrid CMOS-Si photonics ring-based NRZ-OOK transmitter,” in Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

Ram, R.

S. Moazeni, S. Lin, M. Wade, L. Alloatti, R. Ram, M. Popović, and V. Stojanović, “A 40Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45nm SOI CMOS,” IEEE Journal of Solid-State Circuits 52(12), 3503–3516 (2017).
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C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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M. T. Wade, F. Pavanello, R. Kumar, C. M. Gentry, A. Atabaki, R. Ram, V. Stojanović, and M. A. Popović, “75% efficient wide bandwidth grating couplers in a 45nm microelectronics CMOS process,” in Proceedings of IEEE Optical Interconnects Conference (IEEE, 2015), pp. 46–47.

M. T. Wade, F. Pavanello, J. Orcutt, R. Kumar, J. M. Shainline, V. Stojanović, R. Ram, and M. A. Popović, “Scaling zero-change photonics: An active photonics platform in a 32nm microelectronics SOI CMOS process,” in Proceedings of Conference on Lasers and Electro-Optics (2015), pp. 1–2.

M. De Cea Falco, A. Atabaki, L. Alloatti, M. Wade, M. Popovic, and R. Ram, “A Thin Silicon Photonic Platform for Telecommunication Wavelengths,” in European Conference on Optical Communication, (2017), pp. SC2.25.

Ram, R. J.

A. H. Atabaki, H. Meng, L. Alloatti, and R. J. Ram, “High-speed polysilicon CMOS photodetector for telecom and datacom,” Appl. Phys. Lett. 109(11), 111106 (2016).
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L. Alloatti, D. Cheian, and R. J. Ram, “High-speed modulator with interleaved junctions in zero-change CMOS photonics,” Appl. Phys. Lett. 108(13), 131101 (2016).
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K. K. Mehta, C. D. Bruzewicz, R. McConnell, R. J. Ram, J. M. Sage, and J. Chiaverini, “Integrated optical addressing of an ion qubit,” Nature Nanotechnology 11(12), 1066–1070 (2016).
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C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
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L. Alloatti, M. Wade, V. Stojanović, M. Popović, and R. J. Ram, “Photonics design tool for advanced CMOS nodes,” IET Optoelectronics 9(4), 163–167 (2015).
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C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanović, and M. A. Popović, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38(15), 2657–2659 (2013).
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J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Li, J. Sun, M. Weaver, S. Urošević, M. Popović, R. J. Ram, and V. Stojanović, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20(11), 12222–12232 (2012).
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S. Moazeni, A. Atabaki, D. Cheian, S. Lin, R. J. Ram, and V. Stojanović, “Monolithic Integration of O-band Photonic Transceivers in a “Zero-change” 32nm SOI CMOS,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 24.3.

J. Notaros, F. Pavanello, M. T. Wade, C. M. Gentry, A. Atabaki, L. Alloatti, R. J. Ram, and M. A. Popović, “Ultra-efficient CMOS fiber-to-chip grating couplers,” in Proceedings of Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanović, and M. A. Popović, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2014), pp. 1–3.

L. Alloatti and R. J. Ram, “Resonance-enhanced waveguide-coupled silicon-germanium detector,” arXiv preprint arXiv:1601.00542 (2016).

Rausch, W.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Reinholm, C.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Repossi, M.

E. Temporiti, G. Minoia, M. Repossi, D. Baldi, A. Ghilioni, and F. Svelto, “A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies,” in, Proceedings of IEEE International Solid-State Circuits Conference, (IEEE, 2016), pp. 404–405.

Restaino, D.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Richard, C.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Rines, D.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Ristoiu, D.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Robertson, K.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Robinson, C.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Robinson, J. T.

Rosenberg, J. C.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Rudnick, N.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Sacher, W. D.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

Sadagopan, V.

A. Narasimha, B. Analui, E. Balmater, A. Clark, T. Gal, D. Guckenberger, S. Gutierrez, M. Harrison, R. Ingram, R. Koumans, D. Kucharski, K. Leap, Y. Liang, A. Mekis, S. Mirsaidi, M. Peterson, T. Pham, T. Pinguet, D. Rines, V. Sadagopan, T. J. Sleboda, D. Song, Y. Wang, B. Welch, J. Witzens, S. Abdalla, S. Gloeckner, and P. De Dobbelaere, “A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13 µm CMOS Silicon-on-Insulator Technology,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2008), pp. 1–3.

Sage, J. M.

K. K. Mehta, C. D. Bruzewicz, R. McConnell, R. J. Ram, J. M. Sage, and J. Chiaverini, “Integrated optical addressing of an ion qubit,” Nature Nanotechnology 11(12), 1066–1070 (2016).
[PubMed]

Sahn, S.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Sahni, S.

P. De Dobbelaere, A. Dahl, A. Mekis, B. Chase, B. Weber, B. Welch, D. Foltz, G. Armijo, G. Masini, G. McGee, G. Wong, J. Balardeta, J. Dotson, J. Schramm, K. Hon, K. Khauv, K. Robertson, K. Stechschulte, K. Yokoyama, L. Planchon, L. Tullgren, M. Eker, M. Mack, M. Peterson, N. Rudnick, P. Milton, P. Sun, R. Bruck, R. Zhou, S. Denton, S. Fathpour, S. Gloeckner, S. Jackson, S. Pang, S. Sahni, S. Wang, S. Yu, T. Pinguet, Y. De Koninck, Y. Chi, and Y. Liang, “Advanced Silicon Photonics Technology Platform Leveraging a Semiconductor Supply Chain,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2017), paper 34.1.

Salager, L.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Samavedam, S.

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Sanchez, Y.

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Sandhu, G.

C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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Sankaran, S.

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Saroop, S.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Sautreuil, B.

F. Boeuf, S. Cremer, N. Vulliet, T. Pinguet, A. Mekis, G. Masini, L. Verslegers, P. Sun, A. Ayazi, N. K. Hon, S. Sahn, Y. Chi, B. Orlando, D. Ristoiu, A. Farcy, F. Leverd, L. Broussous, D. Pelissier-Tanon, C. Richard, L. Pinzelli, R. Beneyton, O. Gourhant, E. Gourvest, Y. Le-Friec, D. Monnier, P. Brun, M. Guillermet, D. Benoit, K. Haxaire, J. R. Manouvrier, S. Jan, H. Petiton, J. F. Carpentier, T. Quemerais, C. Durand, D. Gloria, M. Fourel, F. Battegay, Y. Sanchez, E. Batail, F. Baron, P. Delpech, L. Salager, P. De Dobbelaere, and B. Sautreuil, “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications,” in Proceedings of IEEE International Electron Devices Meeting (IEEE, 2013), pp. 13.3.1–13.3.4.

Schaeffer, J.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

Schepis, D.

S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M. H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, D. Guo, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J. H. Lee, M. Ostermayr, J. P. Han, Y. Hu, M. Gribelyuk, D. G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2011), pp. 28.1.1–28.1.4.

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M. Georgas, J. Leu, B. Moss, C. Sun, and V. Stojanović, “Addressing link-level design tradeoffs for integrated photonic interconnects,” in Proceedings of IEEE Custom Integrated Circuits Conference (IEEE, 2011), pp. 1–8.

N. Mehta, C. Sun, M. Wade, S. Lin, M. Popović, and V. Stojanović, “A 12Gb/s, 8.6 µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process,” in Proceedings of IEEE European Solid-State Circuits Conference (IEEE, 2016), pp. 491–494.

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C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. H. Atabaki, F. Pavanello, J. M. Shainline, J. S. Orcutt, R. J. Ram, M. Popović, and V. Stojanović, “A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning,” IEEE Journal of Solid-State Circuits 51(4), 893–907 (2016).
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S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Tehar-Zahav, O.

C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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Temporiti, E.

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Thompson, S. E.

S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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Tian, C.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Tian, X.

N. B. Feilchenfeld, F. G. Anderson, T. Barwicz, S. Chilstedt, Y. Ding, J. Ellis-Monaghan, D. M. Gill, C. Hedges, J. Hofrichter, F. Horst, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean, M. Nicewicz, J. S. Orcutt, B. Porth, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci, D. Dang, T. Doan, F. Doany, S. Engelmann, M. Gordon, E. Joseph, J. Maling, S. Shank, X. Tian, C. Willets, J. Ferrario, M. Meghelli, F. Libsch, B. Offrein, W. M. J. Green, and W. Haensch, “An integrated silicon photonics technology for O-band datacom,” in, Proceedings of IEEE International Electron Devices Meeting, (IEEE, 2015), pp. 25.7.1–25.7.4.

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C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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Titriku, A.

K. Yu, C. Li, H. Li, A. Titriku, A. Shafik, B. Wang, Z. Wang, R. Bai, C. H. Chen, M. Fiorentino, P. Y. Chiang, and S. Palermo, “A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization,” IEEE Journal of Solid-State Circuits 51(9), 2129–2141 (2016).
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S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Zhiyong Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, Phi Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Transactions on Electron Devices 51(11), 1790–1797 (2004).
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M. Iqbal, M. A. Gleeson, B. Spaugh, F. Tybor, W. G. Gunn, M. Hochberg, T. Baehr-Jones, R. C. Bailey, and L. C. Gunn, “Label-Free Biosensor Arrays Based on Silicon Ring Resonators and High-Speed Optical Scanning Instrumentation,” IEEE Journal of Selected Topics in Quantum Electronics 16(3), 654–661 (2010).
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Van Den Nieuwenhuizen, R.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Vayshenker, A.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Verheyen, P.

M. Pantouvaki, P. De Heyn, R. Michal, P. Verheyen, S. Brad, A. Srinivasan, H. Chen, J. De Coster, G. Lepage, P. Absil, and J. Van Campenhout, “50Gb/s Silicon Photonics Platform for Short-Reach Optical Interconnects,” in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2016), paper Th4H.4.

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Wachnik, R.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

Wade, M.

S. Moazeni, S. Lin, M. Wade, L. Alloatti, R. Ram, M. Popović, and V. Stojanović, “A 40Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45nm SOI CMOS,” IEEE Journal of Solid-State Circuits 52(12), 3503–3516 (2017).
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L. Alloatti, M. Wade, V. Stojanović, M. Popović, and R. J. Ram, “Photonics design tool for advanced CMOS nodes,” IET Optoelectronics 9(4), 163–167 (2015).
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C. Sun, M. Georgas, J. Orcutt, B. Moss, Y. H. Chen, J. Shainline, M. Wade, K. Mehta, K. Nammari, E. Timurdogan, D. Miller, O. Tehar-Zahav, Z. Sternberg, J. Leu, J. Chong, R. Bafrali, G. Sandhu, M. Watts, R. Meade, M. Popović, R. Ram, and V. Stojanović, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS,” IEEE Journal of Solid-State Circuits 50(4), 828–844 (2015).
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M. De Cea Falco, A. Atabaki, L. Alloatti, M. Wade, M. Popovic, and R. Ram, “A Thin Silicon Photonic Platform for Telecommunication Wavelengths,” in European Conference on Optical Communication, (2017), pp. SC2.25.

N. Mehta, C. Sun, M. Wade, S. Lin, M. Popović, and V. Stojanović, “A 12Gb/s, 8.6 µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process,” in Proceedings of IEEE European Solid-State Circuits Conference (IEEE, 2016), pp. 491–494.

M. S. Akhter, P. Somogyi, C. Sun, M. Wade, R. Meade, P. Bhargava, S. Lin, and N. Mehta, “WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers,” in, Proceedings of IEEE Symposium on High-Performance Interconnects, (IEEE, 2017), pp. 25–28.

Wade, M. T.

C. Sun, M. T. Wade, Y. Lee, J. S. Orcutt, L. Alloatti, M. S. Georgas, A. S. Waterman, J. M. Shainline, R. R. Avizienis, S. Lin, B. R. Moss, R. Kumar, F. Pavanello, A. Atabaki, H. M. Cook, A. J. Ou, J. C. Leu, Y.-H. Chen, K. Asanović, R. J. Ram, M. A. Popović, and V. M. Stojanović, “Single-chip microprocessor that communicates directly using light,” Nature 528(7583), 534–538 (2015).
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C. M. Gentry, J. M. Shainline, M. T. Wade, M. J. Stevens, S. D. Dyer, X. Zeng, F. Pavanello, T. Gerrits, S. W. Nam, R. P. Mirin, and M. A. Popović, “Quantum-correlated photon pairs generated in a commercial 45 nm complementary metal-oxide semiconductor microelectronic chip,” Optica 2, 1065–1071 (2015).
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J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanović, and M. A. Popović, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38(15), 2657–2659 (2013).
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M. T. Wade, F. Pavanello, R. Kumar, C. M. Gentry, A. Atabaki, R. Ram, V. Stojanović, and M. A. Popović, “75% efficient wide bandwidth grating couplers in a 45nm microelectronics CMOS process,” in Proceedings of IEEE Optical Interconnects Conference (IEEE, 2015), pp. 46–47.

J. Notaros, F. Pavanello, M. T. Wade, C. M. Gentry, A. Atabaki, L. Alloatti, R. J. Ram, and M. A. Popović, “Ultra-efficient CMOS fiber-to-chip grating couplers,” in Proceedings of Optical Fiber Communications Conference, OSA Technical Digest (online) (Optical Society of America, 2016), pp. 1–3.

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S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

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S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Y. S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” in, Proceedings of International Electron Devices Meeting, (IEEE, 2006), pp. 1–4.

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Figures (7)

Fig. 1
Fig. 1 The comparison of fT for IBM/GlobalFoundries CMOS processes. [8–10]
Fig. 2
Fig. 2 45nm SOI CMOS process cross-section with relevant devices [From Sun et al., JSSC. 50, 893 (2016)].
Fig. 3
Fig. 3 “Zero-change” SOI platform evolution; (a) Development timeline, (b) EOS22 die photo, (c) WDM transceivers, (d) Key photonic devices of an optical link.
Fig. 4
Fig. 4 (a) 3D layout of a unidirectional grating coupler, (b) Optical transmission at 10.5 degree vertical angle.
Fig. 5
Fig. 5 (a) 3D layout of a spoked-ring modulator [From Moazeni et al., JSSC. 52, 3503 (2017)], (b) Optical transmission of a WDM transmitter row with 11 channels (numbers indicate channel ordering) over 3.2 THz FSR from EOS24 chip. Channel 3’s heater is turned on by 20% strength to show the individual resonance tuning functionality.
Fig. 6
Fig. 6 Photodetectors in “zero-change” platforms: (a) PMOS cross-sections in 45nm and 32nm processes and their features used for O-band light detection, (b) 3D layout of a resonant SiGe PD, (c) and (d) Micrograph and cross-section of the defect-based resonant PD for L-band.
Fig. 7
Fig. 7 40 Gb/s NRZ and PAM4 transmitters results: (a) Micrograph of the 40 Gb/s NRZ transmitter, (b) Total area and energy breakdown for 40 Gb/s transmitter, eye-diagram, NRZ (c) NRZ (d) PAM4 eye-diagram.

Tables (3)

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Table 1 Summary and comparison of non-monolithic silicon photonic platforms.

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Table 2 Summary and comparison of monolithic silicon photonic platforms.

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Table 3 Photonic devices performance summary.

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