We develop a computational framework to study the impact of burst assembly algorithms on the byte loss rate (ByLR) of an OBS network under bursty (ON–OFF) IP traffic input. First we propose a computational method to analyze the characteristics of assembled bursts in terms of burst length and/or burst assembly time distribution under timer-based, burst-threshold-based, and dual-threshold-based burst assemblers. The unique feature of our analytical model is that it can capture the effect of source burst duration (average ON time) on the statistical characteristics of the assembled bursts for all the aforesaid burst assemblers. We then derive the expressions for ByLR for these assembly schemes using the characteristics of assembled bursts as obtained above. This enables us to compare the performance of the burst assemblers under identical traffic scenarios and the impact of source burst duration on loss for each of the above assembly schemes. To our knowledge, such an analytical scheme is not yet available. Using the framework, we also illustrate the loss surfaces for each of the above assembly schemes against load-correlation axes. We also demonstrate how to obtain constant loss contours on the load-correlation plane of a parameterized burst assembler so that the result can be used to dynamically adapt the assembly parameters. The results show that the ByLR increases with an increase in the source burst duration for all the above-mentioned assemblers, but the rate of increase is the least in the case of the burst-threshold-based assembler. It is also observed that the ByLR for the timer-based assembler is the highest and that for the burst-threshold-based assembler is the lowest under identical traffic and latency scenarios.
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