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Abstract
In this work, we have proposed two different designs to improve the efficiency of a graphene-based electro-absorption modulator. The efficiency of the modulator is enhanced by increasing the overlap between the graphene layer and the optical mode of the waveguide. This is achieved by introducing the graphene layer between the silicon nitride cap and silicon waveguide. Using a single monolayer graphene configuration, a switching energy of 3.22 fJ/bit and maximum operating bandwidth of 10.89 GHz is achieved whereas the double monolayer graphene configuration allowed us to achieve a switching energy of 4.26 fJ/bit with a large operating bandwidth of 34 GHz at λ=1550 nm. Low energy consumption coupled with high bandwidth makes these modulator designs a potential candidate for use in on-chip optical communication.
© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
In this era of digitalization where internet and bulky data processing application such as cloud computing, media streaming have captured the market, obtaining a higher data rate at lower energy consumption is a key challenge. A huge amount of energy is dissipated during logical chip operation, data processing and its transfer over the networks. Copper-based interconnects cannot afford to handle such increased data rate at lower energy consumption [1]. Optoelectronic integration tends to provide a feasible solution [2]. It has the capability to handle and process the information at a higher data rate without consuming a huge amount of energy. In case of optical short reach interconnects (< 1 m), the majority of energy dissipation is caused due to sources such as LEDs, LASER; optical modulators and detectors. Our main focus in this work is to reduce the energy consumption of the optical modulators below 10 fJ per bit [3]. Silicon photonics has revolutionized the field of optical short reach interconnects specifically optical modulator due to its capability to achieve higher data rate, compact footprint and easy CMOS compatible fabrication techniques. Traditionally, optical modulation is realized either through Mach-Zehnder interferometer (MZI) configuration or resonance based configuration. MZI based modulator [4,5] enables high bandwidth (BW) operation but at the cost of larger footprint, higher energy consumption and insertion loss. Resonance based modulators involving Ring Resonator [6] and Photonic Crystal Cavity [7] can achieve high optical mode confinement, along with low energy consumption but they suffer from narrow bandwidth operation due to the resonance behavior. Silicon–Germanium-based modulator can be used as an alternative as they can operate at low voltage and offer large bandwidth but they suffer from fabrication complexity due to heterogeneous integration [8,9]. Electro-absorption modulator design based on transparent conductive oxide (TCO) material such as indium tin oxide (ITO) [10] were also experimentally demonstrated which achieved very high extinction ratio but suffered from narrow modulation bandwidth. On the other hand, Graphene-based optical modulators offer a viable solution to the above-mentioned problems due to its intriguing electrical and optical properties [11] as discussed in next section. Liu et al. reported the first broadband graphene on silicon-based modulator [12], however due to the poor overlap between the graphene layer and the waveguide mode the modulation depth was around 0.1 dB/ μm for a drive voltage of 4 V. Hu et al. [13] reported a thermally stable graphene on buried silicon waveguide-based modulator. Although they have demonstrated 10Gbps operation, the energy consumption was still relatively high at 350 fJ/bit. Several other designs were also reported [14,15] but these designs achieved larger bandwidth at the cost of high energy consumption. The reason for such poor modulation depth and high energy consumption can be inferred from the weak interaction between the optical modal field and graphene monolayer as can be observed from Fig. 1(a) and (b). The TE mode as shown in Fig. 1(a) tends to be more concentrated in the center of silicon waveguide so graphene interacts with the only evanescent optical field. In case of TM mode also graphene interacts with only a small portion of optical field as indicated in Fig. 1(b). Plasmonic waveguides provides high local field enhancement and smaller volume of optical mode and thus combining graphene with plasmonic waveguides [16,17] results in high extinction ratio. However, these structures suffer from two main limitations: First, presence of metal layers complicates the process of applying gate voltage since dielectric spacer is heavily affected by presence of high electric field and light. Secondly, metal-dielectric interfaces support surface plasmon polaritons that are transverse in nature in the dielectric region but graphene shows weak interaction with perpendicular field component and strong interaction with only in-plane electric field component which is difficult to obtain with plasmonic waveguides. Again, high field confinement in plasmonic based structures causes high absorption of optical mode by metal and thus results in large propagation losses. The limitation of plasmonic based structure mentioned above was removed in [18], where the author proposed design based on wedge surface plasmon polariton which had electric field component along the graphene layer thus circumventing the limitations of weak interaction of traverse component of electric field associated with the surface plasmon polariton with the graphene layer. However, the main bottleneck associated with this design is high operating voltage i.e. around 10 V due to the use of thick dielectric spacer which resulted in large energy consumption.
Fig. 1. Mode profile of in-plane electric field |E2| for 3 cases. Position of graphene located (a) on the top of silicon TM mode waveguide (b) on the top of silicon TE mode waveguide (c) at the interface between top Si3N4 and bottom Si TE mode waveguide. The red dashed line represents the position of the graphene with respect to the waveguide
In this work, we have proposed a fabrication wise simpler approach to improve the light-matter interaction by placing the graphene layer between the silicon nitride ridge and silicon slab as shown in Fig. 1(c). As a result, one can notice, that the maximum concentration of TE modal field lies around the graphene monolayer thereby increasing the light-matter interaction. This approach helped us to minimize our energy consumption far below the limit which is set for on-chip communication i.e. 10 fJ/bit.
This paper is divided into four sections: section 1 discusses briefly about the previously reported designs, their shortcomings and methods to overcome those shortcomings; section 2 mainly focuses on the optical and electrical properties of graphene; section 3 includes 2D schematic of our proposed designs and their parametric optimization; section 4 includes the discussion and concluding remarks.
2. Optical and electrical properties of graphene
Graphene, a 2-Dimensional, anisotropic, sp2 hybridized, a monolayer of carbon atoms arranged in honeycomb-shaped lattice has great potential for augmenting the modulation depth as well as the bandwidth of optical modulator while maintaining lower energy consumption. Graphene has several unrivalled characteristics such as ultra-high carrier mobility, gapless band structure, tunable conductivity and high thermal stability. The optical transmission through graphene-based modulator can be easily controlled by tuning the fermi level (or chemical potential μC) of the graphene layer either through doping of graphene layer or through application of voltage between graphene and waveguide [12]. Both these approaches cause variation in the carrier density of the graphene layer and thus accordingly shifts its fermi level as can be seen from Fig. 2. The Fermi level of the Graphene layer is related to the applied voltage according to the relation:
Fig. 3. Variation of real and imaginary part of permittivity as a function of fermi level with scattering rate of graphene ħΓ=5 meV, dg=0.34 nm, T = 300 K
3. Design schematic and parametric optimization
In this work we have proposed two designs: one using single layer graphene (SLG) and another design using double layer graphene (DLG) in order to achieve a highly energy efficient optical modulators while maintaining a reasonably high operating bandwidth for the on-chip communication network. In our first proposed design, the silicon nitride ridge is placed on top of SLG which in turn is separated from the buried n-doped silicon slab by a thin dielectric layer of aluminum oxide (Al2O3). It is necessary to choose appropriate dielectric spacer as it plays a significant role in reducing the energy per bit. Thin and high refractive index dielectric such as Al2O3 aids in designing an energy efficient electro-absorption modulator. The whole structure is supported on silicon on insulator (SOI) wafer as shown in Fig. 4(a). One of the metal contacts was connected to SLG and another metal contact is connected to silicon slab through a heavy n doping of order of $1 \times 10^{20}\,\mathrm{cm}^{-3}$. The metal contacts were maintained at a distance of 500 nm from the waveguide edge so that the optical modal field does not get affected. For the capping purpose, we have chosen Si3N4 material because of its low absorption, broad transparency, negligible two-photon absorption (TPA) and low temperature PECVD deposition technique [21–23]. When a positive bias voltage is applied to graphene, a large number of holes gets accumulated in the graphene layer and oppositely charged electrons get accumulated in silicon and vice versa. The graphene-oxide-silicon structure acts as a MOS capacitor in presence of applied bias voltage. In order to accurately map the change in refractive index of silicon due to variation of charge carrier concentration [24] as well as in order to obtain the chemical potential (absolute difference between intrinsic Fermi Level and quasi electron Fermi level) of graphene with respect to the applied bias voltage, an electrical simulation of the device structure is performed using commercially available device simulator. The electrical equivalent circuit diagram for the proposed design is shown in Fig. 4(b). The total capacitance of the structure is given by:
${C_{ox}}$ is the capacitance formed by overlap between the graphene layer and silicon slab insulated from each other by thin $A{l_2}{O_3}$ dielectric as shown below: where, LD is the device length and Wov is the overlapping width between silicon slab and graphene layer in case of single layer graphene configuration (design 1) and between two graphene layers in case of double layer graphene configuration (design 2). ${\mbox{C}_{\textrm{Quan}}}$ is the quantum capacitance developed in graphene layer due to its own carrier density [13] and is given by: In our simulation we have neglected capacitance due to air ${\mbox{C}_{\textrm{air}}}$ and substrate ${\mbox{C}_{\textrm{Si}{\mbox{O}_2}}}$. In order to maximize the absorption of the optical modal field by the graphene layer and hence to improve the extinction ratio, we have extended the graphene layer as well as silicon slab away from the Si3N4 waveguide edge by ${\mbox{d}_{\textrm{ext}}}$ equal to 200 nm in opposite directions. However, this method caused a negative impact on the bandwidth as well as energy consumption since capacitance got increased. Thus, there is always a tradeoff between the extinction ratio and operating bandwidth of the device. The 3-dB bandwidth of the device is expressed as: where, $\mbox{R}_{\textrm{S}}$ is the total series resistance of the device that included the graphene sheet resistance $\mbox{R}_{\textrm{GrSheet}}$ (313 Ω/□) [13]; series resistance due to doped silicon slab $\mbox{R}_{\textrm{Si}}$ which includes series resistance due to 50 nm thick n doped silicon region and heavily doped n+ silicon regionFig. 4. (a) 2D Schematic of Proposed design 1 (b) Electrical equivalent representation of proposed design 1
In our work, we have ignored the silicon-metal and graphene-metal contact resistance, as this highly depends on the fabrication process, contact metal used and contacting method used. It was reported in [25,26] that by etching holes in the graphene layer, the graphene-metal contact resistance gets significantly reduced. To our knowledge, the lowest value of graphene-metal contact resistivity was reported to be around ∼2.2 × 10−9 Ω·cm2 [26]. An ultralow contact resistivity of 5.8 × 10−9 Ω·cm2 using metal silicide-n+-Si contact was reported in [27]. This method employed a Ta silicidation of n+ Si contact surface by a Si-capping silicidation technique. The per bit switching energy in case of modulator is expressed as:
where, Vpp is peak to peak operating voltage. Then, we have optimized the Si3N4 waveguide dimension of proposed device structure 1 as shown in Fig. 5 in order to obtain maximum extinction ratio. The modal analysis of the proposed designs was done using commercially available Finite element method simulator. The simulation grid size was chosen as 0.1 nm in both in x and y directions and boundary condition was set as metallic. The refractive index for Silicon dioxide (SiO2), silicon, silicon nitride (Si3N4), aluminum dioxide (Al2O3) was set as 1.44, 3.475, 1.996, 1.74 respectively for 1550 nm operating wavelength. Figure 5(a) shows the variation of extinction ratio (ratio of maximum to minimum optical transmission through modulator as expressed in dB/μm) as a function of varying waveguide width for different oxide thickness. It is inferred from Fig. 5(a) that the extinction ratio for TE mode got increased as the waveguide thickness was increased and afterwards it got saturated for higher values of waveguide width. The waveguide width was chosen as 700 nm because higher waveguide width increases the capacitance of the device and thus increases the switching energy of the device. Similarly, from Fig. 5(b), for maximum extinction ratio, the height of the $\mbox{S}{\mbox{i}_3}{\mbox{N}_4}$ waveguide was optimized to be 170 nm. Next, using the above waveguide dimension, we have tried to optimize the doping concentration of n doped silicon slab and studied its effect on the transmission loss curve as a function of applied voltage as depicted in Fig. 6. It was observed that when doping concentration was increased, the insertion loss (maximum optical power loss when modulator is integrated into the photonic circuit and can be expressed in terms of maximum transmission through modulator as $\mbox{IL}\, = \,10\mbox{lo}{\mbox{g}_{10}}{\mbox{T}_{\textrm{max}}}$) also increased. However, in our case, when the concentration of n doped silicon slab was kept at $4 \times 10^{ - 19}\,{\rm{cm}}^{- 3}$, insertion loss was below 1 dB for around 15 μm device length. In addition, the series resistance introduced by 50 nm silicon slab is inversely proportional to its doping concentration. So as doping concentration was increased, the series resistance got reduced and hence bandwidth got improved. Therefore, we have chosen the concentration of the n doped silicon slab to be $4 \times 10^{-19}\,\textrm{cm}^{-3}$ and its corresponding sheet resistance for 50 nm thick silicon slab was calculated as 366 Ω /□. Furthermore, the sheet resistance for 50 nm thick heavily n doped silicon ($4 \times 10^{-19}{\rm{cm}}^{-3}$) is calculated as 170 Ω/□. Then, we have studied the effect of oxide thickness on the operating bandwidth and the switching energy as shown in Fig. 7. Using electrical simulation of the proposed design 1 we have obtained the total device capacitance for an oxide thickness of 3 nm as 1.28 pF. Using Eqs. (4), (5) and (6), we obtained the values of ${C_{ox}}$ , ${C_{Quan}}$ and Ctotal values as 2.295 pF, 8.071 pF and 1.786 pF. The difference between the capacitance values obtained from electrical simulation and analytical formula is because we did not take into account the capacitance attributed due to the presence of charges in silicon when the modulator is operated in the depletion region in the Eq. (4). From Fig. 7, it was observed that switching energy first got decreased when oxide thickness was increased and then afterwards it got increased for higher values of oxide thickness. In addition, the bandwidth Eq. (7) increased as the oxide thickness was increased. The behavior of switching energy can be justified from the fact that both the device capacitance as well drive voltage affects the switching energy Eq. (9). In addition, oxide thickness is inversely proportional to the device capacitance so as oxide thickness was increased, the capacitance got reduced. However, according to the relation Q = CV for fixed charges, the operating voltage got increased. For initial values of oxide thickness, the operating voltage got slightly increased however for higher values of oxide thickness; its influence was seen quite high as indicated in Table 1. The total series resistance for a device length of 78.59 μm and oxide thickness of 3 nm was calculated to be 11.34 Ω. The maximum operating bandwidth was calculated to be 10.89 GHz and minimum energy consumption was calculated to be 3.22 fJ/ bit as shown in Fig. 7. Table 1 summarizes the performance of proposed design 1 for different oxide thickness assuming peak to peak voltage as 0.1 Volt. Although using design 1, we were able to obtain maximum operating bandwidth greater than 10 GHz which is sufficient for use in on-chip communication. However, presence of parasitic capacitance as well as silicon slab resistance limited the operating bandwidth of our device. In order to further improve the bandwidth, the doped silicon layer needs to be avoided. So, we have proposed a second design which consists of graphene-oxide-graphene layer sandwiched between the silicon nitride ridge and 50 nm buried silicon slab supported on SOI wafer as shown in Fig. 8. From Fig. 9(a), (b), the waveguide dimension (width x height) was optimized to be 800 nm and 120 nm respectively in order to obtain maximum extinction ratio. Figure 10 shows the effect of variation of oxide thickness on the bandwidth and switching energy respectively. For the double layer configuration (design 2), the analytical formula for calculating the total capacitance Ctotal is given by: $where\; {C_{ox}}$ is the capacitance formed by the overlap between the two graphene layers; ${C_{Quan}}$ is the quantum capacitance developed in graphene layer due to its own carrier density. Using Eqs. (5), (6) and (10), we calculated the values Cox, CQuan and Ctotal as 0.963 pF, 3.392 pF and 0.843 pF respectively. For switching energy and bandwidth calculation we have assumed the capacitance values obtained from the electrical simulation. Using electrical simulation of the proposed design 2 we have obtained the total device capacitance Ctotal for an oxide thickness of 3 nm as 0.426 pF for a device length of 45.3 μm. Furthermore, the total series resistance RS including only the sheet resistance of both the graphene layers was calculated as 11 Ω for a device length of 45.3 μm. Using Eq. (9), the minimum value of switching energy for a device length of 45.3 μm was calculated as 4.26 fJ/bit at dc operating voltage of 1.54 V whereas the maximum operating bandwidth for device length of 59.2 μm was found to be 43.8 GHz for 5 nm oxide thickness and at operating voltage of 1.87 V. Table 2 summarizes the performance of design 2 for different oxide thickness assuming peak to peak voltage to be 0.1 Volt.Fig. 5. Variation of Extinction Ratio for TE mode as a function of (a) waveguide width for different oxide thickness (b) waveguide height for different oxide thickness
Fig. 6. Effect of variation of doping concentration of n doped silicon slab on the transmission loss curve
Fig. 7. Effect of variation of oxide thickness on Bandwidth and Switching Energy with Wg=700 nm, Hg=170 nm and doping concentration of n doped silicon slab as 4 × 10−19 cm−3
Fig. 9. Variation of Extinction Ratio for TE mode as a function of (b) waveguide width for different oxide thickness (c) waveguide height for different oxide thickness
Fig. 10. Effect of variation of oxide thickness on Bandwidth and Switching Energy with Wg=800 nm and Hg=120 nm
Table 1. Performance metrics for proposed design 1 for different oxide thickness
Table 2. Performance metrics for proposed design 2 for different oxide thickness
4. Discussion
In order to quantify the electro-optic performance of our proposed two designs we have introduced a figure of merit (FOM). Since, the most important performance metrics in our work is switching energy consumption and bandwidth so we want to choose a configuration which will allow us to operate at minimum switching energy and maximum operating bandwidth. Thus, we have defined the FOM as ratio of operating bandwidth to per bit switching energy Ebit in GHz/fJ/bit as expressed below:
In Fig. 11, we have plotted the FOM for both SLG configuration and DLG configuration. It is observed that the performance of DLG is almost three times better than the SLG configuration due to higher 3 dB bandwidth of DLG configuration.Fig. 11. Figure of Merit for both optimized single layer and double layer configuration for different oxide thickness
In Table 3, we compare the previously reported graphene modulator designs with ours based on some relevant performance metrics such as operating bandwidth, 3 dB length, energy consumption and figure of merit. Our primary goal in this work was to reduce the energy consumption while maintaining a reasonable modulation bandwidth. Although some of the previous designs [16,28] have shown larger modulation bandwidth, they suffer from large energy consumption. In addition, the performance of our designs in terms of figure of merit is far higher compared to previously reported works due to very low energy consumption (<10 fJ/bit) which is ideal for on-chip communication. In summary, the light-matter interaction got significantly improved when we placed a higher refractive index capping layer on top of graphene integrated silicon waveguide. This aided in achieving higher extinction ratio at smaller footprint and DC operating voltage which in-turn helped in achieving lower switching energy. The switching energy in case of SLG configuration was found to be 3.22 fJ/bit whereas in case of DLG configuration it was found to be 4.26 fJ/bit. Although SLG slightly edges over DLG in terms of switching energy but presence of parasitic capacitance and silicon slab resistance limited its bandwidth. These shortcomings were overcome using double layer graphene configuration. The performance of DLG was found to be three times better than SLG in terms of figure of merit due to higher bandwidth obtained using DLG configuration.
Table 3. Comparison on performance metrics of graphene integrated electro-absorption modulator
Funding
Indian Institute of Technology Kharagpur.
References
1. S. Borkar, “Role of interconnects in the future of computing,” J. Lightwave Technol. 31(24), 3927–3933 (2013). [CrossRef]
2. D. A. Miller, “Attojoule optoelectronics for low-energy information processing and communications,” J. Lightwave Technol. 35(3), 346–396 (2017). [CrossRef]
3. D. A. Miller, “Optical interconnects to electronic chips,” Appl. Opt. 49(25), F59–F70 (2010). [CrossRef]
4. A. Liu, R. Jones, L. Liao, D. Samara-Rubio, D. Rubin, O. Cohen, R. Nicolaescu, and M. Paniccia, “A high-speed silicon optical modulator based on a metal–oxide–semiconductor capacitor,” Nature 427(6975), 615–618 (2004). [CrossRef]
5. K. Debnath, D. J. Thomson, W. Zhang, A. Z. Khokhar, C. Littlejohns, J. Byers, L. Mastronardi, M. K. Husain, K. Ibukuro, F. Y. Gardes, and G. T. Reed, “All-silicon carrier accumulation modulator based on a lateral metal-oxide-semiconductor capacitor,” Photon. Res. 6(5), 373–379 (2018). [CrossRef]
6. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Opt. Express 15(2), 430–436 (2007). [CrossRef]
7. K. Debnath, L. O’Faolain, F. Y. Gardes, A. G. Steffan, G. T. Reed, and T. F. Krauss, “Cascaded modulator architecture for WDM applications,” Opt. Express 20(25), 27420–27428 (2012). [CrossRef]
8. P. Chaisakul, D. Marris-Morini, M. S. Rouifed, G. Isella, D. Chrastina, J. Frigerio, X. Le Roux, S. Edmond, J. R. Coudevylle, and L. Vivien, “23 GHz Ge/SiGe multiple quantum well electro-absorption modulator,” Opt. Express 20(3), 3219–3224 (2012). [CrossRef]
9. J. Liu, M. Beals, A. Pomerene, S. Bernardis, R. Sun, J. Cheng, L. C. Kimerling, and J. Michel, “Waveguide-integrated, ultralow-energy GeSi electro-absorption modulators,” Nat. Photonics 2(7), 433–437 (2008). [CrossRef]
10. Q. Gao, E. Li, and A. X. Wang, “Ultra-compact and broadband electro-absorption modulator using an epsilon-near-zero conductive oxide,” Photon. Res. 6(4), 277–281 (2018). [CrossRef]
11. K. F. Mak, L. Ju, F. Wang, and T. F. Heinz, “Optical spectroscopy of graphene: from the far infrared to the ultraviolet,” Solid State Commun. 152(15), 1341–1349 (2012). [CrossRef]
12. M. Liu, X. Yin, E. Ulin-Avila, B. Geng, T. Zentgraf, L. Ju, F. Wang, and X. Zhang, “A graphene-based broadband optical modulator,” Nature 474(7349), 64–67 (2011). [CrossRef]
13. Y. Hu, M. Pantouvaki, J. Van Campenhout, S. Brems, I. Asselberghs, C. Huyghebaert, P. Absil, and D. V. Thourhout, “Broadband 10 Gb/s operation of graphene electro-absorption modulator on silicon,” Laser Photon. Rev. 10(2), 307–316 (2016). [CrossRef]
14. M. Fan, H. Yang, P. Zheng, G. Hu, B. Yun, and Y. Cui, “Multilayer graphene electro-absorption optical modulator based on double-stripe silicon nitride waveguide,” Opt. Express 25(18), 21619–21629 (2017). [CrossRef]
15. S. Qu, C. Ma, S. Wang, H. Liu, and L. Dong, “Modulation speed limits of a graphene-based modulator,” Opt. Quantum Electron. 50(2), 105 (2018). [CrossRef]
16. J. Luan, M. Fan, P. Zheng, H. Yang, G. Hu, B. Yun, and Y. Cui, “Design and Optimization of a Graphene Modulator Based on Hybrid Plasmonic Waveguide with Double Low-Index Slots,” Plasmonics1–6 (2018).
17. D. Svintsov, V. Vyurkov, V. Ryzhii, and T. Otsuji, “Voltage-controlled surface plasmon-polaritons in double graphene layer structures,” J. Appl. Phys. 113(5), 053701 (2013). [CrossRef]
18. D. Ansell, I. P. Radko, Z. Han, F. J. Rodriguez, S. I. Bozhevolnyi, and A. N. Grigorenko, “Hybrid graphene plasmonic waveguide modulators,” Nat. Commun. 6(1), 8846 (2015). [CrossRef]
19. L. Yang, T. Hu, R. Hao, C. Qiu, C. Xu, H. Yu, Y. Xu, X. Jiang, Y. Li, and J. Yang, “Low-chirp high-extinction-ratio modulator based on graphene–silicon waveguide,” Opt. Lett. 38(14), 2512–2515 (2013). [CrossRef]
20. F. Xu, S. Das, Y. Gong, Q. Liu, H.-C. Chien, H.-Y. Chiu, J. Wu, and R. Hui, “Complex refractive index tunability of graphene at 1550 nm wavelength,” Appl. Phys. Lett. 106(3), 031109 (2015). [CrossRef]
21. G. Suchaneck, V. Norkus, and G. Gerlach, “Low-temperature PECVD-deposited silicon nitride thin films for sensor applications,” Surf. Coat. Technol. 142–144, 808–812 (2001). [CrossRef]
22. Z. Shao, Y. Chen, H. Chen, Y. Zhang, F. Zhang, J. Jian, Z. Fan, L. Liu, C. Yang, L. Zhou, and S. Yu, “Ultra-low temperature silicon nitride photonic integration platform,” Opt. Express 24(3), 1865–1872 (2016). [CrossRef]
23. L. A. Shiramin and D. V. Thourhout, “Graphene modulators and switches integrated on silicon and silicon nitride waveguide,” IEEE J. Sel. Top. Quantum Electron. 23(1), 94–100 (2017). [CrossRef]
24. R. Soref and B. Bennett, “Electrooptical effects in silicon,” IEEE J. Quantum Electron. 23(1), 123–129 (1987). [CrossRef]
25. L. Anzi, A. Mansouri, P. Pedrinazzi, E. Guerriero, M. Fiocco, A. Pesquera, A. Centeno, A. Zurutuza, A. Behnam, E.A. Carrion, and E. Pop, “Ultra-low contact resistance in graphene devices at the Dirac point,” 2D Mater. 5(2), 025014 (2018). [CrossRef]
26. S. M. Song, T. Y. Kim, O. J. Sul, W. C. Shin, and B. J. Cho, “Improvement of graphene–metal contact resistance by introducing edge contacts at graphene under metal,” Appl. Phys. Lett. 104(18), 183506 (2014). [CrossRef]
27. K. Yamada, K. Tomita, and T. Ohmi, “Formation of metal silicide-silicon contact with ultralow contact resistance by silicon-capping silicidation technique,” Appl. Phys. Lett. 64(25), 3449–3451 (1994). [CrossRef]
28. H. Dalir, Y. Xia, Y. Wang, and X. Zhang, “Athermal broadband graphene optical modulator with 35 GHz speed,” ACS Photonics 3(9), 1564–1568 (2016). [CrossRef]
