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Abstract
Most traditional PICs (photonics integrated circuits) are based on a single-waveguide-layer configuration, which takes advantage of the mature fabrication process from the EIC (electronic integrated circuits) industry; but in the meantime, this configuration also limits the performance of PICs in applications such as OPA (optical phased array) devices. We have proposed a multi-waveguide-layer 3-D (3 dimensional) OPA device and demonstrated its unique advantage in broadband high efficiency. In this paper, we present the fabrication process of the proposed 3-D OPA in detail. By developing the fabrication process with a single lithography step, we address the two potential issues in a multi-waveguide-layer PIC: the alignment between layers; and the accurate spacing control between layers. The detailed considerations of processes are also elaborated, especially in the PR (photoresist) exposure and etching.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
Thanks to the unique advantages of photons over electrons, photonic integrated circuits (PICs) have been proposed and studied for decades as the next-generation chip. They have been proven to have various applications in multiple material platforms [1–3]. Most PICs so far inherit the mature CMOS (complementary metal oxide semiconductor) fabrication process from the electronic IC (integrated circuit) industry. In the standard procedure, the basic components (transistors in EICs – electronic integrated circuits, waveguides in PICs) are firstly fabricated on the top surface of a wafer, and then the metal contacts are fabricated above the top surface; thus, the basic components are typically in a single layer. These single-layer fabrication techniques are very mature, but it also limits the performance of the IC in the meantime. In recent years, the EIC industry has developed a trend of converting the memory and computing unit designs from 2-D to 3-D [4,5]. In principle, this idea and the fabrication techniques can also be applied to the 3-D multi-waveguide-layer PICs [6–8].
Optical phased array (OPA) is a relatively new type of PIC; it is proposed as a potential solution in the Lidar application for autonomous driving technology. It has drawn considerable research efforts due to its promising capability of solid-state beam steering since 2009 [9]. As a result, tremendous progress has been made [10]. As one type of PICs, most published OPA devices are based on the single-waveguide-layer configuration [10], which limits the total optical efficiency on both the fiber-to-chip and the chip-to-beam coupling. Works have been done to address this issue. In [11], a direct writing method based on ultrafast laser inscription (ULI) is applied to convert the single-layer waveguides to 3-D waveguides in an OPA device. It forms an edge-coupled 2-D emitting array on the side of the device and thus achieves a high chip-to-beam coupling efficiency. In [12], the idea of a true 3-D OPA with multiple waveguide layers all over the device has been proposed, and the potential fabrication process is discussed.
We have taken one step further by proposing and experimentally demonstrating a true 3-D OPA device [13,14]; a sample with 4X16 OPA on the edge has been fabricated and tested. By applying the multi-waveguide layer configuration, we can utilize the edge coupler for both the fiber-to-chip and the chip-to-beam coupling, which offers the capability of emitting a 2-D converged beam with a broadband high optical efficiency. During this work, we have developed a self-aligned process to address some of the fabrication challenges and significantly reduce the number of process steps. In this paper, we present the development of this process in detail.
2. Fabrication challenges in the multi-waveguide-layer configuration
Figure 1 illustrates the standard method of fabricating a multi-waveguide-layer device. Figure 1(a) shows that, in this process, a whole layering-patterning-cladding-polishing cycle is needed for every layer of the waveguides. It is consistent with the back-end process in the electronic IC industry, which fabricates the interconnection metal layers. In the EICs, it is not necessary to have perfect control over the layer spacing and the alignment between layers; however, in the PICs, especially in the OPA devices, these two issues can mess up the phase profile at the emitting surface and results in a distorted farfield pattern. Figure 1(b) illustrates an example of the potential fabrication errors, the inadequate control of layer spacing, and the misalignment between layers. In the OPA application, a good emitting farfield pattern relies on the proper arrangement of the array. In a Si 3-D OPA, the waveguide core size is typically around 300 to 500 nm; in such a case, a 10% fabrication error will be about 30 to 50 nm, which may not be acceptable. In a Si3N4 3-D OPA, the fabrication tolerance is slightly relieved but still in the range of around 100 nm (∼10% feature size). In the current CMOS compatible fabrication process, such a low fabrication tolerance is challenging in either the layer spacing control (relying on the thickness control during a chemical mechanical polishing CMP process) or the alignment between layers (relying on the calibration between multiple exposures) [15,16].
Fig. 1. Normal method of fabricating a multi-layer structure. (a) Process flow. i, waveguide layer deposition; ii, patterning; iii, cladding layer deposition; iv, chemical mechanical polishing (CMP). (b) Two potential fabrication errors that can significantly affect the device performance are (1) the bad control of layer spacing, and (2) the misalignment between layers.
A possible method to address these two issues is using a single-lithography process over multiple waveguide layers. Figure 2 illustrates this process; instead of patterning one waveguide layer at a time, this process directly patterns all the waveguide layers together. Apparently, this process requires every waveguide layer to contain the same pattern (or at least a portion of the whole pattern to be the same); fortunately, this is possible in an OPA device [13,14]. In this process, the layer spacing is controlled by CVD (chemical vaper deposition) deposition, which has excellent control over the thickness (the accuracy can be smaller than 10 nm). Hence, the waveguide layers are self-aligned due to the single-lithography process.
Fig. 2. Fabrication process flow with single lithography step. i, layer depositions; ii, mask layer pattering; iii, dry etching over multiple waveguide layers; iv, mask layer removal; v, cladding layer deposition. The layer spacing can be well controlled by CVD deposition, and the waveguide layers are self-aligned.
In summary, a single-lithography process will be a better option for a 3-D PIC which has two characteristics: firstly, it allows every layer to have the whole or a part of the pattern to be the same; and secondly, it is very sensitive to the arrangement of the waveguides between layers. In addition, logically, for the applications which have the first characteristic, most of them should tend to have the second one. On the other hand, for those applications which have the second characteristic, it should be minor, but a still considerable portion of them also have the first one; that is to say, these two characteristics should have a particular interdepend symbiotic property.
3. Fabrication of a 3-D OPA device
Figure 3 illustrates the design of the 3-D OPA device. Figure 3(a) is the illustration of the device. We have detailly analyzed the performance of this device in our previous work [13,14]. In summary, thanks to the multi-waveguide-layer configuration, this device can utilize the edge coupling to achieve both the fiber-to-chip and the chip-to-beam coupling, guaranteeing a broadband high optical efficiency. The multi-waveguide-layer design offers two advantages to the device: firstly, at the input coupling end, it enhances the mode-match between the fiber and the on-chip coupler; secondly, at the emitting coupling end, it enhances the vertical convergence to the emitting beam. The beam steering capability is enabled by the Ω-shape design, which purposely generates an extra dispersive effect for the device, so the beam can be steered horizontally by tuning the wavelength of the input light. Utilizing the Ω-shape design allows the device to be simply used by one degree-of-freedom operation. It also frees the device from having individual phase shifters on every waveguide, which is extremely difficult to fabricate in the multi-waveguide-layer configuration.
Fig. 3. Design of the multi-layer Si3N4 3D OPA. (a) Schematic (3D view) of the structure. An SMF is used to couple light into the device, and the waveguide width at the coupling region is enlarged to ensure the best mode matching (see zoom-in figure a1); a 2D 8X16 OPA is formed at the edge of the device (see zoom-in figure a2). (b) Simulation result of the designed structure with no fabrication imperfection, a clear farfield is generated, aliading effect can be observed. (c) Simulation result of the designed structure with fabrication error, a messed farfield is generated because of the phase error.
Figure 3(b) and (c) give an example of the effect of the fabrication error presented in Fig. 1; they show the simulated farfield emitting pattern of the device with and without fabrication error. In the simulation, all the other parameters are set to be the same. The misalignment and thickness error are set to 0 in Fig. 3(b); while in Fig. 3(c), the misalignment is set to 100 nm for the 2nd layer, -100 nm for the 3rd layer, and 50 nm for the 4th layer, and the thickness error are set to 100 nm for the 2nd layer, 50 nm for the 3rd layer, and -100 nm for the 4th layer. In Fig. 3(b), the farfield is clear, and several grating lobes can be observed due to the aliasing effect, (which happens when the emitting pitch is larger than half of the emitting wavelength). As a comparison, the farfield in Fig. 3(c) is messed up, and there are a lot of noise-level emitting lobes appearing in the field; this is because the fabrication error messed up the phase profile at the emitting surface.
Our sample is fabricated at the Lurie Nanofabrication Facility (LNF) in Ann Arbor, Michigan, USA. The one-lithography process is developed based on the fabrication capability of LNF. In the following, the development of the process is presented in detail.
3.1 Photoresist recipe
In the one-lithography process, a strict vertical etching is required to maintain the same pattern over all the layers, so wet etching is not applicable. However, when using an RIE (reactive ion etching) dry etching, any mask layer will also be depleted during the etching. Therefore, the number of waveguide layers that can be etched in one lithography depends on the thickness of the mask layer, which essentially depends on the thickness of the photoresist. The thickness of the PR layer is limited by the feature size of the device or the waveguide width, in our case. Here, width is related to the single-mode condition. As a result of its lower refractive index, Si3N4 is selected as the waveguide material in this device due to its better performance in passive devices than Si [17]. SiO2 is chosen as the cladding material. According to the simulation results, 1100 nm is the maximum width that allows the Si3N4 waveguide to maintain the single mode. So, the first thing we do is to determine the thickest PR that can constantly offer 1100 nm resolution.
The photoresist we used is a standard positive photoresist SPR220 [18]. ACS 200 cluster tool is used for the coating, baking, and developing of the PR, and GCA AutoStepper is used for exposure. The spin rate in the coating step is tuned to achieve different PR thicknesses, and the exposure matrix method is utilized to determine the best exposure time and offset. In this method, multiple dies are exposed on the same wafer with a step-increased exposure time or offset; then, by comparing the color of every die after PR developing, the best exposure time and offset can be found. According to the experiment result, we have found that the thickest PR offering 1100 nm resolution is approximately 4um. Figure 4 shows examples of the developing results. Figure 4(a) is the end of the input taper and the 1st Y-splitter of the device at 4um PR. The picture is focused when a clear boundary of the larger triangles is observed. At this focus, the narrow waveguides are also in focus, indicating that the small and large features are at the same thickness after PR development. Figure 4(b) shows the same part at the 5um PR setting. The larger triangular parts can be developed well, but the narrow waveguide lines are not in focus; this means that when the large features are sufficiently developed, the small features are already over-developed. We conclude this is an indication of a too-thick PR. Therefore, we have determined that the thickest PR configuration for the 1.1um feature size is approximately 4um.
Fig. 4. Illustration of the limited PR thickness. (a) Y-splitter on 4um PR. (b) Y-splitter on 5um PR. The pictures are taken at the best focus of the large feature, the small feature in (a) is also at focus, but the small feature in (b) is out of focus. The feature size is limited by the single-mode waveguide width of 1100 nm. A too-thick PR layer will have many developing defects.
3.2 RIE etching profile
The etching is the most critical step in the one-lithography process. In this work, we have tested 3 different etching methods, which are: A. using only PR as the mask, with etchant composition to achieve the best directionality; B. Using only PR as the mask, with etchant composition to achieve the best selectivity; C. Using a-Si as the hard mask, this method requires a two-step etching, the a-Si is firstly etched by PR, then the Si3N4/SiO2 stack is etched by a-Si. In the experiment, the tool we used is the STS Glass Etcher at LNF, the gas mixture consists of a large amount of helium of 174 sccm and a small portion of etchant gas of a maximum of 40 sccm. A mixture of CF4, C4F8, and H2 is used as the etchant to achieve different selectivity and directionality; HBr is used to etch the a-Si (in a different tool). Table 1 summarizes the etching rate in the 3 different etching methods, and the data are tested on blank wafers.
Table 1. Summary of the etching rate in the 3 cases. Case 1, to have the best directionality when using PR as the mask. Case 2, to have the best selectivity when using PR as the mask. Case 3, using a-Si as the hard mask
In the fluorocarbon-based etch processes, the reaction depends on: 1) a combination of surface passivation of the fluorocarbon; 2) ion bombardment that breaks the bonds in the etched material so they can combine with the fluorocarbon, creating a volatile byproduct. The etching process is highly dependent on the respective rates of these two factors. In short, the higher the carbon content in the gas mixture used, the faster the passivation rate. This will slow the etching process since more energy is required to break through the passivation layer. This effect is stronger on the photoresist than on SiO2 and Si3N4; thus, it leads to a higher selectivity. On the other hand, this effect also leads to a more tapered etching profile. Since ion bombardment tends to be weaker at the edge of features, some of the ions will be shadowed by the passivation layer, and their trajectories will not be perfectly perpendicular to the wafer surface. Moreover, adding H2 could reduce free fluorine content in plasma, creating a similar effect to higher carbon content.
From the data in Table 1, with the knowledge of the maximum thickness of PR to be 4um, we can easily calculate the number of waveguide layers that can be etched in one lithography. Method A has the highest fluorine content, which leads to the best directionality; yet, on the other hand, the selectivity is lower, so the maximum number of layers that can be etched in one lithography is 4 layers. Method B has the highest carbon content (H2 further reduces the fluorine content), so it has the best selectivity; it is possible to etch 14 layers of waveguides at one time. Method C uses a hard mask, which results in an even larger overall selectivity, so etching 50 layers are possible in one lithography.
These estimations are calculated based on the etching rate from the blank wafer. In the practical case, we also need to check the etching profile since we expect the same pattern at every layer. We tested the etching profile from methods A, B, and C with all the other parameters (pressure, RF power, and temperature) set to be identical. Figure 5 shows the results of the etching profile check. 5a and 5b are the profile for Method A and B, respectively; the test is done on the substrate with 3-SiN-layer Si3N4/SiO2 stacks. It can be seen that the etching profile in Fig. 5(a) from Method A is very vertical. This is due to the chamber configuration and gas mixture of the STS Glass Etcher. Because of the relatively small portion of the etchant in the gas mixture, the etching process is highly ‘diluted’, inhibiting excessive passivation. The tool also runs under very low pressure, which helps with the etching profile.
Fig. 5. Etching profile of the 3 cases. (a) Best directionality; (b) Best selectivity, a clear taper can be found on the gratings; (c) Using a-Si hard mask, faceting effect happens in the 2nd etching step, resulting in degraded gratings.
Figure 5(b) shows the etching profile of Method B (best selectivity with PR); it is evident that the gratings are tapered. This phenomenon is caused by the relatively fast growth of the passivation layer, as explained above. Although the taper is already obvious in the 3-SiN-layer substrate, it can be estimated that the tapering effect will be significantly stronger in a 14-SiN-layer substrate, and the top layers will not be able to maintain the dimensions, which is not acceptable in the 3-D OPA devices.
Figure 5(c) is the tested etching results of Method C; the test is done on a substrate with 3um SiO2, 2um a-Si, and 0.97um PR. 5c left is the etching profile after the 1st step of a-Si etching; it can be seen that the etching of a-Si is relatively vertical, and the etching stopped on the surface of SiO2 perfectly. This is due to the significant selectivity difference between Si and SiO2, and about 270 nm PR is consumed. 5c middle is taken 8 mins after the 2nd etching; at this time, the etching on the SiO2 is vertical, but the a-Si hard mask has already started to degrade because of the faceting effect. This effect usually happens in the etching, which is dominated by physical sputtering but not a chemical reaction; in such a process, there is a strong sputter yield dependence on the incidence angle of the incoming ions. In the 2nd step of Method C, a-Si's etching rate is low, indicating that this etching is dominated by physical sputtering. At the corner of a feature, which is typically slightly (maybe not even visibly) rounded, a specific angle will be developed where the sputter yield is highest, resulting in a degradation of the features. This degradation hadn’t merged into SiO2 layers in 5c middle, so the SiO2 features are still vertical; but in 5c right, the profile is taken after 16 mins of the 2nd etching, and the degradation had merged into SiO2. In the OPA sample, Method C eventually results in only a few layers of Si3N4 waveguide being maintained after a long etching, so this method is also not acceptable in a 3-D OPA device.
In summary, we found that only Method A is acceptable for the 3-D OPA device.
3.3 RIE etching rate at small openings
The etching rate in Table 1 is tested on blank wafers. However, in the small openings, the etching rate is usually slower because etchant ions are hard to enter. When using Method A, we have calculated that 4 layers of Si3N4 waveguides are possible to be etched in one lithography. To achieve a full etching on the 4 layers, we need to avoid the small openings. Figure 6 shows the etching profile at small openings, the pictures are taken from a testing wafer containing isolated gratings with different openings, and the grating width is 500 nm. A relatively shallow etching is proceeded in the testing to observe the etching differences in small openings. From Fig. 6, the etching depth at large openings is approximately 1.2um over the whole wafer, while the etching depth is obviously shallower at small openings; it is etched approximately 290 nm at 1um openings, 1030 nm at 2.5um openings, and 1040 nm at 4um openings. Eventually, when the opening size reaches 5.5um, the etching depth at the center of the openings becomes roughly as same as the depth at large openings.
Fig. 6. Illustration of slower etching in small openings. The etching depth at the large openings is approximately 1.2um, while at small openings are: (a) 290 nm at 1um openings; (b) 1030 nm at 2.5um openings; (c) 1040 nm at 4um openings; (d) 1200 nm at 5.5um openings.
4. Fabrication result
In summary, we used 4um PR as the mask layer, Method A for etching, and 6.9 um as the smallest openings in the device. During the etching, time control is utilized to ensure it is sufficient to etch through the four Si3N4 layers. Figure 7(a) shows the image of the emitting end of a completed 4-layer sample; the dedicated backscattering SEM (scattering electronic microscope) imaging takes the picture. The image is taken from an angle so that the end surface is presented, and the tooth-like shape at every pitch is the result of the PECVD (plasmonic enhanced chemical vapor deposition) cladding on a high aspect-ratio grating. Figure 7(b) is a zoom-in picture showing three horizontal pitches; the four brighter boxes are the emitting surface of the Si3N4 waveguides at different layers. A slight inverse taper (the top of the grating is wider than the bottom of the grating) can be observed in the figure; the reason for this should be that during the RIE process, the charge will accumulate on the etching surface, which enhances the horizontal etching right close to the etching surface. Therefore, as the etching becomes deeper, the grating shows a slight inverse taper. In addition, the image is taken from an angle, which also visually enhances the extent of the inverse taper.
Fig. 7. SEM picture for a 4-layer sample. (a): zoom-out view of the device from an angle. The Y-splitter tree and the delay line region can be distinguished from the picture. (b): zoom-in view of three pitches, four Si3N4 end-fire emitters in every pitch can be distinguished.
The optical performance of the fabricated device is tested using a commercial tunable laser and the Fourier optics measurement. The results show that the 3-D OPA device can emit a beam with vertical convergence of 17.42° [14], which indicates that the spacing and calibration between layers are fabricated as designed.
5. Conclusion
In this work, we demonstrated a single lithography fabrication process to address the layer spacing and calibration issues in the normal multi-layer process. In this process, the layer spacing is controlled by CVD deposition, so the accuracy of the spacing thickness can be much better than the control in a CMP process; layer calibration is achieved by self-alignment. In addition, an etching method with a very vertical etching profile is selected. Therefore, it ensures that the pattern at every waveguide layer is sufficiently similar. It is also worth mentioning that our process is developed at the LNF; if one wants to develop such a process somewhere else, the detailed process parameters and the etching possibility may differ. However, the basic idea of this process is valid in any place, that is, controlling the layer spacing by CVD deposition (which is more accurate than the control in a CMP process) and calibrating multiple layers by self-alignment. This method is more suitable than the normal method for a multi-waveguide-layer PIC if it: 1) requires the same pattern on every waveguide layer; and 2) is sensitive to the fabrication errors in layer spacing and calibration.
Disclosures
The authors claim no potential conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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