Silicon photonics (SiP) is increasingly being used commercially due to its high integration density and compatibility with the well-established microelectronic CMOS process [1,2]. SiP has been extensively utilized for datacom and telecom applications [3–5]. The data rate requirements for these systems continue to increase, as data intensive services rise in popularity. Wavelength division multiplexing (WDM) schemes increase the bit rate in a cost-effective manner. WDM schemes increment the aggregate data rate of optical links without incurring in a higher baud rate, thus maintaining the energy cost per bit and the bandwidth requirement for electronic components such as modulators, demodulators, and trans-impedance amplifiers. The wavelength demultiplexer is the fundamental device for WDM systems. The demultiplexer is used to spatially separate the signals carried by different wavelengths in a common physical waveguide. Several demultiplexing architectures have been proposed for the silicon photonics platforms, including arrayed waveguide gratings (AWGs), echelle gratings (EGs), ring resonator (RRs), contra-directional couplers (CDCs), and Bragg gratings [6–12]. The RR, CDC, and Bragg grating architectures make use of serial cascading of various filtering stages, one for each channel. This characteristic makes them unsuitable for high-channel-count systems and burdensome to tune, as each channel must be individually adjusted. AWGs and EGs are preferred for their high channel counts and offer the possibility of simultaneous channel position adjustment with just one control signal. High-performance AWGs and EGs are difficult to realize in the silicon-on-insulator (SOI) platform, as its high index-contrast increases the influence of the fabrication imperfections on the optical phase, with a corresponding penalty in XT, loss, and channel misalignment.

A fabrication procedure with multiple etch steps is required for AWGs with sub-decibel loss [13]. Low-loss EGs demand a high reflectivity grating requiring Bragg reflectors with stringent etching control [12] or an additional non-standard mirror metallization [5], which is challenging to fabricate. An alternative wavelength demultiplexer architecture for the SOI platform that exhibits minimal loss, low crosstalk (XT), and simple fabricability is therefore highly desirable.

In [14], an off-chip surface grating coupler was proposed for implementing a band diplexer. For high-channel count, an on-chip solution is preferred in most applications. To maintain most of the diffracted light within the chip plane, a distributed deflector grating can be used [15]. A deflector comprises a channel waveguide periodically perturbed to produce a diffraction order which is intercepted by a nearby slab waveguide. A planar spectrum analyzer based on this concept was demonstrated in [16]. This device relied on chirping the grating pitch to focus the diffracted beam. Later, the curved waveguide grating (CWG) geometry was proposed to implement a demultiplexer that circumvented the need of pitch chirping to achieve the focusing, with an expanded operation bandwidth [17]. A CWG consists of a deflector grating placed along a focusing curve following the Rowland circle. The CWG demultiplexer architecture can potentially offer lower crosstalk than AWG and EG. AWG crosstalk is mainly caused by the sidewall roughness of the arrayed waveguides used as phase accumulators. In CWGs, the phase accumulation happens in a slab waveguide; thus, mainly the comparatively small silicon height variations contribute to the crosstalk. Compared with EGs, in CWGs, the light travels through the slab region only once; thus, the effect of imperfections in this region is reduced by a factor of 2. Moreover, a high-performance CWG can be fabricated using a simple single-etch fabrication process without a mirror metallization.

Up to this point, the only experimental demonstration of a CWG demultiplexer in an SOI was reported by Bock et al. in 2012 [18]. In this Letter, a subwavelength grating (SWG) lateral cladding was used to improve the device efficiency. However, the reported CWGs still suffered from significant losses (${\sim}{{4}}\;{\rm{dB}}$) [18]. We have recently demonstrated by simulations that off-chip radiation is the primary cause of loss in CWGs [19]. Furthermore, we proposed a technique to suppress the off-chip radiation in grating deflectors [20] by designing a device operating in the single radiation beam regime enabled by SWG metamaterial engineering [21,22].

In this Letter, we leverage the fundamental principle of single beam radiation to implement for the first time, to the best of our knowledge, a CWG demultiplexer with state-of-the-art performance when compared with demultiplexers implemented in a 220 nm SOI platform. We design an eight-channel demultiplexer with a 10 nm (1249 GHz) channel separation and a central wavelength ${\lambda _0}$ of 1550 nm featuring a compact footprint of ${{200}}\;{{\unicode{x00B5}{\rm m}}} \times {{150}}\;{{\mu}}$m. The measured device performance is excellent with insertion loss (IL) of ${\sim}{{1}}\;{\rm{dB}}$ and crosstalk as low as ${-}{{25}}\;{\rm{dB}}$.

The experimental demultiplexer geometry is shown in Fig. 1 (for a simplified schematic, see Fig. S1 of Supplement 1). Our geometry is similar to that used in [18], except for the position of the output waveguides. In [18], the output waveguides were placed perpendicular to the grating direction ($\theta \approx {0^\circ}$), whereas here we place them at $\theta \approx - {35^\circ}$ to impose the single beam condition [20], hence suppressing the off-chip radiation loss. The demultiplexer composes a CWG, a free propagation (FPR) slab region, an SWG transition region between the waveguide grating and the FPR, and the output waveguides joining the FPR at the Rowland circle [17]. The light entering the demultiplexer from the input waveguide is coupled via an adiabatic taper to the CWG. As the light propagates along the waveguide, it is diffracted towards the FPR slab through the SWG region. A near-Gaussian field profile is generated along the grating curve (z) and focused within the FPR slab, onto the output waveguide apertures located on the Rowland circle (focal curve $\xi$). The aperture initial width ${W_g}$ is adiabatically reduced to 500 nm with a 20 µm long taper to suppress higher-order modes and maintain the fundamental mode. The dispersive nature of the grating results in the shift of the focal point along the circle as the wavelength changes. The location of the focal point is determined by the grating curvature and the diffraction angle, which is readily obtained from the grating equation [23]:

 

Fig. 1. SEM image of the fabricated CWG demultiplexer. The blue and red light paths schematically show the focusing behavior of the device for two different wavelengths. The main geometric parameters are indicated on the image. The right inset shows details of the sidewall grating waveguide, the SWG slab, and the FPR slab. The left inset shows details of the output waveguides.

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We target a low-loss eight-channel demultiplexer with center wavelength ${\lambda _0} = 1550\;{\rm{nm}}$, channel separation ${{\Delta}}\lambda = 10\;{\rm{nm}}$ (1249 GHz), and in-plane polarization (TE), designed for an SOI platform with a 220 nm thick silicon, a 2 µm buried oxide (BOX), and a 2 µm ${\rm{Si}}{{\rm{O}}_2}$ upper cladding.

The key idea to attain sub-decibel losses is to design the CWG deflector to work in the single beam diffraction window, which requires the grating to radiate far from the normal direction [20]. To operate in this window, we choose the grating pitch ($\Lambda$) and the effective refractive indices of waveguide grating (${n_{{\rm{FB}}}}$), SWG slab (${n_{{\rm{SWG}}}}$), and ${\rm SiO}_2$ cladding (${n_{{\rm{Si}}{{\rm{O}}_2}}}$) [20] such that, for the operating wavelength:

To fulfill this condition, we position the waveguide for the central output channel (${\lambda _0} = 1550\;{\rm{nm}}$) at an angle ${}\theta ({{\lambda _0}}) = - 35^\circ$, with a corresponding pitch of ${{\Lambda}} = 385{\rm{\;nm}}$ according to Eq. (1).

As a next step in the demultiplexer design, we calculate the width (${W_g}$) and center-to-center spacing (${W_s}$) of the output waveguides. The near field along the grating curve is related to the field distribution at the focal curve through the Fourier transform [24]. Therefore, the width of the output waveguides determines the angular aperture of the optical system and the overall length of the grating waveguide. Assuming a Gaussian beam approximation, a receiving waveguide width ${W_g} = 2.1\;{{\unicode{x00B5}{\rm m}\;}}$ has been selected, yielding a mode field radius ${{\rm{MFR}}_{{\xi}}} = 0.75\;{{\unicode{x00B5}{\rm m}}}$. This corresponds to a full width beam divergence in the FPR slab of $2{{\varphi}} = 26.5^\circ$ containing 95% of the beam power at the focal curve [25]. The output waveguide center-to- center spacing has been set to ${}{W_s} = 1.33{W_g}$ to limit the receiver XT to ${-}60\;{\rm{dB}}$ under the Gaussian approximation which yields a theoretical 3 dB bandwidth of 4.5 nm.

Finally, the grating radius R is calculated for the required channel separation ${{\Delta \lambda}}$. From geometrical considerations, it can be shown that

The grating dispersion D was calculated by Floquet–Bloch mode analysis of the grating waveguide, yielding $D = 0.09^\circ /{\rm{nm}}$. This requires a grating radius ${\rm{R = 177\;\unicode{x00B5}{\rm m}}}$, which in turn sets a mode field radius ${{\rm{MFR}}_{\rm{z}}} = 41\;{{\unicode{x00B5}{\rm m}}}$ at the grating curve.

The choice of a diffraction angle $\theta = - 35^\circ$, while reducing the losses, introduces off-axis aberrations on the image at the focal curve that need to be corrected. Figure 2(a) shows (solid line) the image at the focal curve from linear phase Gaussian illumination, obtained by the 2D Rayleigh–Sommerfeld diffraction integral [26]. The image spot is sub-optimal, as it includes multiple lobes that would result in mode-mismatch loss and significant crosstalk.

 

Fig. 2. Field amplitude at (a) the focal curve and (b) the corresponding field amplitude and phase derivative on the grating curve for the linear phase-front diffracted field at the grating (solid) and the corrected phase front at the grating (dashed).

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Thus, the last step in our design is to optimize the phase and amplitude of the field profile synthesized by the grating to obtain a stigmatic image at the focal curve. To resolve this, we used the reciprocity principle [27]: an ideal Gaussian mode profile is assumed at the output waveguide and back-propagated to find the field amplitude and phase at the grating curve. By conjugating this complex field (i.e., applying time-reversal [27]), we find the required field amplitude and phase profiles for the grating to synthesize [Fig. 2(b), dashed lines]. The phase profile has a near-cubic dependence while the amplitude remains virtually unchanged from the linear phase design. This corrected profile produces a stigmatic spot at the focal plane with virtually no sidelobes, as shown by the dashed curve in Fig. 2(a).

The grating geometry can be efficiently designed by means of Floquet–Bloch mode analysis, as we outlined in Ref. [20]. The amplitude profile can be synthesized by apodizing the grating strength [20], while the required phase profile $\phi (z)$ can be obtained by chirping the grating pitch:

The grating geometry apodization and chirping are further described in Section 2 of Supplement 1.

To efficiently evaluate the full device performance, we first simulate the straightened grating deflector by using 3D FDTD. From this simulation, we extract the field in the FPR slab, which we then locate on the grating arc and propagate by using the scalar 2D Rayleigh–Sommerfeld integral to calculate the field distribution on the Rowland circle (focal curve $\xi$). Finally, we find the transmission by means of the overlap integral of the field produced at each output waveguide position and the waveguide mode profile. Figure 3 shows the obtained demultiplexer transfer function for each of the eight output waveguides. The simulation predicts insertion loss as low as 0.5 dB for channel number 4, rolling off to 2 dB (2.7 dB) for the channel 1 (channel 8). The efficiency drops for longer wavelengths due to a higher residual power remaining at the end of the grating waveguide, as shown by the dashed curve in Fig. 3(a). This is a consequence of the grating strength decreasing for longer wavelengths. On the other hand, the efficiency decline at shorter wavelengths is caused by the onset of off-chip radiation [dotted black curve in Fig. 3(a)]. Off-chip radiation not only reduces the power coupled to the FPR slab [solid black curve in Fig. 3; see Fig. 3(b) for a zoom-in], but also degrades the field shape quality reducing the field overlap integral.

 

Fig. 3. (a) Simulated transmission from the input to the output waveguides (device IL) as a function of the wavelength. We also show the power fraction coupled to the slab region (solid black curve), the power fraction remaining at the end of the grating waveguide (dashed black curves), and the power fraction radiated off-chip (dotted black curve). (b) Zoom-in of (a) showing the variation of channel peak transmission and the power coupled to the FPR slab.

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The devices were fabricated in an SOI platform with a 220 nm thick silicon layer over a 2 µm BOX. The samples were patterned using electron-beam lithography and then etched via anisotropic inductively coupled plasma reactive ion etching. Finally, a 2 µm ${\rm{Si}}{{\rm{O}}_2}$ layer was deposited as the upper cladding. Figure 1 shows a scanning electron microscope image (taken before the cladding deposition) of one of the fabricated demultiplexers and details of the sidewall grating and SWG region.

To characterize the fabricated demultiplexer, we used a tunable semiconductor laser as a light source. The linearly polarized light is passed through a polarization controller, which ensures that TE polarization is injected in the chip. A lensed fiber is used to couple the light into the chip using an SWG metamaterial edge coupler [28]. On the chip, the light is split evenly by a $1 \times 2$ multi-mode interferometer (MMI) power divider. One MMI output is routed directly to the chip edge as a reference signal, while the other is used to feed the demultiplexer. Finally, the demultiplexer outputs are routed to the chip edge and connected to SWG edge couplers. The light exiting the chip is collimated by a micro-objective, filtered by a Glan–Thompson polarizer, and intercepted by a germanium photodetector connected to a digital power meter.

The transmittance of each demultiplexer output was determined by normalizing the power at the output ports to the power at the reference port produced by the MMI power divider, effectively calibrating out the input and output coupling losses and the waveguide propagation loss. Figure 4 shows the measured transmittance of the fabricated device. We measured an insertion loss as low as $1.1 \pm 0.36\;{\rm{dB}}$ which is unprecedented for demultiplexers in fully etched thin SOI platforms [7,13,30]. The crosstalk is less than ${-}{{25}}\;{\rm{dB}}$, and the mean 3 dB cumulative XT as defined in [29] is ${-}{{23}}\;{\rm{dB}}$, i.e., which, to the best of our knowledge, is the lowest value yet reported for a curved waveguide demultiplexer and comparable to other more established demultiplexer architectures in an SOI ([7,13,30]). The best AWG demultiplexers implemented in fully etched thin silicon platforms achieve insertion loss worse than 2.9 dB and crosstalk higher than ${-}{24.4}\;{\rm{dB}}$ [29], while the best CWG demultiplexer has an insertion loss higher than 3 dB and XT higher than ${-}{{25}}\;{\rm{dB}}$. The 3 dB bandwidths of the fabricated device range from 4.6 to 5.3 nm.

 

Fig. 4. Measured transmission spectra of the fabricated demultiplexer. The circles indicate the channel cumulative crosstalk as defined in [29].

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In summary, we have demonstrated a CWG demultiplexer for the SOI platform. We accomplished a significant reduction of the off-chip radiation loss that previously hindered the practical utilization of this type of demultiplexer. In our device, the loss reduction is achieved through the operation in the single beam condition of the grating waveguide using metamaterial refractive index engineering. We designed an eight-channel demultiplexer with a channel separation of 10 nm (1249 GHz). The fabricated device exhibits low loss ($\sim 1\;{\rm{dB}}$) and crosstalk of ${-}{{25}}\;{\rm{dB}}$. The device reported here is the best performing CWG demultiplexer to date, with the performance comparable or exceeding the state-of-the-art devices in SOI. We believe that these results pave the way towards the wider adoption of this new demultiplexing architecture in integrated photonics.