Diffraction gratings and more generally diffractive optical elements (DOEs) are widely used in a broad range of industrial and commercial applications [1], such as spectroscopy [2], beam shaping [3], beam splitting [4], beam sampling [5], and pattern generation [6]. Applying an adequate design methodology, DOEs enable the creation of a target wavefront tailored for a particular application. By modulating either amplitude or phase (or both simultaneously), DOEs can be designed to create specific diffraction patterns in either the near-field (Fresnel DOE) or the far-field (Fourier/Fraunhofer DOE).

Single crystal diamond (SCD) is a material that presents an exceptional combination of mechanical and optical properties. High thermal conductivity and a high laser-induced damage threshold (LIDT, $2\;{\rm{GW}}\;{\rm{c}}{{\rm{m}}^{- 1}}$ at 532 nm [7] for 1 ns pulses at a beam radius of 50 µm compared to $5\;{\rm{GW}}\;{\rm{c}}{{\rm{m}}^{- 1}}$ for fused silica for 5 ns pulses at a beam radius of 60 µm [8]), combined with high hardness and excellent chemical resistance, make diamond a substrate of choice for high-power applications. A wide transparency window ranging from the deep UV to the far IR combined with a large refractive index (2.417 at 635 nm [9]) enables the creation of thin optical elements working across a broad spectrum. Owing to the superior material quality, the commercial availability of high-quality SCD and advances in nanostructuring methods have recently led to increased interest for exploiting diamond in optical and photonic applications [10,11], including micro-optical lenses and lens arrays [12,13].

Applications utilising diamond elements for high-power applications have been demonstrated for Raman lasers [14], exit windows [15,16], and mirrors [11], opening up a new direction of study as the material of choice for such components has been fused silica [5,17]. The use of diffractive elements enables the engineering of the intensity distribution within the beam, which yields improved control of the welding process. A precise control of the beam shape in welding is of particular importance [18,19] in order to control the volume of the molten metal and thus enabling the shaping of the weld pool to the application’s requirement.

In this work, we demonstrate near-field diamond DOEs in SCD. Specifically we demonstrate an efficient design and fabrication process for transmission binary phase SCD DOEs aimed at high-power applications, which benefit from the exceptional properties of SCD. Expanding on our previous work to fabricate high-quality triangular and trapezoidal profile diffraction gratings [20,21], we here employ surface smoothing, e-beam lithography, and diamond reactive ion etching to demonstrate flat-top beam shapers targeted for copper welding application with the aim of providing better control of the weld pool [22], with design and characterization of the device.

The DOE is formed by a structured diamond surface with specific areas varying in depth. The resulting variations in the optical path effectively modulate the phase of the transmitted coherent beam (Fig. 1a). The amplitude of the phase modulation depends on the etch depth, wavelength, and refractive index of the substrate ($\Delta \phi = d \cdot {k_0}({n_d} - 1)$); thus, in order to achieve a $\pi$ phase shift, an etch depth of 187 nm is required in diamond.

 

Fig. 1. Operating principle. (a) Working principle of our DOE: collimated beam is phase-modulated by the DOE resulting in diffraction with the designed transverse beam intensity profile at a set distance from the DOE. (b) Binary phase profile of our DOE made of a $3000 \times 3000$ grid (${{1}} \times {{1}}\;{\rm{\unicode{x00B5}{\rm m}}}$ resolution). The black and white regions represent the 0 and $\pi$ phase levels, respectively. (c) Subsection of our DOE showing the computer-generated features designed to diffract light into a ${{600}} \times {{600}}\;{\rm{\unicode{x00B5}{\rm m}}}$ square of uniform intensity.

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We developed a variation of the iterative Fourier transform algorithm (IFTA) [23], using the thin element approximation (TEA) [24], effectively neglecting diffraction inside the substrate and other effects related to the finite thickness of the substrate, such as scattering and higher order diffraction. The phase distribution of a $3000 \times 3000$ grid (chosen to limit computational effort, ${{1}} \times {{1}}\;{\rm{\unicode{x00B5}{\rm m}}}$ per point) is computed as required on the DOE to obtain the target intensity distribution at the working distance. This differs from far-field DOEs where the angular spectrum (equivalent to the far-field intensity distribution) is the optimization target [25]. The computed phase distributions are shown in Figs. 1(b) and 1(c). The TEA is valid as long as the feature size is large compared to the wavelength, and the element thickness is comparable with the wavelength [26]; furthermore, it is only valid under paraxial illumination [24].

Based on the fabrication process, only a discrete set of ${2^n}$ depths (or $z$-levels) can be addressed, where $n$ is the number of lithography and etch cycles. For a proof of concept demonstration, we explore a single e-beam lithography and diamond etch cycle to form a binary phase profile. This constraint was implemented in our IFTA algorithm using stepwise quantization [27,28]. A different IFTA algorithm, like mixed-region amplitude freedom (MRAF) [29] could also be used. It was found that stagnation can further be avoided by periodic relaxation of the quantization constraint [30] and by adding Gaussian noise following ${\cal N}{(0,0.25^2})$ to the phase of a randomly selected fraction of the points of the DOE after each iteration of the algorithm. While there are a multitude of algorithms for computing phase profiles, for example weighted Gerchberg–Saxton (GSW) [31] and optimal-rotation-angle (ORA) [32], this IFTA method was chosen for its relative simplicity while providing good performance for discrete phase DOEs with binary target intensity [33].

We conceived a square flat-top DOE, designed to shape the beam into a ${{600}} \times {{600}}\;{\rm{\unicode{x00B5}{\rm m}}}$ square of uniform intensity at a working distance of 15 mm and to be used at a wavelength of $\lambda = 532\;{\rm{nm}}$ commonly employed in copper welding. Once computed, the DOE phase distribution can be used to simulate the resulting object plane intensity. The theoretical diffraction efficiency obtained through these simulations for our binary phase square DOE is approximately 50%. Further improvements can be achieved by using 4, 8, 16, or 32 $z$-level DOEs.

Fabrication of the DOEs (Fig. 2a) was carried out on general grade SCD plates with dimensions of ${{3}}\;{\rm{mm}} \times {{3}}\;{\rm{mm}} \times {0.25}\;{\rm{mm}}$ (Element Six). The plates were cleaned in hot Piranha (${{\rm{H}}_2}{{\rm{SO}}_4}:{{\rm{H}}_2}{{\rm{O}}_2}$, 1:1, 100°C, 10 min) and subsequently in concentrated hydrofluoric acid to remove organic and polishing slurry contaminants. During subsequent steps, the diamond chip is attached to a carrier wafer (Si for e-beam and oxidized Si during etching) using QuickStick 135 mounting wax for handling and compatibility with standard microfabrication equipment.

 

Fig. 2. Fabrication. (a) Microfabrication process-flow: i, cleaning in hot Piranha (${{\rm{H}}_2}{{\rm{SO}}_4}:{{\rm{H}}_2}{{\rm{O}}_2}$, 1:1) and subsequently in concentrated hydrofluoric acid followed by high-angle IBE polishing [34]; ii, sputtering of silicon hardmask; iii, spin-coating of HSQ negative resist (FOX-16, thickness ${\sim}500\;{\rm{nm}}$); iv, electron beam lithography (Raith EBPG ${{5000 +}}$), and development in TMAH; v, chlorine-based reactive ion etching (RIE) patterning of the Si layer (STS Multiplex ICP); vi, highly directional ${{\rm{O}}_2}$ plasma etch of diamond substrate (STS Multiplex ICP, 400 W ICP power, 200 W bias power, 30 sccm ${{\rm{O}}_2}$, 15 m Torr); vii, stripping of the hardmask using a wet silicon isotropic etch (${\rm HF}:{{\rm{HNO}}_3}:{{\rm{CH}}_3}{\rm{COOH}}$). (b) Scanning electron microscopy (SEM) recording of the diamond diffractive optical element surface after fabrication. (c) Atomic force microscope (AFM) recording of the DOEs surface revealing a feature depth of 83 nm.

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To remove surface asperities, an ion beam etching-based (IBE) polishing process [34] was carried out. A first normal incidence etching step removes the remaining contamination after which a second etching step, at oblique incidence, performs polishing due to the angle-dependent etch rate. A third normal incidence step recovers the nanoscale smoothness. Amorphous silicon was deposited via sputtering to serve as a hardmask. Silicon was chosen due to the good selectivity during the diamond etch, acting as a conductive layer during electron beam exposure, resisting to the developer (TMAH), and having a good adhesion to both diamond and the electron beam resist. Electron beam lithography (Raith EBPG 5000+) was carried using HSQ negative resist (FOX-16, thickness ${\sim}500\;{\rm{nm}}$), with a matching pattern and resolution of the simulation for fidelity of comparison. Chlorine chemistry reactive ion etching was used to pattern the Si layer (STS Multiplex ICP). Transfer of the pattern into diamond was carried out using highly directional ${{\rm{O}}_2}$ plasma (STS Multiplex ICP, 400 W ICP power, 200 W bias power, 30 sccm ${{\rm{O}}_2}$, 15 m Torr). The etch produces smooth surfaces and vertical sidewalls, comparable in result to the techniques used to create initial recessions for quasi-isotropic etch processes [35–37], but with a higher etch rate ($110\;{\rm{nm}}\;{\rm{mi}}{{\rm{n}}^{- 1}}$) and simpler material stack. The hardmask and HSQ were stripped using a wet silicon isotropic etch (${\rm HF}:{{\rm{HNO}}_3}:{{\rm{CH}}_3}{\rm{COOH}}$). The devices were subsequently characterized through scanning electron microscopy (SEM) and atomic force microscopy (AFM) [Figs. 2(b) and 2(c)], which revealed an etch depth of ${\sim}83\;{\rm{nm}}$. High-aspect ratio AFM measurements reveal a sidewall angle of 88.7°. The etch depth is controlled by a timed etch, and the experimentally obtained etch depth still enables a high-quality beam profile.

The DOEs were characterized in an optical transmission setup (Fig. 3) consisting of a 532 nm laser and a spatial filter designed to expand and collimate the beam to the required diameter (approx. 2 mm $1/{e^2}$). The DOEs were inserted into the beam path using a three-axis linear translation stage enabling accurate positioning. Due both to the short working distance (15 mm) and the small object size of the DOE, the object plane was magnified using a ${{3}.{5\times }}\;{{0}.\rm{1NA}}$ microscope objective and imaged onto a complementary metal-oxide-semiconductor (CMOS) array sensor (Basler acA1300-30uc). Camera gain was reduced to its minimum to reduce noise, and exposure was adjusted to assure maximum dynamic range, while keeping the fraction of saturated pixels under 1% (on the green channel). No contrast correction was applied.

 

Fig. 3. Optical characterization. (a) Experimental setup: a 532 nm CW laser, a 10 nm bandpass filter centered at 532 nm, a spatial filter designed to clean and expand the beam to the required width, the DOE itself, a 3.5x 0.10 NA microscope objective imaging the object plane onto a CMOS array. (b) Beam profile created by a square beam shaper DOE as imaged by the CMOS detector. Inset, we show the flexibility of our design and fabrication method by making a beam shaper forming the logo of our institution (EPFL). (c) Simulated beam profile. (d) Vertically integrated intensity of the beam profile.

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The measured beam profile (Fig. 3b) shows good agreement with the simulated results obtained using a split-step beam propagation method [38] (Fig. 3c). The observed intensity yields good uniformity, with individual speckles inherent to the DOEs. The intensity variation due to speckles is expected to be sufficiently small to allow efficient heat flow from the bright speckles to the dark speckles during welding operations. The vertically integrated beam profile (Fig. 3d) shows a sharp transition between the inside and outside of the 600 µm square of the order of 3 pixels (3.2 µm on the object plane), which is close to the resolution of our system (0.1 NA). The contrast between the square and the background (${\sim}4:1$) is slightly inferior to that of our simulations due to a higher residual transmission component, which we attribute to scattering inside the DOE and on our imaging optics, as well as interference created by the IR-block filter present on our CMOS array sensor. Additionally, we measure a uniformity of ${\pm}16\%$ RMS within the square close to the ${\pm}12\%$ RMS predicted by our simulations (uniformity was measured using a 20 µm Gaussian filter to remove high frequency components due to the presence of speckles).

Additionally we show the versatility of our design and fabrication method by creating an arbitrarily shaped DOE representing the logo of our institution (Fig. 3b, inset).

Our experimental results demonstrate a powerful approach to designing and manufacturing binary DOEs in SCD. We demonstrate the generation arbitrary patterns in the near-field, which is of high practical value for the production of DOEs for use in high-power applications that benefit from the excellent optical and thermal properties of SCD, without requiring additional lenses.

A top-hat near-field beam shaper diffractive element was designed, fabricated, and experimentally characterized. The designed element transforms the incoming Gaussian beam into a ${{600}} \times {{600}}\;{{\unicode{x00B5}{\rm m}}}$ square of uniform intensity at a wavelength of $\lambda = 532\;{\rm{nm}}$ with a theoretical efficiency of ${\sim}50\%$ and uniformity of ${\pm}12\%$. Fabrication was carried out using e-beam lithography and reactive ion etching to create the binary relief pattern, with a resolution of 1 µm and etch depth of 187 nm (83 nm actual). The fabricated element was optically characterized, showing close to diffraction-limited performance, 4:1 contrast, and a ${\pm}16\%$ uniformity. These results indicate reliable transfer of the design patterns, resulting in high optical performance matching simulated values.

Further improvements can be made both in the design and fabrication phase such as the use of a greater number of $z$-levels, which can by itself greatly improve the diffraction efficiency of our devices and the addition of antireflection coatings or structuring [25] to reduce Fresnel reflection. Furthermore, the fabrication process can be straightforwardly adapted to photolithography, enabling large scale commercial exploitation.

The code developed for designing and simulating our DOE is distributed under the GNU General Public License v3.0 and is available at [39] together with the specific design of the DOE presented in this paper.