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Abstract
Dynamic polarization controllers (DPCs) are essential devices in various optical applications. We develop a thin film lithium niobate (TFLN) integrated DPC driven by the real-time implemented Jacobian control algorithm for fast polarization tracking. Experimental results demonstrate a high polarization tracking speed of 100 krad/s when targeting a specific linear state of polarization, with a low control loop delay of 420 ns, half-wave control voltages of 2.75 V, and a fast polarization restoring time of 1.6 us. Compared to previously reported integrated DPCs, the TFLN-based DPC achieves significantly higher tracking speed and lower loop delay. The results highlight the effectiveness of the Jacobian method and the outstanding performance of TFLN-based DPCs. The study opens up possibilities for further advancements in DPC solutions using TFLN technology.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
The state of polarization (SOP) tracking has been extensively studied in a wide range of optical applications, including optical remote sensing [1] and optical communications [2,3]. Dynamic polarization controllers (DPC), the enabling device for polarization tracking, have been proposed and studied since the 1980s, primarily for use in coherent optical communications [4–6]. The DPC transforms a time-varying input SOP to a fixed output SOP based on multiple selections of optical devices, such as fiber squeezer [4,7], lithium niobate (LN) crystal [8–11], plasma [12,13], etc. It has recently found more applications in various studies, such as polarization mode dispersion (PMD) compensation, quantum key distribution [14,15], and optical polarization demultiplexing [16,17]. The wide acceptance of lithium niobate (LN) crystal for DPC is due to its fast electro-optical response. The LN-based DPCs have appeared as commercial products for many years and still hold the record for polarization tracking speed. However, the relatively large size (on the order of centimeters) and high control voltage requirement [18] seriously limit its applications in more integrated systems such as optical transceivers [19,20]. As a solution, the photonic integration shows promise of much smaller DPC devices with much lower control voltages. For example, a silicon-on-insulator (SOI) platform is used to fabricate the first fully integrated DPC [21], showing compatibility with the complementary metal-oxide-semiconductor (CMOS) technology and offering the advantages of compact footprint. A silicon-based integrated DPC with an in-line polarimeter demonstrates a SOP tracking speed of 21.45 krad/s with a 30 us control loop delay [22], thin film lithium niobate (TFLN) has recently emerged as a promising DPC platform [23,24], with a even faster response and lower control voltages.
The DPC usually operates in an endless tracking mode [25–27], i.e., the DPC needs to lock to the desired SOP continuously with the constraint of limited control voltages range. The endless operation poses challenges to the design of an appropriate control algorithm. Multiple algorithms are available, such as gradient descent (GD) [28], simulated annealing (SA) [27], greedy linear descent (GLD) algorithm [29], etc. However, they are either too computationally demanding or require some sort of voltage resetting during the endless tracking. Previously, we have developed a robust and completely reset-free control algorithm, the Jacobian method [30], by drawing parallels between DPC problem and robotics. This paper applies the field programmable gate array (FPGA) implemented Jacobian algorithm to control the fabricated TFLN-integrated DPC device. The experimental results confirm a polarization tracking speed of 100 krad/s when the DPC targets a specific linear SOP, with the control loop delay as small as 420 ns, the half-wave control voltages 2.75 V, and a polarization restoring time of 1.6 us.
2. Working principle
2.1 Schematic design of the TFLN based integrated DPC device
The schematic structure of the proposed TFLN integrated DPC device has three building blocks, i.e., edge couplers, polarization splitter and rotators (PSRs), and cascaded Mach-Zehnder interferometers (MZIs), as shown in Fig. 1(a). The edge coupler with low polarization dependence is used as the fiber-to-chip interface, as shown in Fig.1 (d). The edge coupler is comprised of two stacked inverse tapers to improve the polarization independence. The inverse taper has a gradual increase in width along the mode propagation direction, with the narrow end of the taper closer to the lensed fiber, while the wider part is connected to the photonic waveguides. Specifically, the parameters of the inverse taper are optimized as follows: $w_{\rm {ec}} =$ 0.79 um, $h_{\rm {ec}} =$ 0.4 um, $h_{\rm {LN}} = 0.2$ um, $w_{\rm {hole}} =$ 5 um, and $h_{\rm {hole}} =$ 29.2 um.
Fig. 1. (a) 3D view of the proposed DPC device on the TFLN platform whole structure. (b) The SEM and parameters of 3-dB 2x2 MMI. (c) The logical setup of the DPC device. (d) The schematic diagram of the edge coupler and (e) the polarization splitter and rotator. (f) Simulated fundamental TE optical mode profile and static electrical field vector distribution. (g) Experimental results of the edge coupler, (h) half wave-voltage, and (i) polarization splitter and rotator.
The PSR [31] transforms the fundamental modes into two transverse-electrical (TE) modes in the upper and lower TFLN waveguides, as shown in Fig. 1(e). Note that the mode evolution occurs among super modes of the two TFLN waveguides, which makes the device more compact. In the transforming region of the PSR, the width of the upper waveguide $w_1$ is set to 1.0 um, while the width of the lower waveguide $w_2$ varies from 0.2 to 0.6 um. The gap of the two waveguides $g_2$ remains constant ($g_2$ = 0.4 um) in the transforming region, while it extends to $g_1 = g_3 = 1.4$ um in the input/output regions to reduce the crosstalk between the two waveguides [32]. The length of the PSR in the input, transforming and output regions ($L_1, L_2, L_3$) are set to 100, 1000, and 140 um, respectively. As shown in Fig. 1(b), the four 3-dB 2$\times$2 multi-mode interferometer (MMI) couplers have five parameters, including the width of the taper ($w_c$ = 2.5 um), the length of the taper ($L_t$ = 10 um), the gap of the two taper ($g$ = 1 um), the gap of the two taper ($g$ = 1 um), the width and length of the middle interference region ($w$ = 9.8 um, $L$ = 91 um).
As stated in Fig. 1(c), the schematic setup of the device show that spatial light has been divided into fundmental modes (TE$_0$, TM$_0$) of TFLN waveguide through ECs. After that, the PSR evolutes the TM$_0$ to TE$_0$ of the lower waveguide, while the TE$_0$ go through the origin waveguide directly. With the control of the FPGA, The cascaded MZIs will act as waveplates to trace the polarization of light. The cascaded MZIs are composed of four EO phase shifters (PSs) and four 3-dB 2 $\times$ 2 MMIs. The first and the third PSs (PS1 and PS3) act as the polarization rotators around S1 axis, while 3-dB MMI couplers together with the followed PSs and MMIs (MMI-PS-MMI) act as the polarization rotators around S3 axis in the Poincaré sphere. In general, this architecture allows the input arbitrary SOP of light to be transformed to arbitrary SOP at the output port. The four PSs are implemented in a single-drive push-pull configuration to reduce the driving voltage. The simulated fundamental TE optical mode profile and static electrical field vector distribution of the PSs are shown in Fig. 1(d). Tradeoffs between low half-wave voltage and low optical absorption are made during the design of the coplanar electrodes of the PSs, with ($w_s, t, g, h$) = (8, 1.1, 4.3, 0.7) um. The modes have selectivity in the part of edge couplers which have high couple-efficiency of the fundamental mode, including TE$_0$ and TM$_0$, and the waveguide just has TE$_0$ for modulation and transmission since TM$_0$ has been transfer into TE$_0$ by PSR.
The device is fabricated on a commercial X-cut LN-on-insulator wafer (NanoLN) with a 500-um thick silicon substrate layer, a 3-um thick buried oxide (BOX) layer, and a 400-nm thick TFLN layer. The TFLN waveguide, along the Y axis of the LN, has a ridge height of 200 nm, a slab height of 200 nm, and a width of 1.6 um. The whole TFLN structure is coated with a 700-nm-thick $\rm {SiO_2}$ over-cladding layer. Followed that, 1.1-um thick Au electrodes are adopted. The edge couplers feature a polarization dependent loss (PDL) of $\sim$ 0.5 dB, an optical bandwidth of > 100 nm, and a coupling loss of < 1.8 dB (see in Fig. 1(g)). For the PSR, Fig. 1(i) indicates that a measured insertion loss of < 0.5 dB is obtained over a 110-nm wavelength band [31]. When single stage, which have 1.5-cm length of modulation arm, is modulated by a zigzag wave with a frequency of 100 kHZ and a peak-to-peak voltage of 20V, we obtain a $V_{\pi }$ of 2.75 V (see in Fig. 1(h)). Furthermore, the whole device with four 1.5-cm cascaded PSs also exhibits an on-chip loss of < 2 dB. The footprint of the device is 1.8 cm $\times$ 4 mm.
2.2 Jacobian method
The SOP is defined as a real-value Stokes vector $S = [s_1,s_2,s_3]^T$, where $T$ denotes transpose, and it satisfies the condition $s_1^2+s_2^2+s_3^2 = 1$. We denote the input and output SOP as $S_{\rm {in}}$ and $S_{\rm {out}}$, respectively. The $m$-stage DPC problem can be formalized as $S_{\rm {out}} = f(\boldsymbol {\varphi })S_{\rm {in}}$, where the function $f(\boldsymbol {\varphi }) = M_m(\varphi _m)M_{m-1}(\varphi _{m-1})\cdots M_1(\varphi _1)$ models the effects of $m$ control stages and $\boldsymbol {\varphi } = [\varphi _1,\ldots,\varphi _m]$ represents the vector of $m$ control signals applied to DPC. The DPC model is linearized as [30]:
where $J$ is a $3\times m$ Jacobian matrix, $\Delta \boldsymbol {\varphi }$ and $\Delta S_{\rm {out}}$ are the tiny increments of control signals and SOP.Typically, in order to achieve endless SOP tracking with any desired locking target, a polarimeter is employed to acquire the real-time Stokes vector and calculate the error signal $\Delta S_{out}$. However, when the DPC target is a specific linear SOP, such as $s_1=1$, we can simplify the output space to one dimension, eliminating the need for a polarimeter. To achieve this stabilization, we redefine Eq. (1) as $j\Delta \boldsymbol {\varphi } = \Delta s_1$, where $j\in 1\times m$ and $\Delta s_1 = 1-s_1$. We have realized this algorithm on FPGA and its flow chart is illustrated in Fig. 2(a). Using the dithering technique, $\boldsymbol {s_\varphi } = [s_{1|\varphi _1},s_{1|\varphi _2},\ldots,s_{1|\varphi _m}]$ and $s_1$ are returned as the feedback signals to obtain the gradients of control signals $\partial s_1 /\partial \boldsymbol {\varphi }$. Each element of $\boldsymbol {s_\varphi }$ corresponds to the value of $s_1$ obtained after applying dither signal $\Delta \varphi$ to the corresponding control stage. This process is illustrated in Fig. 2(b). Figure 2(b) is the sequence diagram of a single control loop, where $k$, $k+1$ represent 2 adjacent processing cycles. With $\varphi _i(k)+\Delta \varphi$ applied to the $i$th stage, we can obtain the corresponding feedback signal $s_{1|\varphi _i}$ in $T_1$. These values will be subsequently sent to the calculation module, and the control voltages will be adjusted to achieve real-time SOP tracking. Let $T_2$ represent the duration of each dithering signal and $T_3$ denote the time required for the calculation process. It’s assumed that the control loop consumes $T = T_1+m\times T_2+T_3$ for a $m$-stage DPC. Besides, the total consumption is also influenced by both the practical implementation of the algorithm and hardware performance factors, such as process latency and primary clock. Note that in our previous work [30], we extensively described how adding the control stages appropriately can improve the performance of DPC. However, this approach may not always be effective, as increasing the number of control stages $m$ also means an increase in loop delay and a more complex hardware implementation. The selection of $m$ is a compromise between loop delay and system’s redundancy. This is why we ultimately chose to implement a 4-stage DPC.
3. Result and discussion
3.1 Setup of experiment
The scheme of the experimental setup is illustrated in Fig. 3. The unmodulated wave beam is generated by a 1550 nm DFB laser, whose SOP initially locates at $S_{\rm {in}} = [1,0,0]^T$. The wave beam passes through a commercial polarization scrambler (Novoptel EPS1000), which can be modeled as a rapidly rotated half-wave plate (HWP) sandwiched between two blocks of two quarter-wave plates (QWP) that rotate relatively slowly. As a result, the SOP becomes disturbed and finally locked to the target after being converted by DPC. The integrated DPC consists of four control stages. After the DPC, the light beam is divided into two paths by a $1\times 2, 10:90$ coupler. A commercial polarimeter (Keysight, N7786B) is included in the $90{\%}$ path to monitor the real-time SOP. In the $10{\%}$ path, a polarization beam splitter (PBS) is followed by a balanced photodetector (BPD) to measure the feedback signal $s_1$, which is then sent to the FPGA to help endlessly adjust the control voltages. An analog-to-digital converter (ADC) and four digital-to-analog converters (DAC) are used to receive feedback and send control signals. Behind each DAC, a 1 $\times$ 2 power splitter (PS) is inserted, dividing the control signal into two paths. One path is directly applied to the DPC. Meanwhile, an oscilloscope (OSC) is connected to the other path to record the varying control signals. $T_1$, $T_2$ and $T_3$ mentioned in section 2.2 are 140 ns, 40 ns and 120 ns respectively. These values are used to calculate the control loop of the 4-stage system, resulting in $T$ = 420 ns. We measured a coupling and on-chip insertion loss of 5 dB for the TFLN device, and $\sim$ 7 dB for the entire DPC.
For testing purposes, a polarization scrambler is used to estimate the fastest SOP variation speed that the stabilizer can track. As illustrated in the dashed box, the speeds of QWPs are symmetrically set as 100 rad/s and 300 rad/s, while speed of HWP, denoted as $v$, is set as the fastest to ensure that the scrambled SOP appears approximately equidistributed on the Poincaré sphere. By employing a polarimeter to detect the output SOP at a sampling rate of 50 kHz, we use relative intensity error ($\rm {RIE}$) to evaluate the tracking effect [8,33], which can be written as $\rm {RIE} = \rm {sin^2(\delta /2)}$, where $\delta$ is the excursion angle between the actual and desired SOP.
3.2 Endless and reset-free polarization control
Figure 4(a) illustrates the complementary cumulative distribution function 1-F(RIE) of RIE. This statistical distribution represents the cumulative probability that the RIE (abscissa value) is exceeded in the experiment. The logarithmic ordinate aids in understanding the degradation of DPC in rare circumstances. Each curve represents a RIE measurement at a specified SOP scrambling speed ranging from 0 krad/s to 400 krad/s over a duration of 2 seconds. The leftmost and rightmost curves serve as reference measurements. The former represents the result with the scrambler disabled, while the latter depicts the measurement at a scrambling speed of 400 krad/s without any applied DPC scheme. It can be observed that, at high scrambling speeds (up to 400 krad/s), the RIE value remains below 0.2 with a probability exceeding 0.99 (equivalent to $10^{-2}$ on the ordinate). Considering that the highest tracking speed in [22] is estimated under the condition that the normalized optical error power remains below −10 dBm (equivalent to RIE < 0.1), we consider the highest tracking speed of our DPC to be 100 krad/s, given that it is the maximum speed where the RIE remains below 0.1. To the best of our knowledge, this result represents the highest tracking speed achieved among the existing integrated DPC schemes when the target is a linear SOP.
Meanwhile, the excursion angle can be expressed as $\delta = 2\rm {arcsin}(\sqrt {RIE})$. Figure 4(b) shows the standard deviation ($\delta _{\rm {std}}$) of $\delta$ in both experimental and simulation datas. Both curves exhibit the same varying trend, with the experimental result reaching a maximum value of 0.183 rad ($10.48^{\circ }$) at a scrambling speed of 400 krad/s. The DOP remains above 0.9 and $\delta _{\rm {std}} = 0.096$ rad ($5.5^{\circ }$) at the scrambling speeds of 100 krad/s. Upgrading the electronic hardware would undoubtedly lead to improved tracking performance.
Fig. 4. (a) Complementary cumulative distribution function (CCDF) of the relative intensity error, each measured in sampling rate of 50 kHz over 2 seconds. (b) Standard deviation of simulation (cyan line) and experiment (red line) result is plotted. The DOP of the measurement is illustrated as black line.
We have demonstrated the reliability and practicality of the gradient projection (GP) method in reducing the applied control signals [30]. The key to this method is eliminating redundant components in the null space of the signal vector $\boldsymbol {\varphi }$, thereby constraining it within an optimal range. Since the output voltages of our DACs are limited to $|V_{\rm {max}}| = 12\;\rm {V}$, we take −10 $\sim$ 10 V (nearly $\pm \;3.64\;V_{\pi }$) as the ideal variation range of control voltages. An oscilloscope is used to record the varying control voltages at a sampling rate of 12.5 kHz. Figure 5(a) illustrates the CCDF of the first-stage voltage $V_1$, with each curve obtained over a duration of 5 seconds. $V_1$ typically exhibits the widest range of variation and is most likely to exceed the control boundary, making it the most representative of the control signals. It is observed that the variation range increases with higher scrambling speeds. However, even at scrambling speeds up to 300 krad/s, the probability of $|V_1|>3.64\;\rm {V_{\pi }}$ remains as low as $1.45{\%}$, and $|V_1|$ keeps below 6 V (2.2 $V_{\pi }$) at the rate of 100 krad/s. The distribution of $V_1$ at different scrambling speeds is depicted in Fig. 5(b)-(e), all of which centers around zero. These distributions indicates that the control signals rarely approach the hardware-limited boundary, which strongly supports the effectiveness of the GP method. These results strongly confirm an effective reset-free polarization tracking limited with a voltage range of $\pm \;2.2\;V_{\pi }$ at the rate of 100 krad/s.
Fig. 5. (a) Complementary cumulative distribution function (CCDF) of the first-stage control voltage $V_1$ at different scrambling speed from 10 krad/s to 300 krad/s. (b)-(e) Histogram of $V_1$ at different scrambling speed.
3.3 System’s response to discontinuous change in input SOP
No matter how fast the scrambling speed of the scrambler is, the disturbed input SOP mentioned above is actually “continuous-varying”. However, a discontinuous and sharp change in input SOP will significantly affect the stabilizer’s output, which corresponds to sudden external disturbances, such as lightning strikes [34]. We introduced the concept of recovery time to assess the system’s robustness and stability, which is defined as the time needed for the input SOP to stabilize after violent scrambling. As shown in Fig. 6(a), we use a commercial polarization controller (CPC) to apply sharp disturbance to the input SOP. With a periodic step signal $V_{\rm {step}} = \pm 5\;\rm {V}$ applying to the CPC to induce discontinuous changes in input SOP, Fig. 6(b) shows the corresponding change in $s_1$ when the scrambler operates at a speed of 10 krad/s and the stabilizer is not in use. The periodic fluctuations on the red curve indicates that $V_{\rm {step}}$ clearly induces a sharp change in the input SOP.
Fig. 6. (a) Experimental setup to test system’s response to discontinuous change in input SOP. (b) Step signal $V_{\rm {step}} = \pm \;5\rm {V}$ and corresponding discontinuous change in $s_1$ while the stabilizer is not in use.
Figure 7(a) shows the scrambling step signal $V_{\rm {step}} = \pm 5\;\rm {V}$ applied to the CPC. With the stabilizer in Fig. 6(a) starting to work, Fig. 7(b) illustrates the emulated and experimental response of our stabilizer to this discontinuous disturbance. The recovery time, denoted as the full width at half maximum (FWHM) $T_{\rm {H}}$, is estimated from the response curve. Figure 7(c) provides a detailed illustration of the process of discontinuous change and recovery. In the experiment, the recovery time is $T_{\rm {H}} = 1.6\;\rm {us}$, while the emulated result demonstrates a recovery time of $T_{\rm {H}} = 0.6\;\rm {us}$ for comparison. Since a single loop takes $T$ = 420 ns, this result signifies the ability of our system to stabilize the input SOP to the linear SOP within 4 to 5 loops, irrespective of the severity of the disturbance.
Fig. 7. (a) External step signal ($V_{\rm {step}}$) applied to disturb the input SOP. (b) Emulational and experimental results of our stabilizer reaction to discontinuous change in input SOP. (c) Detailed illustration of the process of discontinuous change and recovery.
4. Conclusion
We have demonstrated that integrated DPC are increasingly becoming the dominant solution in the field of DPC. Among these, TFLN-based PC exhibits exceptional performance due to its low $V_{\pi }$ and response time. We have developed an algorithm, as described in [30], to implement the Jacobian method for a 4-stage TFLN-based SOP stabilizer. This stabilizer achieves continuous and reset-free stabilization of the state of polarization (SOP) when the target SOP is linear ($s_1$ = 1). We demonstrate that the GP method is effective in reducing signal magnitude, and the control voltages are appropriately bounded within an ideal range of variation.
Table 1 summarizes the previously reported integrated DPCs, including their platform, working performance, algorithm, locking target and number of control stages. The tracking speed of our DPC is 4.7 times as high as in [22] and 10 times as high as in [23]. Despite consisting of four control stages, the maximum among all integrated DPC devices in Table 1, our DPC exhibits the smallest loop delay, which is only 1/26 of that in [27]. Furthermore, our stabilizer demonstrates excellent robustness and stability, as evidenced by its recovery time of only 1.6 us. The results of this study provide compelling evidence for the effectiveness of the Jacobian method in the field of DPC and the outstanding performance of TFLN-based DPC. We anticipate that there are many exciting possibilities for further advancements with this DPC solution in the future.
Table 1. Comparison of previously reported integrated DPC
Funding
National Key Research and Development Program of China (2018YFB1801800); Basic and Applied Basic Research Foundation of Guangdong Province (2021B1515120057); Science and Technology Planning Project of Guangdong Province (2019A050510039, 2020B0303040001); National Natural Science Foundation of China (62227819, U2001601).
Disclosures
The authors declare no conflicts of interest.
Data availability
All data included in this study are available upon request by contact with the corresponding author.
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