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Abstract
This paper reports the design, fabrication, and experimental demonstration of a monolithic silicon photonic (SiPh) 32×32 Thin-CLOS arrayed waveguide grating router (AWGR) for scalable SiPh all-to-all interconnection fabrics. The 32×32 Thin-CLOS makes use of four 16-port silicon nitride AWGRs, which are compactly integrated and interconnected by a multi-layer waveguide routing method. The fabricated Thin-CLOS has 4 dB insertion loss, < −15 dB adjacent channel crosstalk, and < −20 dB non-adjacent channel crosstalk. System experiments operated on the 32×32 SiPh Thin-CLOS demonstrate error-free communication at 25 Gb/s.
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1. Introduction
While today’s growing demands for information and data-centric applications are driving the need for high-throughput and energy-efficient computing beyond the current state-of-the-art, electronic switches and interconnects are adding the latency and the energy consumed in data movements in high-performance data centers and computing systems [1]. Optical interconnects are considered as a breakthrough technology that supports distance-independent data movements with extremely high bandwidth (> Terabit/s per waveguide) and energy efficiency (< pJ/bit). Besides, many High-Performance Computing (HPC) or scientific applications and deep learning (DL) frameworks make heavy use of all-to-all communication patterns [2]. Artificial intelligent accelerators also demand nearly-contention-free, high-throughput, and scalable data movement between the compute cores and the main memory [3]. Therefore, providing a compact and scalable all-to-all interconnection technology that can guarantee minimum-diameter connectivity and lowest latency among N nodes would be highly desirable. Recently, there have been several proposals [4–11] centered on the unique cyclic wavelength routing capabilities in arrayed-waveguide-grating-routers (AWGRs), which can offer high-radix all-to-all interconnection (Fig. 1(a, b, and c)). The theory of AWGR can be found in [12,13] and is briefly re-introduced here. AWGR is a passive optical shuffle device that can provide contention-free communication between any input port to any output port simultaneously, using different wavelengths. A $W\times W$ AWGR can support strictly non-blocking all-to-all interconnection between $W$ nodes in a flat topology (Fig. 1(b)), using $W$ wavelengths. Fig. 1(c) shows an example of the intrinsic wavelength routing functionality of a $4\times 4$ AWGR. Each input port uses 4 wavelengths to communicate to 4 output ports. Achieving such an all-to-all interconnects utilizing a silicon photonic AWGR on a silicon platform compatible with today’s CMOS ecosystem is considered extremely attractive for future computing system applications. For instance, the recent demonstration of silicon photonic 512$\times$512 AWGR [14] can achieve all-to-all interconnection between 512 nodes utilizing 512 wavelengths at the total aggregate data rate of multi Petabit/second (e.g. 512$\times$512$\times$20Gb/s = 5.24 Pb/s).
Fig. 1. All-to-all optical communication based on (a) direction fiber connection and (b) AWGR. (c) Wavelength routing functionality of a $4\times 4$ AWGR. $\lambda _i$ represents one of four operation wavelengths. The colors of the label $\lambda _i$ represent different input ports. (d) $N$-node Thin-CLOS architecture by using $K$ groups of $K$ $W$-port AWGRs, being $N=K\times W$. The $x$-th optical input port of the $y$-th node in group $z$ is labeled as $i_x^{y,z}$
A well-known issue with large port-count SiPh AWGRs is their high in-band crosstalk, due to their dense channel spacing (caused by the limited free spectral range (FSR)) and limitations of the fabrication process. All these factors can prevent AWGR-based interconnect systems to be practically realized at large scale ($\geq$32). To improve scalability, as Fig. 1(d) illustrates, the authors in [15] proposed an interconnection architecture called Thin-CLOS LION that can realize the same high-radix interconnects ($N\times N$) by utilizing multiples ($K^2$) of smaller AWGRs ($W\times W$, $N=K\times W$) using fewer number of wavelengths ($W=N/K$). As shown in Fig. 1(d), port $i_{x}^{y,z}$ (blue square) represents the $x$-th optical input port/waveguide of the $y$-th node in group $z$. For example, port $i_2^{1,2}$ is the 2nd optical port of the first node in group 2 (the first node in group 2 is node $W$+1). The total number of nodes is $N$ ($N=K\times W$). Each node is connected to $K$ optical I/O ports ($K$ input waveguides, $K$ output waveguides). Hence, the total number of optical I/O ports is $N\times K$. Although the number of optical ports is scaled up by a factor of $K$ compared to a single AWGR solution, Thin-CLOS has multiple significant advantages. It has much lower in-band crosstalk due to fewer ($N/K$) crosstalk components in smaller AWGRs. It offers larger channel spacing by using fewer ($N/K$) wavelengths within limited FSR. It also relaxes the fabrication constraints and improves the yield by utilizing smaller AWGRs. For instance, the recent demonstration of 64$\times$64 all-to-all interconnection utilized four silica 32$\times$32 AWGRs in parallel and 32 wavelengths [16]. This paper discusses in detail the first demonstration of monolithically-integrated silicon photonic Thin-CLOS LION for 32$\times$32 all-to-all interconnection consisting of four 16$\times$16 AWGRs on a single silicon substrate [17]. The remainder of the paper is organized as follows. Section 2 details the design method, simulations, and optimization results of the monolithic Thin-CLOS AWGR. Section 3 describes the fabrication process. Section 4 shows the testing results of building block components. Section 5 presents the spectra and system testing results of the 32$\times$32 Thin-CLOS prototype. Section 6 concludes the paper.
2. Monolithic thin-CLOS AWGR design
By the virtue of the relatively low effective index contrast offered by SiN/silicon-dioxide waveguides, SiN AWGRs typically have lower phase error, crosstalk, and insertion loss compared to their silicon counterparts [18]. Therefore, we designed our monolithic Thin-CLOS AWGR on a multi-layer SiN platform with silicon-dioxide cladding [19,20].
In a $N=K\times W$ Thin-CLOS system, the number of fiber connection scales as $2\times K^2\times W$ [16], which translates to $2\times K^2\times W$ photonic routing waveguides in a monolithic Thin-CLOS AWGR. A good multi-layer waveguide routing strategy is necessary to compactly route the large number of waveguides. It is worth noting that in a monolithic Thin-CLOS, the number of waveguide crossings of one channel, in the worst case, scales with the same order of magnitude as $2\times K^2\times W$, since the routing waveguides are responsible for intra-group and cross-group connections. As a result, the insertion loss and crosstalk caused by waveguide crossings could be significant when the Thin-CLOS scales out. Our goal is to route the large number of waveguides connecting between AWGRs and I/O ports with minimal footprint, while reducing the insertion loss and crosstalk at the waveguide crossings.
We developed a multi-layer waveguide routing strategy for our monolithic Thin-CLOS design utilizing five SiN layers. Fig. 2(a) illustrates the layer definitions and the routing method. Spatially, layer1 is the bottom layer while layer5 is the top layer. Optical signals are coupled between adjacent layers via inverse taper based adiabatic vertical couplers. Layer1 (red), layer3 (blue), and layer5 (green) are 150 $nm$ thick SiN routing layers where most of the routing waveguides lie on. Layer2 (yellow) and layer4 (brown) are 50 $nm$ thick SiN transition layers with short transition waveguides. The transition waveguides serve as a transitioning stage for the light to couple between the routing layers. The purpose of the transition waveguide is to double the interlayer gap between routing layers, reducing the crosstalk and insertion loss caused by interlayer waveguide crossings, while preserving high interlayer coupling efficiency.
We defined the primary directions for the three routing layers such that the routing waveguide directions of the three routing layers are distinct. Specifically, for the most part, waveguides of layer1 are along northeast-southwest direction, while those of layer3 are along east-west and those of layer5 are along northwest-southeast. Fig. 2(a) shows an example of the multi-layer routing, where channels 1, 2, and 3 represent the light transmitted from layer1 to layer3, layer5 to layer3, and layer1 to layer5, respectively. The waveguides (red or blue or green) on each routing layer are along the same primary direction. This approach prevents any intra-layer waveguide crossings which would potentially add to the crosstalk and insertion loss. The same approach also reduces the footprint significantly as the routing waveguides are in parallel for the most part, and they can be placed with high density. Furthermore, our waveguide routing method treats the transition waveguide as waveguides in both neighboring routing layers. For example, a transition waveguide on layer2 is considered as a waveguide on layer1 and a waveguide on layer3. Therefore, the transition waveguide would not cross the waveguides on neighboring routing layers (since intra-layer crossing is prohibited), preventing extra insertion loss and crosstalk.
Although primary directions are defined for each routing layer, bending waveguides are needed when the light is coupled between each layer, as shown in Fig. 2(a). To design the minimum bending radius, we considered the propagation loss in the bending region as well as the mode mismatch loss at the two facets where the bent waveguide is connected to straight waveguides. The minimum bending radius is designed to 150 $\mu m$ with 0.094 dB total loss for a 60-degree, 150 $nm$ SiN bending waveguide. This relatively large waveguide bending needs to be handled properly to avoid intersection with other bending or the routing waveguides. Our routing strategy assigns all the bending waveguides to be on either layer1 or layer5. By doing this, the bending waveguides on the same layer begin with the same direction, which is the primary direction of that layer, and end with the primary direction of layer3. With all the bending waveguides of the same layer pointing at the same direction, our routing method can aggregate them compactly without waveguide intersections.
An essential enabler of our multi-layer platform is the tri-layer vertical coupler which couples light between adjacent routing layers via a transition layer. We designed the tri-layer coupler by optimizing our tri-layer Y-junction and 3D coupler design [21]. The top view and side view is shown in Fig. 3(a) and (b), respectively. The gap between neighboring routing layers is 2$g$ + 50$nm$, where $g$ is the interlayer gap between 150 $nm$ SiN and 50 $nm$ SiN layers.
Fig. 3. Tri-layer inverse taper based low-loss coupler (a) top view and (b) side view. (c) FDTD simulation optimizing design parameters to couple light between 150 $nm$ layer (green) and 50 $nm$ layer (blue). (d) Power profile side view of interlayer coupling.
A trade-off in the platform design is between the interlayer coupling efficiency of the tri-layer coupler, and the insertion loss and crosstalk of the interlayer waveguide crossings. The mode field diameter of 150 $nm$ and 50 $nm$ SiN adiabatic tapers is typically between 2 $\mu m$ and 5 $\mu m$, which sets the upper bound of the gap $g$ to approximately 1-2.5 $\mu m$. On the other hand, we want $g$ as large as possible to minimize the insertion loss and crosstalk at waveguide crossings. The design parameters including taper length, waveguide width, and $g$, are optimized by FDTD simulation (Fig. 3(c) and (d)) to maximize the coupling efficiency at a reasonably large $g$ such that the insertion loss and crosstalk at waveguide crossings are low. Fig. 4(a) shows the FDTD simulation results of coupling efficiency between the 150 $nm$ and 50 $nm$ thick SiN layers, as a function of $g$, with other optimized dimensions being $W0$= 2.0 $\mu m$, $W1$ = 1.4 $\mu m$, $W2$ = 4.0 $\mu m$, $L1$ = 50 $\mu m$, $L2$= 200 $\mu m$. The tip width of all the inverse tapers is 250 $nm$ which is defined by the minimum feature size of our ASML stepper. The optimum coupling loss is 0.04 dB when $g$ is at 1 $\mu m$, which corresponds to about 2.05 $\mu m$ gap and 0.08 dB coupling loss between the 150 $nm$ SiN routing layers. Note that the coupling efficiency would be degraded when g decreases below 0.6 $\mu m$ (See Fig. 4(a)). This is because the 250 $nm$ taper tip caused discontinuities in the vertical coupler, resulting in mode mismatch loss at the taper tips. The mode intensity around the taper tip is high when g is small (e.g., <0.6 $\mu m$), and therefore causes higher mismatch loss resulting in coupling efficiency degradation. Fig. 4(b) and 4(c) shows the insertion loss and crosstalk between the routing layers as a function of gap. With a 2.05 $\mu m$ gap between the routing layers, the insertion loss at a waveguide crossing is 0.005 dB, and the crosstalk is −53 dB. The routing waveguide crossing angle is $60^{\circ }$ in our Thin-CLOS waveguide routing. It is worth noting that having $g$ at 1 $\mu m$ not only results in high coupling efficiency, low insertion loss and crosstalk at crossings, but also provides a satisfactory fabrication tolerance. As Fig. 4(a) shows, the coupling loss is < 0.05 dB when $g$ varies between 0.8 $\mu m$ to 1.4 $\mu m$. The efficiency degradation is only 0.01 dB when $g$ is off by $\pm$ 200 $nm$. It is also worth noting that, when necessary (e.g., designing a very large scale Thin-CLOS with $N$ = 512 or 1024), the design value of parameter g can be increased, which further lowers the crosstalk and insertion loss, at the expense of limited extra interlayer coupling loss (e.g., g=1.4$\mu m$, extra loss is < 0.01 dB).
Fig. 4. Simulation of (a) Coupling efficiency between routing layer and transition layer, (b) insertion loss from routing layer crossing, and (c) crosstalk from routing layer crossing
Besides the crosstalk, insertion loss, and coupling efficiency, another aspect to consider for designing parameter g is fabrication. Firstly, the silicon dioxide cladding thickness non-uniformity from oxide deposition will contribute to the non-uniformity of g. Secondly, the Chemical Mechanical Polishing (CMP) inaccuracy, caused by factors such as the polishing rate nonlinearity, affects the fabrication precision of g. Lastly, the oxide deposition induced stress should also be considered. For example, in our fabrication, the silicon dioxide was deposited on both sides of the wafer so that the stress from the glass is balanced to avoid wafer-bowing.
As a proof-of-concept demonstration, we designed a SiPh 32$\times$32 Thin-CLOS ($N$ = 32, $K$ = 2, $W$ = 16) using the proposed design methodology. It has 64 ($N\times K$ = 64) optical I/O ports (64 input waveguides, 64 output waveguides). The prototype Thin-CLOS has four 200-GHz-spacing 16$\times$16 SiN cyclic AWGR located on the bottom layer (layer1), preventing any possible performance degradation caused by the nonuniformity of optical thickness or stress across multilayers. The Thin-CLOS device footprint is 8.707 $mm$ $\times$ 8.001 $mm$. The vertical dimension is defined by the 127 $\mu m$ I/O waveguide spacing (8.001 $mm$ = 63 $\times$ 127 $\mu m$), to ensure compatibility with commercial 127-$\mu m$-spacing fiber arrays. The operating polarization of the Thin-CLOS device is Transverse Electric (TE). The detailed design procedures of the 16-port AWGR can be found in [14,22].
3. Fabrication
We fabricated the Thin-CLOS chip on a 150 mm Silicon wafer, as shown in Fig. 5, starting with Low-Temperature Oxide (LTO) deposited by Low-Pressure Chemical Vapor Deposition (LPCVD) serving as a bottom oxide cladding layer. All the five SiN waveguide layers were deposited by LPCVD, and then patterned by ASML PAS 5500 300 deep-UV lithography stepper and Inductively Coupled Plasma (ICP) Etching. The oxide cladding is LTO deposited by LPCVD and planarized by Chemical Mechanical Polishing (CMP). Finally, a 4 $\mu m$ LTO was deposited as top cladding. Fig. 6 shows the fabricated chip, with a 32$\times$32 Thin-CLOS, and test structures, including a 16-port single AWGR, test waveguides, and tri-layer couplers.
Fig. 6. Fabricated chip that has a $32\times 32$ Thin-CLOS AWGR, a $16\times 16$ single AWGR, test waveguides and test tri-layer couplers.
4. Single component characterization
Figure 7(a) shows the transmission spectra of the $16\times 16$ SiN AWGR when using input port 8 (8th input waveguide) measured by an Optical Spectrum Analyser (OSA). The measured AWGR insertion loss is 2.1 dB with spectral roll-off up to 3 dB. The measured free spectral range (FSR) is 25.7 $nm$ (3.209THz), which is off by 0.3% from design. The measured channel spacing is 1.6 $nm$ (200 GHz) as designed, with full-width-at-half-maximum (FWHM) of 1.0 $nm$. The adjacent channel crosstalk is < −18 dB, and the non-adjacent channel crosstalk is < −25 dB. Fig. 7(b) shows the measured transmission of cascaded tri-layer vertical couplers at 1550 $nm$. The results show that the tri-layer vertical coupler insertion loss is 0.272 dB and 0.308 dB for layer1-layer3 and layer3-layer5 coupling, respectively. Due to the symmetry of the tri-layer couplers, the calculated coupling efficiency between 150 $nm$ and 50 $nm$ layers is between −0.135 dB and −0.154 dB. The measured coupling loss is 0.228 dB higher for the tri-layer coupler (0.114 dB higher for neighboring layer coupling) than the simulation. It could be caused by the interlayer misalignment from photolithography, since the ASML stepper has a misalignment accuracy of 60 $nm$ using Primary Marks.
Fig. 7. Single components measurement of (a) $16\times 16$ SiN AWGR transmission spectra and (b) transmission of tri-layer vertical couplers
5. Monolithic 32$\times$32 thin-CLOS experimental demonstration
As discussed in Section 2, the 32$\times$32 Thin-CLOS AWGR has 64 optical I/O ports (64 input waveguides, 64 output waveguides, being $N$=32, $K$=2). Fig. 8(a)-(d) show the measured spectra of the monolithic Thin-CLOS when using input ports 17, 16, 49, and 48, by OSA. The four input ports are connected to the center input ports (port 8 or 9 as in a 16-port AWGR) of four different AWGRs of the Thin-CLOS. Specifically, Thin-CLOS input ports 17, 16, 49, and 48 are connected to port 9 of AWGR 1 in group 1, port 8 of AWGR 2 in group 1, port 9 of AWGR 1 in group 2, and port 8 of AWGR 2 in group 2, respectively. The measured insertion loss is 4.0 dB with 4.5 dB maximal roll-off. The adjacent channel crosstalk is < −15 dB, and the non-adjacent channel crosstalk is < −20 dB. Fig. 8(a)-(d) and (f) show the measured FSR (25.7 $nm$ or 3.209 THz), channel spacing (1.6 $nm$ or 200 GHz), and FWHM (1.0 $nm$) are the same as the results measured in the single 16-port AWGR. This is expected since the frequency response of the multi-layer waveguide connection is uniform over C-band. The single channel spectra for the best-case channel and worst-case channel of the 32$\times$32 Thin-CLOS is shown in Fig. 8(e). The worst-case channel out of all 1024 (32$\times$32, or 4$\times$16$\times$16) channels is Input63_Output2. It has > 15 dB extinction ratio, but the insertion loss is about 7 dB higher than the best-case channel, which is mainly due to the roll-off effect. This channel corresponds to input port 16 and output port 1 of the first 16$\times$16 AWGR in group 2, and therefore it suffers from the highest roll-off induced insertion loss. This channel also has the worst-case number of waveguide crossings (44 crossings) and the worst-case interlayer couplings (8 times interlayer coupling).
Fig. 8. Measured transmittance of the fabricated $32\times 32$ Thin-CLOS, when using input port (a) 17, (b) 16, (c) 49, and (d) 48. (e) Single channel spectra of the best-case channel and worst-case channel of the 32$\times$32 Thin-CLOS. (f) Zoomed-in view of (d) showing multi-channel.
Figure 9 shows the experiment setup we used to demonstrate the wavelength routing capability of the monolithic Thin-CLOS that enables any input port to communicate with any output port. The light source is a tunable laser diode (TLD). The continuous wave (CW) light from the source is amplified by a booster erbium-doped fiber amplifier (EDFA) and modulated by a Mach-Zehnder Modulator (MZM) at 25 Gb/s. The modulator is driven by a high-speed digital to analog converter (DAC) with $2^{11}-1$ PRBS signal. The modulated signal is edge coupled in and out of the Thin-CLOS chip by lensed fibers. The chip output signal is attenuated by a variable optical attenuator (VOA), then amplified by an EDFA and received by a photodetector (PD). We consider the EDFA and PD as an optically pre-amplified receiver (RX). The RX output is then transmitted to a digital communication analyzer (DCA) to capture eye diagrams, and to a real-time Bit Error Rate Tester (BERT) for BER measurement as a function of the RX input power. During the testing, the optical power at the input of the VOA was close to −21.5 dBm. By tuning the VOA, we tested the BER curves and found the minimum power required at the pre-amplified RX for error-free operation of each channel to capture eye diagrams.
Fig. 9. Experimental Setup. TLD: tunable laser diode; EDFA: erbium-doped fiber amplifier; PC: polarization controller; DAC: digital to analog converter; MZM: Mach Zehnder Modulator; VOA: variable optical attenuator; RX: receiver; PD: photodetector; DCA: Digital Communication Analyzer; BERT: Bit Error Rate Tester
We tested the port-to-port communications of 12 representative channels (12 combinations of input port and output port). The four input ports tested are 17, 16, 49, and 48 since they are connected to the center input port of four different 16$\times$16 AWGR of the Thin-CLOS LION. For each input port, the output ports 1, 9, and 16 of the corresponding 16$\times$16 AWGR are selected for testing. Since port 1 and 16 have the largest roll-off while port 9 has the smallest roll-off, the 12 combinations of input ports and output ports cover port-to-port communications through the four 16$\times$16 AWGRs, with the maximum and minimum roll-off effect (from the center input port) of each small AWGR included. Fig. 10 shows the eye diagrams of signals transmitted through the 12 representative channels of the Thin-CLOS. Fig. 11 shows the measured BER curves (shows 8 channels instead of 12 channels to make the image clearer), achieving $10^{-12}$ BER with limited power penalty compared to the back-to-back (B2B) BER curve. The B2B measurement was taken at 1528.3 $nm$ (one of the passband wavelengths of the AWGR). The measured power penalty variation of the Thin-CLOS AWGR is due to the pre-amplified RX having a sensitivity variation of 2 dB, which is caused by the wavelength-dependent gain of the EDFA. When comparing the BER curves and baseline at the same wavelength (1528.3 $nm$), the AWGR is including about 1 dB power penalty. The power penalty could be due to possible reflection at the facets, or due to the AWGR passband narrowing of the modulated signal. The reflection-induced power penalty can be avoided by applying anti-reflection coating to both facets and/or using angled facet waveguides for input and output coupling. The experiment demonstrates 25 Gb/s error-free port-to-port communication through all the channels tested on the Thin-CLOS chip. The total system capacity is 32$\times$32$\times$25 Gb/s=25.6 Tb/s.
Fig. 10. Eye diagrams of representative channels of the 32$\times$32 Thin-CLOS, with input port being 16, 17, 48, and 49.
6. Conclusion
In this paper, we experimentally demonstrated the first monolithic 32$\times$32 Thin-CLOS AWGR, a scalable AWGR-based SiPh fabric. The Thin-CLOS is designed by implementing a novel multilayer waveguide routing method integrating four 16-port SiN AWGRs on an optimized 5-layer SiN platform. Successful design, fabrication, and characterization show 4.0 dB total insertion loss, <−15 dB adjacent channel crosstalk, and <−20 dB non-adjacent channel crosstalk. System testing shows error-free port-to-port commutation at 25 Gb/s. This work shows the possibility of making large radix number SiPh AWGR by multi-layer photonic design and integration. The fabricated monolithic Thin-CLOS prototype paves the way of constructing large-scale SiPh optical interconnect systems [5,23], with limited number of wavelengths. Future works include (1) Experimentally investigating the crosstalk effect of multi-channel communication over the SiPh Thin-CLOS LION, (2) loss and crosstalk reduction of the SiPh Thin-CLOS AWGR, and (3) demonstrating scalable on-chip bandwidth-reconfigurable optical interconnect (Thin-CLOS Flex-LIONS) by monolithically integrating Thin-CLOS AWGR with Flex-LIONS [5,6].
Funding
U.S. Department of Defense; National Science Foundation (1611560).
Acknowledgments
The devices were fabricated at the Marvell Nanofabrication Laboratory (Berkeley, CA) and the Center for Nano-MicroManufacturing (Davis, CA).
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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