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Abstract
The accurate calibration of large-scale switch networks is critical for integrated photonics, in which the integrated optical true time delay chip is typical. In this work, a novel self-calibration method without extra testing ports is proposed by introducing lossless thermo-optic phase shifters instead to calibrate the network. As a demonstration, a 5-bit delay line based on silicon nitride is fabricated and calibrated. The extinction ratio of all the switches is greater than 30.9 dB at the cross and bar states. Using this method, the 5-bit optical delay line which can be tuned in a range of 118.53 ps and reach a low delay time deviation less than ±0.4 ps.
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1. Introduction
The characteristics of photonic integrated circuits (PICs) are defined by their transfer functions that depend on the phase and amplitude frequency responses. Due to the difficulties in maintaining sub-wavelength accuracy during fabrication, adaptive post-production tuning of on-chip parameters, such as the power splitting ratio of the couplers and the phase shifts, is necessary to guarantee a desired frequency response. A promising solution is the phase change materials (PCMs) due to the large nonvolatile change in the refractive index upon phase transition [1]. The PCMs-integrated PICs offer an opportunity for post-production tuning, which can be used to tune the split ratio of the directional coupler [2] and change the center wavelength of the micro-ring resonator [3]. However, as the complexity of PICs increases, some calibration process is needed to know how to compensate the fabrication errors. Therefore, large-scale PICs are challenged by their calibration due to the inevitable manufacturing variations, thus limiting their practicality.
Optical true time delay line (OTDL) is a typical large-scale switch network that is a promising solution for broadband phased array antenna applications in radar systems, due to its low beam-squint and electromagnetic interference [4]. The delay time can be tuned discretely by changing the state of switches to select the optical routes of different lengths [5]. In radar systems, long-time delay in tens of nanosecond scale is required for the large aperture antennas and arrays with a high number of elements. Due to the low propagation loss, several long-time delay OTDLs based on fiber systems have been proved [6–8] but the fiber-based OTDLs suffer from the bulky volume and low fiber length accuracy. As a result, the integrated OTDLs have attracted more research interest in the past decades due to their small footprint, high delay accuracy, stability and low cost. Although many fully integrated OTDLs have been demonstrated [9–12], there are still some challenges to overcome. First, the maximum delay time is usually limited by high propagation loss, and its range is sub-nanosecond. Second, it is different from the fiber-based OTDLs with the discrete switch components. The ON and OFF points of the switches in a fully integrated OTDLs are unclear due to the fabrication variations, which leads to a low extinction ratio (ER) and terrible signal-to-noise ratio of the delayed optical signals. In recent years, to overcome the propagation loss, ultra-low-loss silicon nitride (Si$_{3}$N$_{4}$) waveguide technology has been developed [13,14]. Some OTDLs based on Si$_{3}$N$_{4}$ platform have also been demonstrated [9,15]. However, there is still not a lossless and automatic method to calibrate the switches of the Si$_{3}$N$_{4}$ OTDLs. Some previous OTDLs are calibrated by utilizing directional coupler splitters as testing ports or utilizing variable optical attenuators (VOAs) to break optical interference. The VOA method based on p-i-n diode is accessible only on the silicon-on-insulator (SOI) and III-V platforms and some additional insertion loss may be introduced due to free-carrier absorption. Although directional coupler splitters are available for all integrated photonic platforms, the power splitters will introduce more extra insertion loss [12]. What is more, due to the large number of testing ports, packaging and automatic control are also inconvenient.
In this work, we first experimentally demonstrated a novel self-calibration method for the integrated OTDLs. A 5-bit OTDL is designed and fabricated on a 300-nm thick Si$_{3}$N$_{4}$ platform. The OTDL is composed of six switches and five delay waveguides with different path lengths. The lossless thermo-optic phase shifters (TOPSs) are introduced into the delay waveguides for calibration. Our experiment shows that all the switches of the OTDL can be well calibrated with a high ER of >30.9 dB at the cross and bar states. The calibrated OTDL can be tuned from 0 ps to 118.53 ps with a delay step of 3.82 ps and the deviation of the delay time is <$\pm 0.4$ ps. The on-chip insertion loss is less than 10.5 dB for all the delay states.
2. Device design and fabrication
To explain the calibration method, the schematic diagram of the fundamental 1-bit delay line with two switches (SW1 and SW2) is shown in Fig. 1(a). A thermo-optic phase shifter PS1 is introduced into the delay waveguide WG1. The shifter is used to precisely explore the switch’s ON and OFF points. In general, the state of SW1 and SW2 is unknown due to the fabrication variations. Here, the transfer matrix of SW2 can be defined as
where $T_{11},T_{12},T_{21},T_{22}$ are complex variables associated with the SW2’s state. When the light enters from the port In2, the electric field relationship between input and output can be expressed as
Fig. 1. (a) Schematic of the 1-bit delay line with two cascaded $2\times 2$ optical switches (SW1 and SW2) and a phase shifter (PS1). The insets are the power-phase responses, when the SW1 works at different states. (b) Schematic of the 5-bit delay line architecture. (c) Schematic of the single $2\times 2$ thermo-optic switch. (d) Schematic cross section of the TOPS with deep trench isolators (ISL).
When the SW1 is bar state, the light only passes through the WG2, as the red line shown in Fig. 1(a). The electric field amplitude in WG1 is $E_{1}=0$ and the interference between $E_{1}$ and $E_{2}$ is broken. Then the output power can be expressed as
It can be seen from Eq. (3) that the output power is independent from the phase difference $\Delta \varphi$. Of course, if the SW1 is cross state, the same conclusion can be also obtained. Therefore, we can find the ON and OFF points of SW1, when the output power does not change with the $\Delta \varphi$ that is tuned by the PS1, as shown by the inserts in Fig. 1(a). Hence, an N-bit OTDL can be fully calibrated by repeating the above process. Therefore, the automatic calibration of the integrated OTDL can be realized on general platforms, such as SiO$_{2}$, SOI, Si$_{3}$N$_{4}$, III-V and LNOI. Of great importance, it does not need the directional coupler splitter or VOA. The OTDL with easy packaging and high performance is promising.
As a demonstration, a 5-bit OTDL based on silicon nitride platform was designed and fabricated. The schematic diagram of the OTDL is presented in Fig. 1(b). The OTDL is composed of six switches (SW1-SW6) and five stage delays. As is shown in Fig. 1(c), the single thermo-optic switch is composed of two $2\times 2$ multimode interference couplers (MMIs) and a TOPS with a resistance of about 61 $\Omega$. The TOPS is isolated by deep trenches to reduce electrical power consumption and thermal crosstalk, as shown in Fig. 1(d). Every stage of the delay is composed of two waveguides with a length difference. The delay time difference in the $N^{th}$ stage is $2^{(N-1)}\Delta \tau$. The delay step is designed to be $\Delta \tau$ = 3.7 ps. The waveguide group index of $N_{g}$=1.87 is used, and the corresponding waveguide length difference is $\Delta L$ = 593.58 ${\mathrm{\mu} }$m. Hence, the designed delay time ranges from 0 ps to 114.7 ps for the 5-bit OTDL. To calibrate the delay line, five thermo-optic phase shifters (PS1-PS5) are introduced into the delay waveguides, as shown in Fig. 1(b). The phase shifters of the switches and the delay waveguides have the same design structure. The OTDL’s layout is presented in Fig. 2(a). The input and output ports are routed to the chip edge and terminated with the edge couplers with a pitch of 127 $\mathrm{\mu}$m to facilitate coupling with a fiber array.
Fig. 2. (a) Layout of the 5-bit OTDL. (b) Optical microscope image of the fabricated chip. (c) Photo of the packaged chip with fiber array coupling and wire bonding.
The OTDL chip was fabricated based on CUMEC CSiN300 technology platform. A 300-nm thick LPCVD Si$_{3}$N$_{4}$ film was deposited on a 200-mm silicon wafer with a buried oxide (BOX) layer. The deep ultraviolet lithography (DUV) technology and dry-etching process were used to pattern the Si$_{3}$N$_{4}$ film to form 1-$\mathrm{\mu}$m single mode waveguides and other waveguide devices, as shown in Fig. 1(d). Then, thermal annealing was done to reduce waveguide propagation loss. After annealing, 2-$\mathrm{\mu}$m thick silicon dioxide (SiO$_{2}$) was deposited to avoid the metal absorption of the heaters. And then, a AlCu metal layer was deposited and patterned to form the heaters and electronic wires. Finally, 1.5-$\mathrm{\mu}$m PECVD SiO$_{2}$ was deposited as an upper cladding layer. In addition, a deep dry etching process was performed to define the thermal isolation trenches, as shown in Fig. 1(d). The fabricated Si$_{3}$N$_{4}$ chip and PCB were fixed onto a metal base and a wire bonding process was used to provide electrical connection, as shown in Fig. 2(c). For the optical packaging, a standard single mode fiber array with a pitch of 127 $\mathrm{\mu}$m was used to align the edge couplers, then the UV glue was used to fix the fiber array.
3. Experimental results
3.1 Characterization of the first stage switch
As is shown in the red dashed frame in Fig. 1(b), the switch network of the OTDL except for the SW1 can be considered as a black block with 2 inputs and 2 outputs. The black block’s transfer matrix is defined as $T(W)$, where W is the initial electrical power of SW2-SW6. In order to prove the effectiveness of the calibration method, the first switch SW1 has been measured in detail. The input and output are In1 and Out1, respectively. A tunable laser with an output optical power of 10 dBm and a wavelength of 1550 nm was used as the light source. All the shifters of the switches and the delay waveguides were connected to the voltage source and all the switches were set to work at 3 V. As is shown in Fig. 3(a), PS1 has different electrical power response curves under the different voltages of SW1. For calibration, an objective function is defined as $\Delta P(W)=|P_{max}-P_{min}|$, where W is the electrical power of SW1. $P_{max}$ and $P_{min}$ are the maximum and minimum value of the output power, respectively, when the PS1’s electrical power ranges from 16.4 mW to 147.2 mW. Figure 3(b) shows the measured $\Delta P$ under the different electrical powers of SW1. It can be seen that the $\Delta P$ is strongly dependent on the SW1’s electrical power. Two local minimum values of the $\Delta P$ can be found at P1 and P4, where the corresponding electrical power of SW1 are 30.26 mW and 132.87 mW, respectively. P1 and P4 are considered as the ON or OFF point of SW1. The detailed electrical power response curves of PS1 are presented in Fig. 3(a), when the SW1’s voltage is P1(30.26 mW), P2(132.87 mW), P3(214.37 mW) and P4(310.97 mW), respectively. It can be seen that the output power almost does not change with the PS1’s electrical power under the condition of P1 or P4. Since the output power at P4 is significantly higher than that at P1, the points P4 and P1 correspond to the ON and OFF states of SW1, respectively. But it should be mentioned that since the transfer matrix of switches SW2-SW6 has to be assumed arbitrary it is uncertain whether the ON state is the cross state of SW1. At other electrical power points away from the ON and OFF points, such as P2 and P3, a larger $\Delta P$ is recorded, as is shown in Fig. 3(a).
Fig. 3. (a) Output optical power of the delay line as a function of the PS1’s electrical power, when the electrical power of SW1 is P1(30.26 mW), P2(132.87 mW), P3(214.37 mW), and P4(310.97 mW), respectively. (b) $\Delta P$ versus SW1’s electrical power, when the voltage of SW2-SW6 is 3 V. (c) $\Delta P$ versus SW1’s electrical power, when the voltage of all the switches is 0 V, 1 V, 2 V, 3 V, 4 V and 5 V, respectively. (d) Variation of $\Delta P$ with SW1’s electrical power, under different propagation directions, when the voltage of SW2-SW6 is 1.5 V.
The same initial voltage was applied to the switches SW2-SW6. The transfer matrix $T(W)$ varies with the initial voltages, but the local minimum point remains unchanged, as shown in Fig. 3(c). The local minimum points of the $\Delta P$ can be always found near 30.26 mW and 132.87 mW. Therefore, the ON and OFF points can be always found in the calibration method regardless of the state of the remaining switch network. There is some voltage drift of the calibrated ON and OFF points under the different initial voltages because of the thermal crosstalk. As shown in Fig. 2(a), the layout of the OTDL is so dense that there is thermal crosstalk between adjacent waveguides. The reciprocity of light is also characterized at the initial voltage of 1.5 V. The similar curve of $\Delta P$ with the same local minimum points is obtained whether the light is from In1 to Out1 or from Out1 to In1, as shown in Fig. 3(d).
3.2 Calibration of the delay line
After a detailed characterization of SW1, all the switches of the OTDL were calibrated. Before the calibration, the initial voltage of 3 V was applied to all the switches (SW1-SW6), and the voltage of all the thermo-optic phase shifters (PS1-PS5) was 0 V. Then, the first switch SW1 was calibrated by testing the $\Delta P$ at the different electrical power of SW1. Here, the $\Delta P$ was obtained by the electrical power sweep of PS1. The local minimum points of the $\Delta P$ were found, as shown in Fig. 4(a) (black arrow). The corresponding electrical power are the ON or OFF point of SW1. The former switch SW1 was set to work at ON or OFF point before the calibration of SW2. Then, the light was injected from only one port of SW2. The SW2 can be considered as the first stage and calibrated in the same way. Therefore, the $\Delta P$ at the different electrical power of SW2 was measured by the electrical power sweep of PS2. Similarly, the ON and OFF points of SW2 were also found at the local minimum points of $\Delta P$. The remaining switches from SW3 to SW5 were also calibrated step by step in the same way. Although there is not a corresponding PS6 for the calibration of SW6, we can tune the phase shifter of PS5 to get the $\Delta P$ and to find the ON and OFF points of SW6 due to the optical reciprocity as demonstrated in Fig. 3(d).
Fig. 4. (a) The SW1’s $\Delta P$ (upper black line) and output power (lower red line) versus the applied electrical power. (b) SW2, (c) SW3, (d) SW4, (e) SW5, (f) SW6.
The calibrated electrical tuning power was applied to the switches SW1-SW6, and the power response of switches was measured when the light was from In1 to Out1. As shown by the red curves in Fig. 4, the ON and OFF states are correctly found at the calibration points for all the switches. They almost have perfect performance as same as a single switch, where the ERs are more than 46.7 dB for six switches. Another group of ERs are also measured by testing the output power from Out2 and they are more than 30.9 dB for six switches. The detailed characterization of the calibrated switches is also listed in Table 1. The measured output power of the 32 delay states ranges from −3.69 dBm to −8.32 dBm, as shown in Fig. 6(d). To calculate the on-chip insertion loss of the delay line, the edge coupler loss was measured to be 3.91 dB/facet by testing a straight bus waveguide on the same chip. Therefore, when the input optical power is 10 dBm, the on-chip insertion loss of the 32 delay states ranges from 5.87 dB to 10.5 dB. There is still a large power fluctuation at the different delay states. Two factors lead to the nonuniformity of the output power. First, due to the propagation loss of the delay waveguides, the different delay states have a different insertion loss. Second, there is still the thermal crosstalk that changes the ON and OFF points of the switches, as shown in Fig. 3(c). The thermal crosstalk phenomenon is particularly obvious, when all the switches are set to work at high electrical power .
Table 1. Characteristics of the Switches at ON and OFF States
3.3 Delay performance
Figure 5 shows the experimental setup for the microwave response measurement of the chip. The packaged chip is placed on a cold plate that is controlled at 25$^{\circ }$C by a temperature controller (NewPort Temperature Controller Model 3700). The output optical power of the laser (ID PHOTONICS-CBWX-2C2L-FA) is 10 dBm and the wavelength is 1550 nm. The RF signal from the vector network analyzer (VNA) is modulated to the optical carrier through a commercial modulator (iXblue MXAN-LN-40). The modulator works at quadrature bias point. The modulated light is coupled to the chip from the input port In1. The modulator is driven by the RF signal from the VNA (Kesight N4373). The modulated optical signal is amplified by an Erbium Doped Fiber Amplifier (EDFA) to compensate for the insertion loss of the modulator and the chip. Then, the optical polarization is adjusted to TE through a polarization controller (PC) before coupling to the chip. A multi-channel voltage source (NI PXIe-4162) is used to tune the optical switches of the OTDL for the specific delay states. Finally, the optical signal is delayed by the switchable optical delay line and detected by a high-speed photodetector (Optilab PD-40-M). Then the signal from the photodetector is received by the VNA one-by-one for the measurement of amplitude and phase response of the beating microwave signal.
Fig. 5. The experimental setup of the microwave photonic link for the measurement of the delay line. PC: polarization controller, EDFA: Erbium Doped Fiber Amplifier, SMU: multi-channel Source Measure Unit, PD: photodetector, VNA: vector network analyzer.
Figure 6(a) shows the phase curves of the 32 delay states. The phase delay is relative to the shortest one. In the range of 1 GHz to 20 GHz, the phase increases linearly with microwave frequency, but the slope is different at different delay states. The group delay response can be calculated from the frequency derivative of the phase as $\tau = d \phi /d\omega$ [16]. Here, by linearly fitting the phase response, the slope of the fitting curve is considered as the delay time $\tau$. As is shown in Fig. 6(b), the measured relative delay time is from 0 ps to 118.53 ps. Then a delay time function is defined as $\tau (N) = \Delta \tau \times N + B$, where $\tau (N)$ is the measured delay time in state N, $\Delta \tau$ is the delay step, N is the state index and B is a time constant. A theoretical delay step of $\Delta \tau$ = 3.82 ps is obtained by linearly fitting the function of $\tau (N)$. The reason why the 3.82 ps is larger than the designed value of 3.7 ps is that the fabrication variation leads to the group index deviation. As shown in Fig. 6(c), the delay error between the measurement and theory is $\delta \tau <\pm 0.4$ ps for all the delay states.
Fig. 6. (a) The delay line’s microwave phase versus the microwave frequency, at the different delay states. (b) The delay times of 32 delay states. (c) The delay time errors of 32 delay states. (d) Output optical power at different delay states.
4. Discussion
Our work is compared with the state-of-the-art integrated OTDLs as illustrated in Table 2. Since the low index contrast platforms have a lower fabrication variation, the OTDL based on SiO$_{2}$ [9] or 60-nm Si$_{3}$N$_{4}$ [11] is directly measured without calibration and its ER is only 20 dB. The calibration method based on directional coupler splitter or VOA is used in [10,12]. Although the ER is improved to 25 dB, the insertion loss is too high due to the splitting loss or free-carrier absorption. Our OTDL is calibrated by utilizing lossless TOPS and the measured ER is >30.9 dB for both cross and bar sates.
Table 2. Performance Comparison of Various Integrated OTDLs
As described above, there are many calibration methods, but each kind of methods have advantages and disadvantages. Our calibration method can avoid tap loss, simplify optical packaging process and the requirements associated with tap monitors, but it also has some problems that should be concerned. Compared with the calibration method based on coupler splitter, the calibration based on TOPS can not distinguish the switch states between cross and bar. To confirm whether the switch is in its cross or bar state some additional measurement steps are required. For the delay line, the specific switch state can be confirmed by the measurement of the delay state with a vector network analyzer. Since each stage of calibration requires a two-dimensional tuning (e.g. PS1 and SW1), time cost is another factor that should be concerned. For example, if the voltage of PS1 and SW1 ranges from 0 V to 5 V with a step of 0.01 V, 251001 points of measurement are required. Since the PS1 is just used to determine whether SW1 is in ON or OFF state by introducing phase perturbation, a small voltage range and a large scan step are acceptable. When the PS1 ranges from 1 V to 3 V with a step of 0.1 V, 10521 points of measurement are required. It can be seen that the calibration time is only 4.2$\%$ of that before optimization. To further reduce the calibration time the voltage step of SW1 can be adjusted in real time by a gradient descent algorithm with a cost function of $\Delta P$. Then the points of measurement can be reduced to hundreds. What is more, the thermal cross-talk introduced by the heater on delay line waveguides (eg. PS1-PS5) should be considered. If the operating power of the heater is too high, the state of adjacent switches will be changed. As result, it prevents us from getting the correct calibration results. Especially in the long switch network, the high thermal cross-talk is fatal to calibration. To avoid thermal crosstalk, it is recommended to use a low heater power because a small phase perturbation in the delay waveguide is sufficient to confirm that whether the switch is in ON or OFF state. The calibration method are also effective on the thin film lithium niobate platform. Due to its high-speed electro-optic characteristics, the calibration time and thermal cross-talk can be further reduced. In addition, the operating wavelength also affects the performance of the calibration in theory. Narrow bandwidth optical splitter, such as directional coupler, shows asymmetric splitting when the operating wavelength is far from the center wavelength. The corresponding switches can only reach a low extinction ratio. As result, it will prevent us from getting the peak of $\Delta P$. Even if we find this peak point, it may not be the correct ON or OFF point. Therefore, It is recommended to do the calibration at the center wavelength.
5. Conclusion
In summary, we report an accurate self-calibration method for large-scale switch network. As a demonstration, a 5-bit OTDL based on silicon nitride has been well calibrated. All the switches of the 5-bit OTDL have an ER of >30.9 dB at cross and bar states. The calibrated switches almost have perfect performance as same as a single switch. After calibration, the OTDL can be tuned from 0 ps to 118.53 ps with a delay step of 3.82 ps, and the delay time deviation is <$\pm 0.4$ ps. The uniformity of the OTDL’s output power is disturbed by thermal crosstalk, but it can be improved by properly designing the layout. Since the calibration is based on the lossless TOPS, there are a series of advantages such as low extra loss, easy packaging, self-calibration and availability on general platforms (such as SiO$_{2}$, SOI, Si$_{3}$N$_{4}$, III-V and LNOI). This calibration method is not only suitable for delay lines, but also for other large-scale PICs. The large-scale programmable PICs with this self-calibration will be more powerful to process a variety of signals such as optical communication, neuromorphic computing, artificial intelligence and quantum computing.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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