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Abstract
Quantum well intermixing (QWI) on a III-V-on-insulator (III-V-OI) substrate is presented for active-passive integration. Shallow implantation at a high temperature, which is essential for QWI on a III-V-OI substrate, is accomplished by phosphorus molecule ion implantation. As a result, the bandgap wavelength of multi-quantum wells (MQWs) on a III-V-OI substrate is successfully tuned by approximately 80 nm, enabling the monolithic integration of electro-absorption modulators and waveguide photodetectors using a lateral p-i-n junction formed along the InP/MQW/InP rib waveguide. Owing to the III-V-OI structure and the rib waveguide structure, the parasitic capacitance per unit length can be reduced to 0.11 fF/µm, which is suitable for high-speed and low-power modulators and photodetectors. The presented QWI can extend the possibility of a III-V complementary metal-oxide-semiconductor (CMOS) photonics platform for large-scale photonic integrated circuits.
© 2022 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
Photonic integrated circuits (PICs) based on direct-gap III-V semiconductors such as InP and related materials have undergone marked development, particularly for optical fiber communications, since III-V semiconductors, various layers of which are grown epitaxially on a bulk substrate, enable the monolithic integration of laser diodes (LDs), modulators, photodetectors (PDs), and passive waveguides [1,2]. However, the low optical confinement in a III-V waveguide on a bulk substrate hinders the high integration density compared with Si photonics on a Si-on-insulator (SOI) substrate [3]. To eliminate this drawback of III-V photonics, we have proposed a III-V complementary metal-oxide-semiconductor (CMOS) photonics platform that enables a high-optical-confinement III-V waveguide using a III-V-on-insulator (III-V-OI) substrate such as a SOI substrate [4–6]. A III-V-OI substrate fabricated by wafer bonding enables the fabrication of ultrasmall passive waveguide components [7–9], modulators/switches [10–14], PDs [15–19], LDs [20–22], and electronic-photonic integration [23]. Compared to monolithic Si photonics with Ge PDs and Si optical modulators [24,25], our approach has the advantage of superior device performances and monolithic integration of LDs due to the direct bandgap of III-V semiconductors. Our approach also enables higher optical confinement than Si photonics with III-V hybrid integration [26], resulting in better device performances. Therefore, our approach provides one of the promising platforms for high-performance PICs. For active-passive integration on a III-V CMOS photonics platform, it is necessary to integrate III-V semiconductor layers with appropriate bandgap energy for each LD, PD, modulator, and passive waveguide on a III-V-OI substrate. Etching and regrowth on a III-V-OI substrate allow flexible active-passive integration but requires a complex fabrication procedure [27]. The twin-guide structure is another simple approach for active-passive integration with a moderate optical confinement [28]. In this paper, we present a third approach to achieving the active-passive integration using quantum well intermixing (QWI), which simultaneously endows a simple process and high optical confinement. By O2 plasma surface activation and bonding in a vacuum with a low ramp rate in annealing, we develop a III-V-OI substrate, which can be processed at the high temperature required for QWI. Moreover, we introduce P2+ implantation for QWI on a III-V-OI substrate that ensures shallow ion implantation with practical implantation energy. As a result, PDs, electro-absorption (EA) modulators, and passive waveguides are monolithically integrated on the same III-V-OI substrate, as shown in Fig. 1.
2. Fabrication of III-V-OI substrate
To promote the interdiffusion of phosphorus vacancies for QWI, high-temperature annealing above 600°C is necessary [29]. However, void generation at the bonded interface of a III-V-OI substrate during such high-temperature annealing is a problem [30–32]. We have deposited an Al2O3 layer on III-V and SiO2/Si substrates by atomic layer deposition (ALD) before wafer bonding to achieve a hydrophilic surface for bonding and surface passivation for a III-V layer [10]. However, an ALD Al2O3 layer contains surface organic contaminants that cause void generation during annealing after wafer bonding [33]. We introduce O2 plasma surface activation [34] without the ALD Al2O3 bonding interface to suppress void generation during annealing for QWI. O2 plasma irradiation is expected to remove organic contaminants. Excess water molecules on the wafer surfaces before bonding may also cause void generation. To examine the impact of excess water molecules on void generation, atmospheric and vacuum environments in wafer bonding were compared. During annealing, the generation of water and hydrogen [35,36], which is inevitable in hydrophilic bonding, can also cause void generation. Since it is known that the ramp rate of heating affects void generation [30,37], we examined high and low ramp rates of bonded wafer heating.
Figure 2(a) shows the fabrication procedure for a III-V-OI substrate with wafer bonding. First, an InP epitaxial wafer containing multi-quantum wells (MQWs) with 200-nm-thick upper and 25-nm-thick lower InP cladding layers was prepared by metal-organic chemical vapor deposition. The MQW structure consisted of 7 × 6.5-nm-thick In0.735Ga0.265As0.835P0.165 wells with 8-nm-thick In0.735Ga0.265As0.513P0.487 barriers and 25-nm-thick In0.735Ga0.265As0.513P0.487 separate-confinement heterostructure (SCH) layers. InP/In0.53Ga0.47As multiple etch-stop layers were inserted between the device layer and the InP substrate. A 2-µm-thick SiO2 buried oxide (BOX) layer was formed on a Si substrate by wet oxidation. Then, O2 plasma surface activation for 15 s was performed for the two wafers using a plasma activation system (EVG810LT). After surface cleaning using a wafer cleaning system (EVG301) that can remove particles on the wafer by spraying ultrasonic water onto the substrate surface, the two wafers were brought into contact in atmosphere manually or in vacuum using a wafer bonder (EVG501) by applying a pressure of 24.6 kN/m2 for 3 min. Bonding annealing at 200–300°C was carried out for 2 h in atmosphere. Note that a bonding temperature between 200 and 300°C does not affect the void density in the following discussion. During heating, we examined a high ramp rate (> 30°C/min) and a low ramp rate (2°C/min). Finally, the InP substrate and etch-stop layers were selectively removed using phosphoric acid solution. Figure 2(b) shows a photograph of the 2-inch III-V-OI substrate with uniform bonding. A cross-sectional transmission electron microscopy (TEM) image of the III-V-OI substrate is shown in Fig. 2(c). It was found that the InP/MQW/InP device layers were bonded onto the SiO2 BOX layer.
Fig. 2. (a) Fabrication procedure for III-V-OI substrate with wafer bonding. (b) Photograph of 2-inch III-V-OI substrate and (c) cross-sectional TEM image of III-V-OI substrate.
Figure 3 shows the void density of the III-V-OI substrate after bonding annealing at 200–300°C and rapid thermal annealing (RTA) in nitrogen atmosphere at 600°C for 1 min. When bonding was performed in atmosphere with fast ramp annealing, the void density exceeded 105 cm-3, which is unsuitable for device integration. When the bonding environment was changed from atmosphere to vacuum, the void density was reduced by more than one order of magnitude. Slow ramp annealing also slightly reduced the void density. As a result, the void density of approximately 2 × 103 cm-2, which is close to the defect density of the original InP wafer, was successfully obtained by vacuum bonding and slow ramp annealing, as shown in the plan-view photograph of the III-V-OI wafer after RTA in Fig. 3. Note that the void density did not increase even after RTA in the case of vacuum bonding. The void density in case of the bonding in atmosphere with slow ramp annealing was approximately 2 × 104 cm-2. Therefore, the vacuum environment is more effective than slow ramp annealing for reducing the void density.
Fig. 3. Void density of III-V-OI substrate after bonding annealing at 200–300°C for 2 h and annealing at 600°C for 1 min. The inset shows the plan-view photograph of the III-V-OI substrate after RTA.
3. Quantum well intermixing on III-V-OI substrate
Since the thermal expansion coefficient between Si and InP is significant, the thickness of the III-V device layer in the III-V-OI substrate should be less than approximately 400 nm to avoid thermal damage during annealing [38]. Therefore, a thick InP upper cladding, typically used for QWI on an InP bulk substrate, cannot be used for the III-V-OI substrate. Previously, we found that the implantation energy of P+ should be less than 5 keV for a III-V-OI substrate to ensure the generation of phosphorus vacancies within a thin InP upper cladding [39]. However, high-temperature ion implantation, which is required for extending the bandgap tuning range in QWI [40], was not applicable with such low implantation energy because of the limitation of the available facilities that we outsourced. To overcome this constraint, we introduced phosphorus molecular ion (P2+) implantation [41] for QWI on a III-V-OI substrate, by which shallow implantation is achievable even at an implantation energy of 10 keV because of the mass of P2+ being larger than that of P+. As a result, we can perform high-temperature implantation for QWI on a III-V-OI substrate.
Figure 4(a) shows the sample structures used for QWI experiments. In addition to the III-V-OI substrate in Fig. 2, the original InP epitaxial wafer was used as a bulk sample. After capping the surfaces with a 3-nm-thick ALD Al2O3 passivation layer, P2+ implantation was carried out at 200°C. The implantation energy and dose were 10 keV and 5 × 1014 cm-2, respectively. Figure 4(b) shows the photoluminescence (PL) spectra of the bulk sample obtained before and after annealing at 650°C for 12 min. The peak wavelength of the PL spectrum before annealing was approximately 1545 nm, close to that of the original MQW. In contrast, a blue shift in peak wavelength was clearly observed after annealing owing to QWI, revealing the effectiveness of P2+ implantation for QWI. The full width at half maximum of the PL peak tends to decrease during QWI slightly, attributable to the improvement in the crystal damage caused by P2+ implantation. Figure 4(c) shows the peak wavelength shift in the PL spectra of the bulk and III-V-OI samples as a function of the square root of the annealing time. When the diffusion coefficient is constant, the diffusion length is proportional to the square root of the annealing time. We found that the peak shift of the III-V-OI sample was smaller than that of the bulk sample; this was attributed to the promoted recombination between phosphorus vacancies and interstitials in the III-V-OI structure [39]. The peak shift of the III-V-OI sample was saturated to be approximately 80 nm but was sufficient for the monolithic integration of EA modulators and PDs. Note that there is room for improvement in the peak shift through the optimization of the III-V layers such as the upper InP thickness.
Fig. 4. Quantum well intermixing on III-V-OI and InP bulk substrates by P2+ implantation at 200°C. The implantation energy and dose were 10 keV and 5 × 1014 cm-2, respectively. (a) Layer structures of bulk and III-V-OI substrates. (b) PL spectra of bulk sample obtained before and after annealing at 650°C for 12 min. (c) PL peak shift of bulk and III-V-OI substrates as a function of square root of annealing time. The annealing temperature was 650°C.
4. Device fabrication
Figure 5(a) shows the fabrication procedure for passive waveguides, EA modulators, and PDs on a III-V-OI substrate with selective QWI. After fabricating a III-V-OI substrate as depicted in Fig. 2(a), a 10-nm-thick ALD Al2O3 layer was deposited on the substrate. A 60-nm-thick SiO2 mask was deposited by plasma-enhanced chemical vapor deposition (PECVD) and patterned for selective QWI by electron-beam (EB) lithography using OEBR CAN 2cp EB resist and inductively coupled plasma reactive ion etching (ICP-RIE) using C4F8/Ar plasma. The Al2O3 capping layer acted as an etch stop layer. After SiO2 etching, the Al2O3 capping layer was removed by NMD-3 (Tokyo Ohka Kogyo) and a 3-nm-thick ALD Al2O3 was deposited once again as a capping layer for P2+ implantation. Note that we redeposited Al2O3 for the accurate control of the Al2O3 thickness for QWI. As depicted in Fig. 4, selective QWI with 24 min annealing at 650°C was carried out by P2+ implantation (10 keV, 5 × 1014 cm-2) at 200°C. The Al2O3 and SiO2 layers were removed by BHF, and InP/MQW/InP rib waveguides were formed by EB lithography and RIE etching (CH4/H2/Ar =30/70/30 sccm, 10 Pa,100 W) with a SiO2 mask. The cross-sectional TEM image of the waveguide is shown in Fig. 5(b). The waveguide width was designed to be 600 nm. Next, Si ion implantation (45 keV, 1 × 1014 cm-2) with a 300-nm-thick SiO2 mask was performed, followed by annealing at 650°C for 1 min to form n+-regions. Then, a Zn-doped spin-on-glass (SOG) layer was spin-coated with a 10-nm-thick Al2O3 mask. After curing the SOG layer at 300°C for 120 min, Zn diffusion was carried out at 500°C for 1 min to form p+-regions. The SOG layer was removed by BHF, and each device was electrically isolated by RIE etching. The device was passivated with 10-nm-thick ALD Al2O3 and 780-nm-thick PECVD SiO2 after surface cleaning followed by surface passivation with (NH4)S solution. Finally, Ti(50 nm)/Au(200 nm) electrodes were formed by thermal evaporation and lift-off. Figure 5(c) shows the cross-sectional TEM image of the bonding interface. We observed a thin InP oxide layer formed by O2 plasma surface activation at the interface.
Fig. 5. (a) Fabrication procedure for passive waveguides, EA modulators, and PDs on a III-V-OI substrate with selective QWI. (b) Cross-sectional TEM image of InP/MQW/InP rib waveguide on a III-V-OI substrate. (c) Cross-sectional TEM image of the bonding interface.
5. Electro-absorption modulator
We first evaluated the EA modulator on the III-V-OI substrate. The plan-view schematic and photograph of the EA modulator are shown in Fig. 6. The EA modulator and passive waveguide were fabricated using the implanted region where the bandgap wavelength was shifted from 1550 nm to 1470 nm by QWI. The length of the modulator was 250 µm. The input light was coupled from a cleaved single-mode optical fiber (SMF) to a focusing grating coupler after the polarization of the input signal was adjusted to a transverse-electric (TE) mode, and the output was coupled back from another grating coupler to a SMF. The output power was measured with an InGaAs optical power meter. A tunable laser (Santec TLS-510) was used as a light source.
Fig. 6. (a) Plan-view schematic and photograph of EA modulator on III-V-OI substrate. (b) Transmission spectra of EA modulator with various biases.
Figure 6(b) shows the transmission spectra of the EA modulator with various bias voltages applied to the lateral p-i-n junction. The optical intensity at wavelengths from 1540 nm to 1560 nm was modulated by the applied electric field. Since an in-plane electric field was applied to the MQW, the absorption in the MQW was modulated through the Franz–Keldysh effect but not through the quantum-confined Stark effect (QCSE) [42–44]. The extinction ratio of 9 dB was obtained at a 1540 nm wavelength with -5 V bias. Note that the propagation loss of the intermixed waveguide with λpeak of 1470 nm at a 1550 nm wavelength evaluated by the cut-back method was 13 dB/mm, which can be reduced by further extending the bandgap tuning range.
The capacitance of the lateral p-i-n junction formed on the III-V-OI substrate was evaluated with various device lengths using a precision LCR meter (Agilent E4980A) at 1 MHz, and the results at a bias voltage of -3 V are shown in Fig. 7(a). The gap between the waveguide edge and the heavily-doped junction was designed to be 600 nm. Hence, the total width of the intrinsic layer of the p-i-n junction was 1.6 µm. When the waveguide mesa was not formed by etching, the device capacitance per unit length was 0.44 fF/µm. The device capacitance was reduced by forming the waveguide mesa because the effective junction area decreased. As a result, the device capacitance per unit length was reduced to 0.11 fF/µm, more than 10 times smaller than the typical capacitance of a conventional EA modulator on a bulk substrate [45]. From the measured capacitance, we estimated the 3 dB cut-off frequency of the EA modulator by assuming a 50 Ω resistor, as shown in Fig. 7(b). It was found that the III-V-OI structure and rib waveguide structure enable a modulation frequency of more than 200 GHz when the device length is 100 µm. Note that the measured series resistance of the device was approximately 24 Ω.
Fig. 7. (a) Capacitance of lateral p-i-n junction formed on III-V-OI substrate as a function of device length. (b) Estimated 3 dB cut-off frequency of modulation assuming 50 Ω resistor.
The dynamic modulation characteristics of the EA modulator were evaluated using the measurement setup shown in Fig. 8(a). A 12.5 Gbps non-return-to-zero (NRZ) electrical signal generated by a pulse pattern generator was injected into the EA modulator with a bias voltage of -2.25 V. The peak-to-peak voltage (Vpp) was approximately 4.5 V after the RF amplifier. Continuous-wave (CW) light at a wavelength of 1540 nm was injected into the device. The output from the device was coupled to an SMF fiber through the grating coupler, then amplified by an erbium-doped fiber amplifier (EDFA). Finally, the amplified optical signal was received by a photodetector and measured by a sampling oscilloscope. As shown in Fig. 8(b), we obtained a clear eye opening at 12.5 Gbps. Currently, the bandwidth measurement is limited by our equipment. However, the EA modulator is expected to operate at a higher frequency, as illustrated in Fig. 7(b).
Fig. 8. (a) Measurement setup of dynamic modulation characteristics for EA modulator. (b) Eye pattern of EA modulator with 12.5 Gbps NRZ signal.
6. Photodetector
We also evaluated the waveguide PD on the III-V-OI substrate. Figure 9(a) shows the plan-view schematic and photograph of the PD fabricated using the region without QWI where the bandgap was 1550 nm. The region with QWI was used for fabricating the passive waveguides and grating couplers. The length of the PD was designed to be 30 µm. Note that the grating coupler for the output was also prepared to measure the transmission of the PD, as discussed later. We used a measurement setup similar to that for the EA modulators. Figure 9(b) shows the measurement results for dark current and photocurrent. The photocurrent was measured when 0 dBm CW light at a wavelength of 1550 nm was injected into the grating coupler. The dark current gradually increased with bias voltage but was less than approximately 2 µA at -1 V, which is sufficiently low for detecting a high-speed optical signal. We found that the dark current increased after dry etching. Hence, the dark current can be reduced further by improving dry etching and surface treatment after etching. Owing to the built-in potential in the lateral p-i-n junction, photocurrent was obtained even without bias and exhibited almost no bias voltage dependence.
Fig. 9. (a) Plan-view schematic and photograph of PD on III-V-OI substrate. (b) Photocurrent and dark current measurements.
To further investigate the PD characteristics, we evaluated the transmission of the PD with various PD lengths at a wavelength of 1550 nm, as shown in Fig. 10(a). From the slope of the transmitted optical power with respect to the PD length, the absorption of the PD per unit length was determined to be -0.9 dB/µm. The solid black line in Fig. 10(b) shows the responsivity estimated from the PD absorption in Fig. 10(a) when the internal quantum efficiency (QE) was assumed to be 100%. The red points show the measured responsivities at various lengths when the bias voltage was -1 V. We achieved the responsivity of approximately 0.7 A/W when the PD length was 30 µm, taking into account the coupling loss of the grating coupler (10 dB) and the propagation loss of the passive waveguide (1.5 dB). The measured responsivity was lower than the expected one, suggesting a QE lower than 100%, which is attributable to the degradation of the carrier extraction efficiency of the lateral p-i-n junction and carrier recombination by crystal defects. There is plenty of room for improving the responsivity by optimizing the process for p-i-n junction formation.
Fig. 10. (a) Transmitted optical power of PD with various device lengths at a wavelength of 1.55 µm. (b) Estimated and measured responsivities of PD. The measurement was performed at -1 V.
The dynamic characteristics of the PD were evaluated using the measurement setup shown in Fig. 11(a), which is similar to that for the EA modulator in Fig. 8(a). We achieved a clear eye pattern with a 12.5 Gbps NRZ signal and error-free operation, as shown in Fig. 11(b). Since the gaps between the waveguide edge and the n- and p-doped regions were 300 nm and 100 nm, respectively, the total width of the intrinsic layer of the p-i-n junction was 1.0 µm. Hence, the operation speed of the PD might be limited by the carrier transit time, which can be improved by reducing the width of the intrinsic layer.
Fig. 11. (a) Measurement setup of dynamic modulation characteristics for PD. (b) Eye pattern of PD with 12.5 Gbps NRZ signal.
7. Conclusion
We applied QWI to a III-V-OI photonic platform for active-passive integration. We found that phosphorous molecule ions instead of phosphorus ions enabled shallow implantation at a high temperature with practical implantation energy, ensuring phosphorus vacancy generation in a thin top InP cladding of a III-V-OI substrate. As a result, the bandgap energy of the MQW on a III-V-OI substrate was successfully blue-shifted, enabling the monolithic integration of EA modulators and PDs. With a simple integration process, the presented QWI with phosphorous molecule ion implantation paves the way to the fabrication of large-scale PICs on the III-V CMOS photonics platform.
Funding
New Energy and Industrial Technology Development Organization (JPNP13004); Japan Science and Technology Agency (JPMJMI20A1).
Acknowledgments
Part of this work was conducted in the Takeda Sentanchi super clean room, The University of Tokyo, supported by the “Nanotechnology Platform Program” of the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan, Grant Number JPMXP09F21UT0042.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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