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Abstract
Cryogenic environments make superconducting computing possible by reducing thermal noise, electrical resistance and heat dissipation. Heat generated by the electronics and thermal conductivity of electrical transmission lines to the outside world constitute two main sources of thermal load in such systems. As a result, higher data rates require additional transmission lines which come at an increasingly higher cooling power cost. Hybrid or monolithic integration of silicon photonics with the electronics can be the key to higher data rates and lower power costs in these systems. We present a 4-channel wavelength division multiplexing photonic integrated circuit (PIC) built from modulators in the AIM Photonics process development kit (PDK) that operate at 25 Gbps at room temperature and 10 Gbps at 40 K. We further demonstrate 2-channel operation for 20 Gbps aggregate data rate at 40 K using two different modulators/wavelengths, with the potential for higher aggregate bit rates by utilizing additional channels.
© 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
There has been an extensive body of research dedicated to developing compact, low-power consumption electro-optic (EO) modulators on the silicon-on-insulator (SOI) platform [1–10], with many having been fabricated using complementary metal-oxide-semiconductor (CMOS) manufacturing processes. As such devices find use in datacenter and telecommunication applications, they must withstand continuously high temperatures. However, some applications require devices to withstand very low temperatures such as in cryogenically cooled environments. Traditional superconducting materials require less than 10 K to become superconductors. However, new research has uncovered superconductors that operate at temperatures as high as 250 K [11–14], thus significantly expanding possible temperature range of cryogenic superconducting systems and making them increasingly more feasible due to their reduced cooling power requirement. Several superconducting integrated circuits have been demonstrated [15,16], including some using high temperature superconductors [17–19]. In superconducting computing, including superconducting quantum computing, cryogenic cooling enables significantly lower power consumption of electronics and opens the door for significantly higher data rates [20–22]. The limited cooling power available in such low-temperature cryogenic systems sets strict constraints on the power budget and necessitates the use of low power consumption technologies. These applications are currently heavily dominated by electronics but with the increase in data rates, the heat burden that electronics imposes on these cryogenically cooled systems becomes nonnegligible.
Silicon photonics offers low-power consumption at very high data rates and it can provide greater benefits where electronics falls short. For instance, data transmission from the cold space to the outside environment is a significant source of energy loss due to the high heat conduction of conventional electrical transmission lines. Increasing the data rate necessitates the use of additional transmission lines which increases the energy consumption due to the increased thermal load on the cooling system. Replacing the electrical lines with a single optical fiber can significantly alleviate this problem thanks to its small thermal conductivity and cross section, leading to lower thermal conductance between the cold and warm environments. Hence, an EO data conversion in the cryogenic environment is needed for which silicon photonics would be a great candidate due to its compact footprint, while also enabling significantly higher transmission data rates.
The field of silicon photonics has matured significantly over the last two decades and is now at the heart of many high-speed transceivers. Great effort has been dedicated to the development of a comprehensive set of robust CMOS-compatible silicon photonics devices. Foundries now offer photonic PDKs to circuit designers, eliminating the resource-intensive process of designing all of the individual circuit components oneself. This enables designers to focus on PIC design instead of component design, reducing the time required to create a system, and improving the chances of developing a successful prototype using a single foundry run. The photonic devices in such PDKs perform well at room temperature and elevated temperatures common in telecommunications, however their suitability for cryogenic applications is unknown.
There are also barriers to silicon photonics entering this space. Electronics offers great flexibility due to the well-established and sophisticated packaging solutions that can withstand a wide temperature range. Photonics packaging remains a great focus of research and still has a long road ahead. In addition, photonic devices such as silicon modulators that operate based on the free-carrier effect may not necessarily be able to operate at low temperatures as well as they do at room temperature given that thermally excited free carriers become scarce at cryogenic temperatures, a phenomenon known as carrier freeze-out [23]. That, in turn, might necessitate a higher turn-on voltage to address carrier freeze-out and ensure an adequate modulation depth which would result in increased power consumption. Alternatively, raising the doping level of the device’s p-n junction has been shown to address the situation by creating more free carriers at the expense of higher optical transmission loss [24] thus degrading the link quality. Gehl et al. show that the turn-on voltage of a silicon micro-disk modulator designed for room temperature more than doubles when cooled below 60 K and can be compensated for by increasing the doping levels. In either case, these trade-offs would reduce the benefit offered by the proposed photonic solution and are of practical concern.
We present the design and operation of a 4-channel wavelength-division multiplexed (WDM) photonic circuit fabricated at AIM Photonics foundry using PDK components such as the silicon micro-disk modulators offered by the foundry. We confirm 25-Gbps and 10-Gbps modulation per channel at room-temperature and 40 K, respectively, and demonstrate 2-channel operation at 40 K.
2. WDM circuit design
The WDM circuit consists of a cascade of 4 micro-disk modulators with room temperature resonance wavelengths of 1550 nm, 1556.4 nm, 1562.8 nm and 1569.2 nm on a shared silicon waveguide bus line. The modulators have a nominal free spectral range (FSR) of 25.6 nm which sets the channels equally spaced by 6.4 nm. Figure 1(a) shows a closeup view of the circuit where modulator anode and cathode pads are marked with P and N, respectively. The pads marked by H are connected to each modulator’s integrated heater which could be used to shift the resonance to the laser wavelength, but are not utilized in our measurements as tunable lasers are used to optimize performance. As shown in the schematic diagram of Fig. 1(b), the bus line contains tap couplers and integrated photodiodes for monitoring and wavelength tuning purposes that were not used for the present system demonstration. The circuit is coupled with fiber edge couplers on either side to transfer the optical signal on and off the chip. The modulator pads are placed immediately adjacent to each modulator in order to maintain the lumped element electrical behavior in subsequent measurements.
Fig. 1. (a) Microscope image of the 4-channel WDM circuit; relevant pads are highlighted with P and N denoting modulator anode and cathode pads, respectively, and H denoting integrated heater pads. The other pads are dummy pads. (b) Schematic diagram of the 4-channel WDM circuit as implemented in the system. TLS: Tunable Light Source, MUX: Multiplexer, PIC: Photonics Integrated Circuit, DEMUX: Demultiplexer, PD: Photodiode.
3. Circuit simulation
The WDM link of Fig. 1(b) is modeled using Lumerical Interconnect according to the schematic layout depicted in Fig. 2. The simulation uses the model of the modulators imported from the AIM Photonics PDK. 4 lasers with 100-kHz linewidths launch a continuous-wave (CW) optical signal into a combiner that operates as an ideal multiplexer. The wavelength of each laser is set 0.08 nm higher than the corresponding modulator’s resonance wavelength to maximize the extinction ratio and minimize any transmission penalty. Each modulator is also biased with −1 VDC. A pseudo-random bit sequence (PRBS) generator in conjunction with a pulse generator create a sequence of 231-1 bits that drive each modulator. The modulated optical signal is then separated by a cascade of 4 ideal micro-ring resonators that act as an optical add-drop demultiplexer. The optical signal of each channel is fed to a photodiode. The electrical signal from the photodiode is passed through a low-pass Bessel filter before entering the bit error rate tester (BERT) to measure the bit error rate (BER) and obtain an eye diagram. The low-pass filter has a cutoff frequency that is 1.5 times the highest frequency component of the signal to provide channel isolation without degrading the signal power or shape. Figure 3 shows the eye diagrams obtained from the WDM circuit simulation. As the eye diagrams demonstrate, signal-to-noise ratio (SNR) as well as BER deteriorate as data rate is increased from 25 Gbps to 45 Gbps in 10-Gbps increments.
Fig. 2. Schematic diagram of the 4-channel WDM circuit as modeled using Lumerical Interconnect. 4 CW lasers send optical signals with 0.08 nm higher wavelength than the modulator resonances into a combiner. The modulators, imported from AIM PDK, are each driven by a pulse generator with a non-return-to-zero (NRZ) PRBS. A cascade of micro-ring resonators separates the optical channels and feed each to a photodiode that is then filtered and passed to a bit error rate tester. Some of the components such as heaters’ DC suppliers have been removed from the diagram for better clarity.
Fig. 3. Simulated eye diagrams for a single channel while all 4 channels are active. Eye diagrams correspond to system running at (a) 25 Gbps, (b) 35 Gbps, and (c) 45 Gbps. The maximum BER for any channel is <1e-20, 1.2e-5 and 3.1e-3 at 25 Gbps, 35 Gbps and 45 Gbps, respectively. 4 CW lasers with 100-kHz linewidth are used and the modulators are biased with −1 VDC voltage.
4. Individual modulator test results
4.1. Optical tests
Due to the resonant nature of the modulators, slight fabrication imperfections, temperature variations, etc. cause their resonance wavelengths to deviate from the nominal values. As a first step, a broadband light source in conjunction with an optical spectrum analyzer (OSA) is used to identify the location of the resonances, according to the diagram of Fig. 4. Broadband linearly-polarized light is launched into a polarization-maintaining optical fiber using the amplified spontaneous emission of an erbium-doped fiber amplifier (EDFA) coupled with a fiber polarizer. The optical fiber is mounted on a fiber rotator that ensures the optical mode polarization is in-plane with the PIC, thus coupling to the TE-polarized mode of the PIC’s edge coupler since the on-chip circuit components are designed for TE polarization. A standard SMF-28 optical fiber couples light out of the PIC and into an OSA. Figure 5 shows the optical spectrum of the modulator bank at room temperature as well as 40 K with the room-temperature resonances having been blue-shifted by 8.54 nm on average relative to the nominal values predicted by AIM Photonics’ PDK due to variations in fabrication. Additionally, a comparison between Fig. 5(a) and 5(b) demonstrates a 13.5-nm blue-shift in the resonance of the modulators as the chip is cooled from room temperature to 40 K. Using the same test setup, various DC voltages are applied to the modulator with nominally 1550nm resonance wavelength and the resulting shift in the spectrum is plotted in Fig. 6, for both temperatures. Figures 5 and 6 show no significant difference in the spectral shape, including the FSR, and DC electrical behavior of the modulators between room temperature and 40 K. According to Fig. 6, the Q-factor of modulators λ0 and λ3 are 4.4e4 and 4.8e4, respectively, when the DC bias is turned off. However, the actual Q-factors may be higher because the limited resolution bandwidth of the OSAs prevents us from fully capturing the depth of the resonances.
Fig. 4. Schematic diagram of modulator spectral analysis, spectra versus DC bias, and I-V curve measurements. Optical and electrical connections are drawn in green and black, respectively. An EDFA is used as a broadband light source. OSA: Optical Spectrum Analyzer.
Fig. 5. Spectrum of the 4-channel WDM circuit at (a) room temperature and (b) 40 K obtained by an OSA with resolution bandwidth of 0.02 nm. While the modulators’ nominal FSR is 25.6 nm, the FSR of the fabricated modulators is between 24.2 nm and 24.8 nm due to fabrication imperfections, principally thickness variations. The resonances seem to be sharper at low temperatures which is likely due to chip-to-chip fabrication variations and difference between room-temperature and 40 K measurement setups.
Fig. 6. Spectra of a modulator for various DC voltages applied at (a) room-temperature and (b) 40 K. The resonances seem to be sharper at low temperatures which is likely due to chip-to-chip fabrication variations and difference between room-temperature and 40 K measurement setups.
4.2. Electro-optic tests
Using the measurement setup of Fig. 4, the I-V curve of the modulator diode is obtained at room temperature and 40 K, as shown in Fig. 7, demonstrating the carrier freeze-out effect through a flatter I/V curve requiring a higher forward bias turn-on voltage.
Fig. 7. I-V curve of modulator with resonance λ0=1550 nm at room temperature (blue) and 40 K (red). The slope of the curve decreases with temperature requiring higher turn-on voltages and demonstrating evidence of carrier freeze-out.
To derive the electrical frequency response of the modulator, a Keysight N4373D Lightwave Component Analyzer (LCA) is used according to the layout depicted in Fig. 8. The LCA is calibrated using a Keysight N4694A Electronic Calibration Module. Using an impedance standard substrate, the path from the LCA to the tip of the high-speed RF probe is also de-embedded. Therefore, the calibration reference plane is at the point of contact between the tip of the probe and the modulator pads on the PIC. The S11 (reflectivity) and S21 (electro-optic response) of modulator λ0=1550 nm are measured as shown in Figs. 9 and 10, without any applied DC bias voltage. The reflectivity of the modulator indicates a pad capacitance of 100 fF. As a result, the modulator’s EO response indicates only a 10-GHz bandwidth. However, using a negative DC bias can increase the modulator’s electrical bandwidth, thereby permitting error-free operation at higher bit rates.
Fig. 8. Measurement setup for S11 and S21 response. Optical and electrical connections are drawn in green and black, respectively. TLS: tunable laser source, LCA: Lightwave Component Analyzer.
Fig. 9. Reflectivity (S11) of the modulator with nominal resonance of λ0 = 1550 nm. (a) Smith chart representation and (b) magnitude and phase of S11 as a function of frequency.
Fig. 10. Electro-optical response (S21) of the modulator with nominal resonance of λ0=1550 nm at room temperature and no DC bias.
To measure the BER, the LCA shown in Fig. 8 is replaced with an EDFA coupled with an optical filter and a Discovery Semiconductor DSC10H-39-FC/UPC-V-2 high-speed photodetector which is connected to the Error Detector (ED) of an Anritsu MP1800A Signal Quality Analyzer (SQA). The SQA’s pulse pattern generator drives the modulator with a PRBS that is 231-1-bits long. The laser is set to −5 dBm, which given the −13.5-dB insertion loss of the chip including losses of two fiber edge couplings, according to Fig. 5, gives us about −11.75 dBm power in the waveguide. In order to reduce the noise generated by the EDFA, a 0.7-nm wide optical band-pass filter is used before the amplified optical signal reaches the photodetector. The photodetector converts the optical signal to an electrical one which then goes to the SQA’s ED for error rate measurement and an Agilent Infiniium DCA 86100A sampling oscilloscope to plot the eye diagram. With a measurement floor of 10−12, error-free operation was demonstrated at room temperature using a 1.2-Vpp drive voltage and −1-V DC bias at room temperature for 20-Gbps and 25-Gbps speeds as shown in Fig. 11. The drive voltages reported throughout here are voltages at the modulator.
Fig. 11. Eye diagrams showing (a) 20-Gbps and (b) 25-Gbps error-free operation at room temperature. A band-pass optical filter with 0.7-nm bandwidth centered at the modulator resonance wavelength is used to reduce EDFA noise. A 1.2-Vpp signal is used to drive the modulator with −1-V DC bias. The eye diagrams are obtained using an Agilent Infiniium DCA 86100A sampling oscilloscope.
Next the chip is wire bonded to a printed circuit board made of Rogers 3010 material with 50-ohm traces connected to an SMP connector. The packaged PIC is placed into a Montana Instruments cryostat. RF cables connect the package with the cryostat’s RF feedthroughs. Optical fibers mounted on a pair of alignment stages couple the optical signal into and out of the PIC. The waveform measurements are repeated at 15 Gbps at two different temperatures, 110 K and 70 K, similar to the room temperature tests. A 27-1-bit long PRBS pulse pattern with 1.5 Vpp and no DC bias is generated to drive the modulator and obtain the eye diagrams shown in Fig. 12. To find the optimum BER the de-emphasis is manually adjusted and the BER is measured as reported in Table 1. There is a slight difference in measured signal-to-noise ratio, but the error rates are very similar at these two temperatures. As the cryostat temperature is further reduced to 40 K, the eye diagram closes further and the SNR degrades. At 15 Gbps data rate, the error rate significantly increases to 2.0e-7. Reducing the data rate to 10 Gbps allows for improved error rates, even when running with a lower RF signal amplitude. Figure 13 shows the eye diagram of the modulator running at 10 Gbps at 40 K using a 1.25-Vpp drive voltage without a DC bias voltage. The open waveforms confirm that low error rates should be possible. Optimum RF signal amplitudes and laser wavelengths in each case were obtained by systematically varying these parameters using an automated setup while measuring the BER. This process produces a map of BER vs. signal amplitude and laser wavelength. An example of this search map for 40 K with 10-Gbps data rate is shown in Fig. 13. This map further illustrates that the optimum wavelength varies with signal amplitude due to self-heating of the modulator and that error-free operation at such a low temperature is only achievable at signal amplitudes of 1 V or greater.
Fig. 12. Eye diagrams showing 15 Gbps at (a) 110 K and (b) 77 K, giving an SNR of 5.4 and 4.5, respectively. A band-pass optical filter with 0.8-nm bandwidth is centered at the modulator resonance wavelength. A 1.5-Vpp signal is used to drive the modulator with 0 V DC bias. The eye diagrams are obtained using a sampling oscilloscope with a de-emphasis filter.
Fig. 13. (a) Eye diagram showing 10 Gbps operation at 40 K, and (b) map of BER vs. signal amplitude and laser wavelength used to find optimum conditions for error-free operation at 40 K with 10-Gbps data rate. Voltage on the y-axis is the signal amplitude which is half the Vpp. Error-free operation is indicated by crossed circles near 1000 mV and 1534.04 nm. Skewed outlined region of the map shows lowest BER achieved. It also illustrates shifting modulator resonance due to self-heating.
Table 1. Minimum BERs achieved at three cryogenic temperatures.
5. WDM circuit demonstration
Finally, WDM operation is demonstrated at 40 K. Due to measurement setup limitations including electrical interfacing of all 4 channels of the system in the cryostat environment, 2-channel operation is demonstrated here. To this end, modulators with nominal resonances of λ1=1556.4 nm and λ3=1569.2 nm were selected. As shown in Fig. 1(a), these modulators are physically 400 µm apart. The experimental setup shown in Fig. 14 uses a 2 × 2 fiber coupler to combine two wavelength signals into a shared optical fiber and a standard coarse wavelength division fiber demultiplexer to separate the two signals. The performance of the system was measured at 10 Gbps. The system wavelength and signal amplitudes were optimized to find error free operation with both signals running. The optimum wavelengths for modulators 1 (λ1) and 2 (λ3) were found to be 1534.2 nm and 1545.7 nm, respectively. The laser wavelength for modulator 1 is slightly different from the optimum value suggested by Fig. 13(b) due to a thermal shift that is the result of the self-heating effect on the chip that shifts the modulator bias. Signal amplitudes of 1.1Vpp and 1.05Vpp were used to drive modulators 1 and 2, respectively. The improved performance at lower signal amplitude for the WDM demonstration when compared to Table 1 is likely due to variations in interfacing the chips, as electronic packaging was changed between these measurements to accommodate greater number of signal lines interfacing the chip.
Fig. 14. (a) Optical setup for the dual-wavelength BER measurements. The two BERTs are connected to a single clock reference. (b) BER vs. average received power. Optical attenuator is only used for power penalty measurement. The optical power in the bus waveguide is constant throughout the experiment as we increase the attenuation. However, some variation in the power in the waveguide can be seen since the modulator is operating near resonance. Attn: Attenuator
Figure 14 also shows the power penalty measurement at 10 Gbps. Here, the BER versus average received power is measured for two test cases: 1) a single modulator running (dashed traces), and 2) both modulators running (solid traces). For modulator 1 (red traces) the power penalty curves overlap very closely, but the BER saturates near 9e-11 before reaching error-free operation at −5 dBm. This indicates RF crosstalk was not an issue in our system. The shape could either be attributed to vibrations in the cryostat that lead to signal power fluctuations, or the noise distribution in the ON and OFF states of the signal. Modulator 2 reaches error-free operation at −3.5dBm, but interestingly, shows slightly better performance when modulator 1 is also running (solid blue trace). This small discrepancy may be due to a self-heating effect on the chip that moves the modulator bias a small amount.
6. Conclusion
By integrating silicon photonics with electronics in cryogenically cooled environments, whether for computing or data transmission to the outside world, the heat burden on these cryogenic systems can be significantly reduced. We reported 25 Gbps and 10 Gbps operation of standard silicon micro-disk modulators from the AIM Photonics’ PDK at room temperature and 40 K that were fabricated at AIM Photonics foundry. 2-channel WDM operation was realized by cascading these silicon micro-disk modulators with different resonance wavelengths. Results demonstrated an aggregate data rate of 20 Gbps at 40 K. We are now investigating a 4-channel WDM PIC that should provide a 40-Gbps aggregate data rate at 40 K.
Funding
U.S. Air Force (FA8650-15-2-5220).
Acknowledgements
The authors would like to further acknowledge the support of the Army Night Vision and Electronics Sensors Directorate and the Air Force Research Laboratory (AFRL/RYDI). Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525 (SAND2020-12238 J). The views and opinions expressed in this paper are those of the authors and do not reflect the official policy or position of the United States Air Force, Department of Defense, or the U.S. Government.
Disclosures
The authors declare no conflicts of interest.
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