1. Introduction

The high speed internet access in the households is putting a lot of pressure on the existing radio frequency (RF) technologies supported by the 802.11n standard [1] with net data rate between 54-600 Mbit/s. The optical domain is arising as support to the existing systems, the communication over plastic optical fiber (POF) is in use for many years reaching speeds in the Gbit domain (IEEE 802.3bv standard [2]). On the other side, the prospects for optical wireless communication (OWC) are just beginning to open. In 2011 a final standard for visible light communication (VLC) was established (IEEE 802.15). There, data rates range from 100 kbit/s to 100 Mbit/s [3] and various industrial and academic groups are pushing the VLC agenda. The main challenge for Gbit operation is the sensitivity of the optical receiver.

The optical receiver design is of high importance and suitable technologies must be chosen to achieve good overall speed and noise performance. There is a tradeoff between suitable technology for photonic devices and electrical circuitry especially in the infrared range where silicon cannot be used for photodetectors. For these reasons hybrid solutions have been demonstrated in the past such as an array of InGaAs PIN photodiodes flip-chip bonded to custom CMOS electrical circuits [4] and an external large-diameter APD wire bonded to a commercial TIA [5].

By moving to the visible range the production process can be simplified and its cost lowered by using silicon technology. The fully integrated solution on a single chip reduces the bonding parasitic and performance uncertainties. Optoelectronic integrated circuits (OEICs) in silicon have been around for more than 20 years, the integration of highly sensitive receivers has been thoroughly studied in [6]. The needed high biasing voltage for avalanche photodiodes (APDs) complicates the matter for APD OEICs. In order to achieve a high speed, a shallow p-n junction APD structure has been used [7], in this way slow carrier diffusion time constant is avoided but since there is no separate multiplication and absorption region, this leads to APD’s high ionization-coefficient ratio k_eff, which is the ratio of impact ionization probabilities of holes and electrons. The high k_eff together with poor low-field responsivity (R_PIN) of these photodiodes lowers the sensitivity of the receivers. Additionally, the lateral current flow of these photodiodes makes their bandwidth dependent on the length of the photodiode [8], therefore most of the structures have relatively small dimensions, for which a remedy can be to use the segmented photodiode [9]. In [10,11] a segmented APD with a p+\n-well structure was realized with an active area of 100 µm × 100 µm in a standard 0.35 µm CMOS process and used as a detector for VLC. However the APD was not integrated together with the transimpedance amplifier on the same chip but a commercial low-noise amplifier (LNA) was wire bonded to the APD. The commercial LNA had the advantages of a dedicated low-noise high-speed technology, but the need for wire bonding is not optimum for future mass production and makes the receiver less compact.

In our previous studies a different approach was pursued, the vertical photodiode structure with separate multiplication and absorption zone was realized in 0.35 µm pin-photodiode CMOS technology which offered bipolar devices with small modifications of the guard rings distance from the active devices [12,13]. Another implementation was in standard 0.35 µm high-voltage (HV) CMOS technology which offers deep wells (low dose implants) for high voltage which are surrounded by deep-well guard rings to prevent breakdown even down to −100 V of substrate voltage [14]. The p-wells of the NMOS transistors are inside deep n-wells, whose reachthrough voltage is larger than 100 V. The n-wells of the PMOS transistors are also inside deep n-wells guaranteeing their operation down to substrate bias of −100 V. So the CMOS circuits are well isolated from the negative substrate bias. Due to the vertical structure of the integrated APD, large active areas were possible. However, due to the suboptimal design of the electrical circuitry the 200-µm diameter APD OEIC (200APD OEIC) in HV CMOS [15] achieved more than 3 dB lower sensitivity than its BiCMOS counterpart with the same photodiode area at a data rate of 1 Gbit/s [12]. Based on the insights from the measurement of 200APD OEIC, a redesigned circuit with improved sensitivity is presented showing that pure CMOS-APD-OEIC design can compete with bipolar in the same feature size technology. Additionally, the receiver with increased photodiode diameter of 400 µm (400APD OEIC) is designed and measured. The benefits of increased photodiode diameter are demonstrated in optical wireless communication experiments in terms of increased transmitting distance without using any optics at the receiver side. The limits of maximizing APD dimension sizes in HV CMOS technology are predicted based on the measurement results of the APD devices on wafer level as well as characterization of 200APD and 400APD OEICs. The used HV CMOS process did not require any process modifications for integration of the APD. The integration does not include a DC-DC converter for substrate biasing since this component requires a large amount of chip area and the commercial options are relatively inexpensive and offer high efficiency.

2. High-voltage CMOS avalanche photodiode

The structure of the APDs used for integration is the same as in the previous technology run [14]. The cross-section of the APD is shown in Fig. 1(a). In contrast to the PIN photodiode process used in [12,13], the HV process is compatible with an antireflection-coating (ARC) layer which benefits the low-field responsivity, also wavelength dependent oscillation effects in the responsivity spectral curve due to optical interference are eliminated by ARC. Beneath the ARC layer is the APD’s active region. The APD has separate multiplication (n+/deep p-well) and absorption zone (deep n-well/p epitaxial layer). The deep n-well surrounding the n+ region prevents the edge breakdown and reduces the effective doping of the deep p-well. Lower effective doping of the p-well shifts the electric field distribution in favor of the absorption zone so that the depletion of the epitaxial layer is achieved before vertical breakdown. Since there are always differences from die to die, wafer-to wafer and in this case run-to-run, we measured again some important characteristics of the APDs at test structures on the wafer level such as capacitance and gain-bandwidth (GBW) product which are important for circuit design.

 

Fig. 1 (a) Cross section and (b) capacitance vs. reverse bias voltage of the HV CMOS APDs.

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2.1 Capacitance

The capacitance measurements were performed with an Agilent 4284A LCR meter. The LCR meter could provide up to 40 V of reverse voltage. At 40 V of bias voltage the test structure of the APD with 200-µm diameter has a capacitance of 621 fF and the 400-µm diameter APD has a capacitance of 2.33 pF. At higher bias voltages somewhat lower values can be expected based on the negative slope being still present at 40 V (see Fig. 1(b). According to [14], complete depletion of the deep n well occurs already at about 20 V and for higher biasing voltages the depletion edge spreads towards the p+ substrate.

2.2 Gain-bandwidth (GBW) product of the APD

The APD has all the time constants that determine the bandwidth of a PIN photodiode, such as RC time constant, drift time, diffusion time, etc. However, the APDs have one additional time constant called avalanche buildup time, meaning that after a certain multiplication gain M the APD’s bandwidth starts to deteriorate with further increase of M. For the GBW measurement the smallest realized APD with diameter of 100 µm was chosen so that the RC time constant coming from the photodiode capacitance and 50-Ω resistance of the transmission line was not limiting the BW. The bandwidths were determined by measuring the S21 parameter with a network analyzer which modulated the 675-nm laser source, while the other port was fed by the APD signal output. In Fig. 3(a) the measured gain-bandwidth curve is shown for an optical power of 2.5 µW. We can see the two important operating regions of the APD: the “constant” bandwidth region where velocity saturation occurs in the absorption (drift) zone and the APD has a maximum bandwidth of 1.4 GHz at M=7.5, and the “constant” gain-bandwidth product region where avalanche buildup time decreases the APD’s bandwidth. At the gain of approximately 50, the bandwidth of the APD is 740 MHz resulting in a GBW product of 35 GHz. At optical powers of 1 µW and 25 µW, at the same gain of M=50, the bandwidth is around 850 MHz, see Fig. 2(b), same as previously determined in [14] resulting in GBW product of 42.5 GHz. Although there are differences in APD characteristic from diode to diode and from wafer-to-wafer, these measurements still provide a rough estimate about the multiplication range for which the APDs in HV CMOS are suitable for Gbit operation. The photodiode had a low-field responsivity of approximately 0.4 A/W (675 nm), and the breakdown voltage of the photodiode was around 71 V, which are both similar values as those obtained in [14].

 

Fig. 2 (a) GBW curve and (b) BW of the HV CMOS APD at different optical powers.

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3. Large diameter APD receivers in high-voltage CMOS technology

The first design of 200APD OEIC in HV CMOS technology was reported in [15]. The design contained two opto-integrated circuits, one was the high-speed receiver for data communication with the 200-µm diameter APD, and the other circuit consisted of two highly-sensitive differential TIAs with four PN junction photodiodes for monitoring the position of the laser beam when the receiver is used in OWC application. The four PN photodiodes were forming a ring around the APD used for communication, pairs of opposite PNs were connected to differential TIAs. The proof of work for the sensing circuit of the PN photodiodes was done in [16], and it was not redesigned in this iteration since it had satisfactory results. The high-speed receiver, however, had noise and offset issues due to its feedback loop design, which can be seen in Fig. 5(a). The structure of the receiver is a pseudo-differential since there are two single-ended transimpedance amplifiers (TIAs) and differential postamplification. One TIA is connected to the APD while the other TIA (dummy) serves for providing the dc input to the limiting amplifiers. The dummy TIA is compensated with capacitor C_B which stabilizes it and reduces its bandwidth for noise reduction. The feedback loop that drives the dummy TIA in order to obtain the same dc levels at the input of the first limiting amplifier was closed around the TIA stages. The feedback loop consisted of the OTA and RC filters which worked as proportional integral (PI) controller. However, as it was shown in measurements, the limiting amplifiers and output f_t-doubler had their own input offset which was not compensated and was amplified towards the output. Another issue was that no RC filtering was used after the OTA stage. Therefore the noise of the OTA dominated the total input-referred noise current i_n,rms. The postlayout simulated noise bandwidth of the initial design was 527 MHz and i_n,rms was 787 nA with an input capacitance C_APD = 570 fF (simulated value), unfortunately main noise contributor was the OTA stage. The large noise contribution from the OTA resulted in a measured sensitivity of –31.8 dBm at 1 Gbit/s, which is worse compared to the APD receiver in pin-optimized BiCMOS technology [12] that reached –35.5 dBm at 1 Gbit/s. The measured bandwidth of the circuit was approximately 500 MHz, and the lower cutoff frequency originating from the feedback network was 589 kHz [17]. The receiver was initially designed for a high total transimpedance value of 450 kΩ with a current consumption of 45 mA at 3.3 V. During the measurements, the current consumption was lowered to 39 mA (by reducing the supply voltage of postamplifing stages) because the gain values of the postamplifing stages had to be decreased in order to reduce the effects of the offset voltage. The differential transimpedance had a value of 161 kΩ.

One way to overcome the offset issue would be to close the loop around the whole amplifying chain, and to place an RC low pass filter between the OTA and the dummy TIA. However, with that design, the dc points would still shift with the rise of the input photocurrent. Additionally, since the offset loop includes the dummy TIA, a current equal to the photocurrent should pass through the resistor in the RC network thus limiting its value or the values of the maximum input current. These points are especially important when having in mind that the receiver is intended for OWC communication, where the photocurrent can originate not only from the signal but also from the ambient light. For these reasons the topology presented in Fig. 3(b) is used in this design. The OTA is being fed from the back of the amplifying chain, which should theoretically eliminate the offset of the postamplifers.

 

Fig. 3 Block diagram of the 200APD OEIC: (a) offset loop around the TIAs (previous design) (b) offset loop around the whole amplifying chain and dc current cancellation (new design).

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The source followers as level shifters at the output of the f_t-doubler were needed to provide suitable dc input for the OTA. The dc current is subtracted from the main TIA node via NMOS transistor M_S. In this way with the increasing average APD photocurrent the dc points of the circuit are not disturbed. An RC network consisting of 5-kΩ resistor and 5.5-pF capacitor is placed on chip to reduce the noise of the OTA. Since it was connected to the gate of M_S, there is no current to make a voltage drop across the 5-kΩ resistor. Now the loop gain of the overall offset feedback loop includes the passband gains of the amplifying stages, thus increasing the lower cut-off frequency [18] of the receiver. For these reasons, large off-chip 100-nF capacitors (marked in red) had to be used to lower the cutoff frequency to 16 kHz, which should eliminate any DC wander effects.

The folded cascode TIA (see Fig. 4) design is not changed compared to the previous run [15], since it was already well noise optimized. The input capacitance of M₁ was C ^̃_IN = 316 fF, a little more than half of the estimated photodiode capacitance, C_APD = 570 f_F. Based on [19], the input capacitance of a common-source (CS) amplifier (C ^̃_IN =C_GS+C_GD) in a shunt-feedback TIA should be equal to the photodiode capacitance for a minimized input referred noise current. Here this condition was purposefully not fully achieved, since such a large transistor would need a large biasing current and the feedback resistance would need to be halved, which would increase its noise contribution and the noise contribution of the postamplifing stages. The simulated postlayout bandwidth of the TIA stage is 778 MHz when no loading is present at the output. The TIA has a transimpedance gain of 3.11 kΩ. The current consumption of the limiting amplifiers is increased to maximize their bandwidth, the four stage limiting amplifiers consume about 22 mA as well as f_T-doubler, whereas the TIA’s consumption is 7.52 mA. The postlayout simulations of the whole receiver result in an increased bandwidth of 604 MHz, the noise bandwidth BW_n is 622 MHz, and the total input referred noise current i_n,rms is 153 nA. Therefore, by redesigning the feedback loop even with a larger noise bandwidth, i_n,rms was decreased approximately five times compared to the previous design. The total transimpedance gain is 266 kΩ. The measured current consumption of the new design together with the circuitry for four PN photodiodes is 55.3 mA at 3.3 V of supply voltage.

 

Fig. 4 TIA circuit diagram with component values and biasing.

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Since the redesigned 200APD OEIC showed overall good noise and bandwidth simulation results, another receiver with increased photodiode diameter was designed. The 400-µm diameter APD receiver (400APD OEIC) was designed in the same HV CMOS technology, since the increased photodiode diameter should lead to reduced irradiance (optical power density) needed for OWC. The same TIA topology was used as for 200APD OEIC.

The folded cascode TIA for increased photodiode diameter has a larger input transistor M₁ in order to match the estimated capacitance of C_APD = 2.28 pF, C ^̃_IN = 1.066 pF which is slightly less than half of the C_APD. The drain current of M₁ was also scaled up to reach the desired current density. The feedback resistance R_FB needed to be reduced by a factor of two for this design. The postlayout transimpedance of the TIA is 1.48 kΩ and the bandwidth when no loading is present at the output is 744 MHz. Since the TIA has a smaller transimpedance gain in this design, the output f_t-doubler was replaced with simple differential 50-Ω output buffer, which offered more gain. The overall simulated transimpedance of the 400APD OEIC is 241 kΩ. The postlayout simulated bandwidth of the entire receiver is 631 MHz, the noise bandwidth is 656 MHz and the total input referred noise current is 253.7 nA (1.65 times larger than 200APD OEIC). The measured current consumption is 67.4 mA at 3.3 V of supply voltage.

3.1 Simulated sensitivity

In contrast to the PIN receivers, the sensitivity of the APD for a certain bit-error rate (BER) cannot be calculated straightforward. Because the avalanche noise of an APD is not negligible, the improvement of the signal-to-noise ratio is smaller than the multiplication factor M and there are codependences on M in the expressions for noise and sensitivity. The avalanche noise comes from the randomness of the multiplication process and it is signal dependent. The mean square noise current of an APD can be expressed as [19,20]:

Since the multiplication raises the excess noise factor F, but also amplifies the signal (I_APD = P_{0,1}∙M∙R_PIN), there must be an optimum multiplication gain which minimizes the noise. At this optimum multiplication, the noise generated from the APD, i_n,APD, should be equal to the amplifier’s total input-referred noise, i_n,TIA. Knowing the total input referred noise current given in Eq. (3), the BER function is [20]:

Since both numerator and denominator of Eq. (5) depend on the avalanche multiplication gain, a numerical solving approach by MATLAB as in [21] is used to determine the optimum M to calculate the optical sensitivity for BER = 10⁻⁹. The MATLAB program sweeps the average input optical power P versus M and searches for the lowest P for which BER < 10⁻⁹. During the calculations, the mean photocurrent value is used as a threshold I_th. In the second iteration, the sweep is zoomed around the result from the first iteration, and the final value for the sensitivity of the APD receiver and the optimum multiplication M can be obtained.

The parameters used for the simulations were BW_n = 656 MHz, R = 0.41 A/W, k_eff = 0.0849 [22] and laser extinction ratio ER = 8 (measured). The total input-referred noise current of the amplifier, i_n,TIA, was swept during the simulation and the optimum multiplication and sensitivity curves depicted in Fig. 5 were obtained. Based on the i_n,TIA and BW_n obtained in the postlayout simulations, the simulated sensitivity for 200APD OEIC is –35.9 dBm and optimum multiplication is M = 25, while the 400APD OEIC has a simulated sensitivity of –35.15 dBm and an optimum multiplication of M = 32. As we can see from Fig. 5(a), the optimum gain M increases with increasing total input referred noise current of the receiver, i_n,TIA, so when the circuit becomes noisier, more APD gain is needed to overcome this noise. Also, as seen from Eq. (2), the optimum gain is also a strong function of k_eff, which is determined by the technology. As k_eff increases, the optimum multiplication should decrease to keep F small. The HV CMOS offers low noise silicon APDs with k_eff = 0.0849, which is a much lower value than modulation doped APDs produced in same feature size pin-photodiode CMOS technology, whose k_eff = 0.4175 [22]. The modulation doping was used to increase the BW of the APDs at the cost of a higher working voltage and to reduce the pronounced voltage dependence of multiplication gain that was present in APDs without modulation doping in the same technology. For APDs without modulation doping in pin-photodiode CMOS technology, the k_eff could not be estimated, but the excess noise factor F is about 5, which was comparable to the HV CMOS process at M = 40. Therefore, the 0.35 µm HV CMOS process promises a high sensitivity.

 

Fig. 5 Simulated (a) optimum M and (b) sensitivity of the APD receivers in HV CMOS.

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4. Measurement results of APD receivers in HV CMOS

4.1 Optical sensitivity

The optical receiver sensitivity is defined as the minimum average optical power to reach a certain BER. It was measured at 675 nm wavelength with a VCSEL as light source. The laser source had an extinction ratio of 8, and it was modulated with 2³¹-1 pseudorandom binary sequence (PRBS31) using SYMPULS BMG 12GIG bit pattern generator. The output of the laser source was guided via multimode fiber down onto the photodiode area of the HV CMOS receivers. The optical power levels were adjusted using an external optical attenuator and measured via an optical power meter. For the high voltage biasing of the substrate, a KEITHLEY 2612 source meter was used that could also measure the APD currents in the nA range. The substrate voltage was manually adjusted in order to reach the best sensitivity.

Figure 6(a) shows the measured sensitivity curves of the 200APD receiver at different data rates. At 1 Gbit/s, the 200APD receiver achieved the sensitivity of approximately –35.5 dBm, which fits well with the simulated value. This sensitivity was achieved at an APD bias voltage V_APD = –73.7 V, which resulted in M ≈ 49. This multiplication gain is much higher than the simulated optimum M. The possible explanation why the measured optimum M is higher than expected is twofold. First, we do not know the value of the total serial resistance R_S of the APD (from cathode terminal to the TIA and from anode terminal to the substrate).

 

Fig. 6 Measured BER vs. average optical power, λ = 675 nm, PRBS31: (a) 200APD OEIC, (b) 400APD OEIC.

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This series resistance R_S produces thermal noise which gives an additional noise term in the input-referred noise current power spectral density (PSD) equal to 4kTR_S(2πC_APD)²f ² [23]. The second, more important reason is the small offset that was present in the circuit for amplified photocurrents lower than 7–8 µA, depending on the chip sample. The probable culprit for this is the offset of the f_T-doubler stage which was too large for the offset feedback loop. The 400APD OEIC does not have this stage and it shows no offset problems for any input current. Nevertheless, the 200APD OEIC achieved 3.7 dB improvement in sensitivity compared to the previous design [15,17] and, more importantly, the 200APD achieved the same sensitivity as its BiCMOS counterpart with the APD of the same area at 1Gbit/s [12]. This is an important result for the receiver designed in standard HV CMOS technology, since the transconductance (g_m) and therefore the gain of the CMOS amplifiers, is inferior compared to g_m of BiCMOS transistors for the same bias current. The sensitivity of the 200APD OEIC was measured at two additional data rates of 622 Mbit/s and 1.25 Gbit/s (standards for passive optical networks, PON) and reached sensitivities of –36 dBm and –34.2 dBm respectively.

The 400APD OEIC reached the sensitivity of –34.7 dBm at 1 Gbit/s, the optimum substrate voltage was –73.7 V, which for this receiver resulted in M = 41. This multiplication value is again somewhat higher than the simulated one of 32. The probable reason is again the unaccounted resistance present in series with APD. This sensitivity is comparable to its BiCMOS counterpart with same photodiode area, which reached sensitivity of –34.6 dBm at 1 Gbit/s [12]. The measured sensitivity curves at 622 Mbit/s (P_sens = –35.7 dBm) and 1.25 Gbit/s (P_sens = –32.8 dBm) are also present in Fig. 6(b). The sensitivity of the 400APD receiver was measured even up to 1.5 Gbit/s and reached −30.7 dBm (BER≤10⁻⁹). However there is about a 3 dB drop in sensitivity compared to 1 Gbit/s for which the receiver was initially designed. Based on the rise and fall times of the transient response, the maximum data rates can be conservatively estimated as 1.26 Gbit/s for the 200APD receiver, and 1.225 Gbit/s for the 400APD receiver.

4.2 AC response

For the measurement of the AC response, like in the BW measurements of the photodiode, the 675-nm laser source was modulated by one port of a Rhode&Schwarz ZVR vector network analyzer, while one of the OEIC outputs was connected to the other port. The normalized frequency responses of both APD receivers are shown in Fig. 7.

 

Fig. 7 Normalized AC responses of 200APD and 400APD OEIC, V_SUB = –74 V, λ = 675 nm, P_avg = –31.2 dBm.

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The 200APD OEIC has a measured bandwidth of 560 MHz, which is improved compared to the previous design [17], where the bandwidth of 500 MHz was achieved. The BW increase was expected, since the electrical circuitry had higher bandwidth in simulation at the cost of higher power consumption, but also because the substrate contacting was improved by increasing the contacting area in order to reduce the APD’s serial substrate resistance. The lower –3-dB cutoff frequency is around 20 kHz, which is a much smaller value compared to 589 kHz previously measured in [17]. The 400APD OEIC has a bandwidth of approximately 500 MHz, which is a smaller value compared to the 200APD OEIC and to the simulated value of 630 MHz. The reason is that the RC time constant coming from the parasitic serial resistances of the APD, interconnects and R_IN of the TIA together with the C_APD was probably too large. Nevertheless, high sensitivity was reached at 1 Gbit/s. The lower −3-dB cutoff frequency was 27.6 kHz.

5. HV CMOS APD OEICs as optical receivers for OWC

For OWC experiments, the setup depicted in Fig. 8(a) was used. The experiments were conducted in our laboratory with normal lighting levels in the range 300–500 lux measured at the receiver installation. During the measurements no optics was used to increase the detection area and there was no optical filter in front of the APD receiver, the receiver’s PCB was mounted on a rotatable platform, the outputs of the receiver were fed into the BER tester (SYMPULS SBF 10 GIG) and into the Tektronix DSA8200 oscilloscope. A narrow beam transmitter, a 680-nm VCSEL with the average output power of 0.85 mW, was modulated by a driver MAX3740A with PRBS31 using the SYMPULS BMG 12GIG pattern generator.

 

Fig. 8 (a) OWC setup and (b) beam diameter vs. transmitting distance.

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The beam shaping was performed using the cost effective collimating lens MPG-95 from Roithner, which was mounted in a plastic tube that allowed adjustment of the collimation. The resulting beam divergence was measured to be 0.057 degrees (full width at half maximum, FWHM). For beam characterization a monochrome CMOS camera was used, the data was processed in MATLAB and the beam diameters as well as beam divergence were calculated, see Fig. 8(b). The narrow beam was steered via a MEMS mirror from Mirrorcle (S1911) [24].

The narrow transmitter beam together with the high sensitivity of the APD receivers enabled large distances for error free (BER < 10⁻⁹) transmission. At a data rate of 1 Gbit/s the maximum transmitting distance is 12 m with the 200APD OEIC and 22 m with the 400APD OEIC, see Fig. 9. Doubling of the APD diameter resulted in this case in 1.83 times increase of the transmission distance. This result was expected since doubling of the APD diameter reduces the irradiance needed for receivers in given technology, as was already seen in [25] when BiCMOS APD receivers were used. Comparing to [26], where the same OWC setup was used, the 200-µm diameter APD BiCMOS receiver reached 11 m of error free distance while the 400-µm diameter BiCMOS APD receiver reached 20 m [27].

 

Fig. 9 Measured BER at different transmitting distances at 1 Gbit/s.

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In contrast to a previous HV CMOS design where the same system setup was used [15], now we improved the transmitting distance from 7 m to 12 m i.e. 1.71 times, therefore sensitivity improvement had similar effect as doubling the photodiode diameter. During the measurements the substrate of the 200APD receiver was biased at –74 V, whereas that of the 400APD receiver was biased at –73.8 V. Figure 10 shows the eye diagrams at maximum transmitting distances. In this environment, with a dc current coming from the office lighting, the feedback loop in the redesigned 200APD OEIC can now work properly, even for low signal input optical powers, see Fig. 10(a).

 

Fig. 10 Eye diagram at: (a) 12 m distance, 200APD OEIC and (b) 22 m distance, 400APD OEIC at 1 Gbit/s.

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In comparison, the APD realized as p+/n-well structure wire bonded to a commercial low-noise amplifier could achieve 1.5 m of transmitting distance at 3 Gbit/s [10] in VLC setup with 680 nm VCSEL transmitter collimated with an aspheric lens. However the transmission was at BER < 10⁻⁶ and an aspheric lens with 50 mm diameter was used at the receiver side to increase the collection area. In an outdoor link [11] the same receiver could achieve 72 m of transmitting distance at data rates between 1 Gbit/s and 2 Gbit/s for a BER below the forward error correction (FEC) limit of 3.8 × 10⁻³ and with a 75 mm diameter aspheric lens in front of the APD receiver. It was stated that the needed optical power was approximately −30 dBm in the Gbit range. Our receivers were operated for the BER limit below 10⁻⁹. If the BER limit would be relaxed to the FEC level we can see from Fig. 6 that the sensitivity of our receivers would be improved by more than 4 dB, which would give 9-10 dB improvement in sensitivity at 1 Gbit/s compared to [10,11]. The APD receivers described in this manuscript besides higher sensitivity have also a larger APD area compared to [10,11] by a factor of 3.14 (200APD receiver) and 12.56 (400APD receiver), therefore we could achieve over 10 meters and over 20 meters, respectively, of error free transmission distance without using any optics at the receiver side.

Both of the APD receivers are lens less, therefore the reception of the optical light should be possible in a full field of view (FOV). However, due to the angular power penalty of cosα when receiver is under the angle α in respect to the optical axis, BER deterioration is to be expected. The maximum receiving angle for which the receiver can be tilted in respect to the optical axis and still have BER < 10⁻⁹ depends on the starting BER level. The 200APD OEIC was placed at 11 m, and the 400APD receiver was placed at 20 m since these distances have BER < 10⁻¹⁰, which gives some margin for angular displacement. In the case of the 200APD OEIC, the BER is below the 10⁻⁹ limit up to a full incidence angle of 76°(±38°), and those results are similar for the 400APD OEIC which has a full receiving angle of 74°(±37°). The receiving angle for a lens less receiver does not depend on the photodiode diameter. These results are similar to the full receiving angle of 68° achieved with the previous design [24] where a higher starting BER value was used (approx. 1∙10⁻¹⁰). Compared to a receiving angle of 20° ± 1° of lens less APD BiCMOS receivers (starting BER < 10⁻¹⁰ [26,27]), the receiving angle of the HV CMOS APD receivers is much wider; this is due to the presence of ARC on the HV CMOS APDs that prevented optical interference effects.

During the transmission experiments the main ambient light source was the office lighting which under normal ambient conditions enabled the proper work of the receivers at high transmitting distances as seen above. In order to examine the performance of the receivers with different light sources and different illuminance levels, we used adjustable light sources which are otherwise intended for microscope lights. The light sources were white LED, and two halogen lights from OSRAM: halogen lamp 64637 and halogen lamp 64627. The optical spectra were measured using an AvaSpec3648 spectrometer. The spectra are shown in Fig. 11. These light sources have better color characteristics, i.e. more continuous optical spectrum than the fluorescent office lighting which has peaks at certain emission lines.

 

Fig. 11 Optical spectra of the used adjustable ambient light sources and office lighting.

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The 200APD OEIC was placed again at 11 m of transmitting distance, and the data rate of the VCSEL transmitter was 1 Gbit/s. The BER measurement results of the 200APD OEIC under different ambient lights can be seen in Fig. 12. When the substrate biasing voltage was kept at –74 V, which was the optimum under our lab lighting, the maximum illuminance in case of halogen light sources was approximately 2000 lux for BER < 10⁻⁹. However, as the illuminance would go up, the offset loop could work properly and the biasing could be lowered to an optimum value (smaller M) and higher level of lux could be tolerated. At –71 V of biasing voltage in case of the halogen lamps, the maximum illuminance was 4000 lux (halogen 64627) and 3700 lux (halogen 64637) for BER < 10⁻⁹. The LED light has a more favorable optical spectrum and induced less dc current with respect to the lux level. At –74 V the maximum level of allowed illuminance was 3100 lux, whereas at –71 V the maximum allowed illuminance was 6150 lux.

 

Fig. 12 200APD OEIC: BER vs. background illuminance, distance 11 m, 1 Gbit/s, VCSEL 680 nm.

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The measured results for the 400APD OEIC are shown in Fig. 13. The 400APD OEIC was placed at 20 m of transmitting distance, the data rate was 1 Gbit/s and the biasing voltage was kept at –73.8 V. The maximum allowed illuminance was 560 lux for halogen lamp 64637, 600 lux for halogen lamp 64627 and 2000 lux for the white LED. The 400APD OEIC is more sensitive to ambient light than the 200APD OEIC since it has a four times larger collection area, i.e. four times larger induced primary dc photocurrent coming from ambient light sources. Although the dc photocurrent does not shift the dc levels in the circuit due to the feedback loop, there is a shot noise contribution from this dc background photocurrent, I_BCG, which would be added to the I_PIN in the noise expression Eq. (1). Therefore, the optical spectrum of ambient light has a strong influence on the APD receivers. Compared to BiCMOS APD receivers [26] and [28], which were tested with halogen lamp 64627 and could sustain 6000 lux and 2000 lux in case of 200-µm and 400-µm diameter APD, respectively, the HV CMOS receivers are more sensitive to ambient light. The main reason for this is a high receiving angle because with ARC there are no oscillations in the responsivity spectra. Of course, the HV CMOS receivers could work even with higher levels of background light, but the starting BER level would have to be lower, which would mean shorter transmitting distances for this setup. Additionally, the adjustable light sources were pointed directly onto the receiver area, whereas in practical installation the receiver could be oriented in other direction to reduce I_BCG.

 

Fig. 13 400APD OEIC: BER vs. background illuminance, distance 20 m, 1 Gbit/s, VCSEL 680 nm.

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It is worth noting that the change in the ambient light level i.e. a change in the input dc photocurrent will disable the transmission for a time needed by the feedback loop to regulate the offset. In the case of our receivers, during this time the current through M_S (see Fig. 3) needs to be settled to the right value so that there is no dc current coming into the TIA. This recovery time (τ_rec) will depend on the level of the dc background induced photocurrent. As the dc current increases, the recovery time also increases. The amplified primary background photocurrent, I_M,BCG = M∙I_BCG, in the case of the 400APD receiver was approx. 3 µA at 500 lux and 10 µA at 2000 lux when halogen lights were used. For small values of I_M,BCG under normal ambient conditions (500 lux) the limiting amplifier still worked even without the settled input current. For the upper limit of 2000 lux, I_M,BCG would be too large and the transmission would have to be interrupted during τ_rec which in this case would be approximately 10 ms according to simulation. In the case of the 200APD receiver the values of I_M,BCG would scale with the APD area and ratio of optimum M of the two receivers.

6. Maximizing the APD diameter in HV CMOS for a data rate of 1 Gbit/s

As could be seen from the results in previous sections, a larger photodiode diameter d increases the total input-referred noise current thus degrading the sensitivity, but also increases the photodetection area. In an OWC application this leads to a decrease of the needed irradiance for achieving a certain BER, which was demonstrated in previous section by the increase of the transmission distance when using 400APD OEIC as a receiver compared to 200APD OEIC. Therefore, by maximizing the APD diameter, performance gains in OWC are to be expected, under the condition that there is no excessive ambient light illuminance, which should be satisfied in an indoor environment. In order to find the maximum possible diameter, we must first see how the total input-referred noise current scales with the photodiode diameter d. If we look at the photodiode’s space-charge region (SCR) capacitance as a parallel plate capacitor whose plate distance is equal to the width W of SCR and whose plate area A is equal to the photodiode area, the capacitance can be approximately calculated by the following formula:

As an approximation, the photodiode capacitance scales with d ². The formula for the input-referred mean-square noise current of a shunt-shunt feedback TIA with a feedback resistance R_F and a MOSFET in common source (CS) configuration is given with [23]:

Another issue is that, as i_n,TIA increases, the optimum multiplication gain M also increases, and our APD’s GBW product is constant. Although the GBW curve measured in Section II may shift from photodiode to photodiode, for a rough estimation of the maximum multiplication for which the APD in HV CMOS still has enough bandwidth, we will take M = 50, for which the BW_APD = 850 MHz. This value can be taken as an intrinsic photodiode bandwidth, BW_IN, whereas the total –3-dB bandwidth of the OEIC can be approximately calculated as [29]:

Since we are aiming at the data rate of 1 Gbit/s, the optimum BW_total should be equal to 700 MHz. As a conservative value based on Eq. (8) the external bandwidth, BW_EX, coming from the total input capacitance and input resistance of the front-end R_in – i. e. the TIA bandwidth – should be equal to 1.25 GHz, which is feasible in a 0.35 µm HV CMOS technology with f_T = 25 GHz. We will assume, for the simulation purposes, a brick wall low-pass transfer function of the optical receiver for which BW_n = BW_total = 700 MHz. For the scaling purposes, the reference 100-µm diameter APD receiver with bandwidth of 700 MHz (including the reduction due to the intrinsic photodiode BW) will be assumed. The total input-referred noise current i_n.TIA of this receiver with a 100 µm diameter APD can be estimated to approximately 80 nA based on the values of i_n,TIA for the 200APD OEIC and 400APD OEIC, which had simulated noise bandwidths between 622 MHz and 656 MHz, and scaling the noise with the BW^1.5 [23]. By using MATLAB code as in [21], the optimum multiplication and optical sensitivity for BER < 10⁻⁹ can be simulated with respect to the photodiode diameter. Figure 14(a) shows the optimum multiplication depending on the photodiode diameter, For M = 50, the photodiode diameter is d = 790 µm ≈ 800 µm, and the sensitivity is –33.38 dBm. The simulated sensitivities for 200 µm APD and 400 µm APD receivers with these parameters are –35.7 dBm and –34.59 dBm respectively, which is again very close to the measured results marked at Fig. 14(b). We see that by doubling the photodiode diameter there is between 1.1 dB and 1.2 dB loss in sensitivity, but the needed irradiance would decrease with a factor of approximately 3 when the diameter is doubled. If the same setup for OWC would be used, the APD receiver with the maximum diameter of 800 µm would achieve a transmitting distance of 34 m, therefore the theoretical transmitting distance increase would be 1.7 times with doubling of the photodiode diameter.

 

Fig. 14 (a) Simulated optimum APD multiplication and (b) simulated sensitivity curve depending on APD diameter, ER = 8, BW_n = 700 MHz, R = 0.41 A/W, k_eff = 0.0849, i_n,TIA = 80 nA @ APD Ø = 100 µm, I_th in the middle.

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7. Conclusion

Low cost, compact and highly sensitive integrated optical receivers are needed for future wireless optical communication. The increase of the photodiode diameter is challenging, and thus its capacitance, because there is a tradeoff with optical sensitivity and, in some cases, speed. Integrated solutions in standard 0.35 µm HV CMOS process are demonstrated. The redesigned 200 µm diameter APD receiver reaches an excellent sensitivity of –35.5 dBm at 1 Gbit/s. Additionally, the high speed receiver with increased photodiode diameter of 400 µm was designed and reaches a high sensitivity of –34.7 dBm at 1 Gbit/s. The reached sensitivities are comparable to the APD receivers in [26,27] where bipolar transistor were available. The performance gains were demonstrated through OWC experiments where increase of the transmission distance without any optics at the receiver side was demonstrated. High transmission distances at 1 Gbit/s were reached up to 22 m. The characterization of both receivers enabled the estimation of the maximum possible diameter of the APD receiver in a given technology as well as performance gains in OWC applications. The maximization of the APD diameter has obvious benefits for a single channel lens less receiver in terms of reduced needed irradiance, but it can also be useful for maximizing the cell size in angle diversity receivers or in single channel imaging receiver, since the focused beam spot has more available area for possible offset from the photodiode center, requiring less expensive and complex optics. Due to their high operating voltages, these receivers would not be suitable for optical wireless interface in mobile phones, but numerous applications would be possible in RF-sensitive areas such as hospitals and airplanes, or fabrication halls where a high speed communication with low latency is required and power consumption and voltage regulation is not a limiting factor.