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Abstract
In this study, we examine the electrical characteristics of complementary metal−oxide−semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.
© 2018 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
Recently, there have been several studies on the introduction of optoelectronics in industrial and scientific applications for image sensing, surveillance cameras, flame detectors, remote control, chemical and biological sensing, and optical interconnects for inter chip data communication [1–7]. These technologies commonly use photosensors and photodetectors made of pn- or pin- photodiodes that tend to be easily disrupted due to substrate noise and crosstalk from adjacent diodes [7–9]. This makes it difficult for the device to perform better than phototransistors. Conventional metal-oxide semiconductor field-effect transistor (MOSFET)-based phototransistors are used in civil and military applications because of their low cost, low-power consumption, high performance, and design flexibility [10–15]. However, the scaling down of traditional MOSFET-based optoelectronic devices is becoming increasingly difficult due to their fundamental material and process limitations [16–19]. Silicon nanowire (SiNW) MOSFETs are particularly effective in overcoming these scaling limitations [20–25]. Top-down fabrication methods enable the controlled assembly of SiNWs into well-ordered arrays at accurate locations, which allows for the implementation of integrated photonic systems. In addition, SiNW MOSFETs have excellent electrical switching characteristics because their 3D gate structures provide immunity from the superior short channel effect and their processes are compatible with current CMOS technologies.
In this paper, we report the electrical characteristics of SiNW CMOS inverters under illumination. Our device is suitable for photosensors and photodetectors because of its high absorption rate and efficient photocurrent generation using transparent substrates. The SiNW CMOS inverters also show variation in the switching threshold voltage (Vinv) under different laser powers and wavelengths. This means that the device can be accurately controlled by sensing the incident light, which enables it to be effectively used in highly sensitive optoelectronic applications within the visible light range.
2. Experimental procedures
SiNWs were derived from a (100)-orientation bulk p-type silicon wafer using top-down CMOS-compatible technologies, i.e., photolithography, crystallographic wet etching using tetramethylammonium hydroxide solution, and thermal oxidation. We separately formed n+ and p+ source/drain regions through ion implantations with BF2+ and As+ ions at a dose of 5 × 1015 cm−2 and ion energies of 80 and 50 keV, respectively, followed by activation annealing. Next, we applied wet chemical etching using buffered oxide etchant solution to remove the surrounding oxide. The SiNWs with a diameter of 100 nm were transferred onto 200-μm-thick transparent polyethersulfone substrates through the direct transfer method. The source/drain aluminum metal electrodes (100-nm thick) were deposited using a thermal evaporation process and then 15-nm high-k Al2O3 gate oxide layers were formed by atomic layer deposition. Finally, gate aluminum metal electrodes (100-nm thick) were fabricated by a thermal evaporation process.
The optical image and schematic illustration of a SiNW CMOS inverter consisting of n- and p-SiNW field-effect transistors (FETs) on a transparent substrate are shown in Figs. 1(a) and (b). The SiNW CMOS inverter incorporates a 1:3 ratio of n- to p-SiNWFETs in order to compensate for the hole mobility. The source of the p-SiNWFET is connected to the supply voltage (Vdd) and the source of the n-SiNWFET is connected to the ground voltage (GND). The drains of both the n- and p-SiNWFETs are tied together as the output node (Vout). The input voltage (Vin) is connected to the gate nodes of both the n- and p-SiNWFETs. Therefore, both SiNWFETs are driven directly by the input signal. The channel lengths (Lch) of both the n- and p-SiNWFETs are designed to be 2.0 µm and Al gate electrodes (width = 3.0 µm) are arranged on the channel region in order to have adequate gate-to-drain overlap [26–28]. Lasers were used as the light source with 633-nm and 532-nm wavelengths and powers of 0.4 mW and 0.8 mW. To minimize bias stresses, the lasers were switched off and the devices were left in the dark for 10 min before each measurement. All electrical characteristics of the SiNW CMOS inverters were measured with a semiconductor parameter analyzer (Agilent 4155C).
Fig. 1 (a) Optical images and (b) schematic illustration of the SiNW CMOS inverter on a transparent substrate.
3. Results and discussion
We first examine the electrical properties of the individual n- and p-SiNWFET used for constructing the SiNW CMOS inverter. Figures 2(a) and (b) show the drain current (Ids) versus the gate-source voltage (Vgs) characteristics of p-SiNWFET for Vdd = 2 V under different wavelengths (red = 633 nm, green = 532 nm) of light. The on-current (Ion) and the off-current (Ioff) are measured at the laser power of 0.4 mW. Ion under darkness and under 633-nm- and 532-nm-wavelength light are ~10.3, ~10.1, and ~10.2 µA, respectively, and Ioff under darkness and under 633-nm- and 532-nm-wavelength light are ~214, ~294, and ~429 pA, respectively. The threshold voltages (Vth) under darkness and under 633-nm- and 532-nm-wavelength light are determined to be −2.01, −1.41, and −0.81 V, respectively, as shown in Fig. 2(a). At the laser power of 0.8 mW, Ion under darkness and under 633-nm- and 532-nm-wavelength light are 9.8, 10.6, and 10.9 µA, respectively, and Ioff under darkness and under 633-nm- and 532-nm-wavelength light are ~0.2, ~1.6, and ~5.2 nA, respectively. Vth under darkness and under 633-nm and 532-nm wavelength light are −2.5, 0.47, and 0.97 V, respectively, as shown in Fig. 2(b). The results show that Ion has similar values but Ioff gradually increases under different wavelengths of light. Furthermore, as the laser wavelength decreases and the laser power increases, Ids increases and Vth shifts toward the positive direction. This indicates that the rate of electron-hole pair (EHP) generation varies with the laser wavelength and intensity [29, 33-34]. The rate of generation of EHPs is proportional to the amount of illumination and depends on the absorption coefficient for silicon in the channel [7, 10, 14, 29–37]. The absorption coefficient generally increases at shorter wavelengths, because the short wavelength light is absorbed near the Si surface and results in increasing the rate of EHP generation [38]. In addition, the conductance of the silicon channel increases with higher laser power because the incident spectral photon flux density increases [7].
Fig. 2 Ids-Vgs transfer curve of the SiNWFETs for Vdd = 2 V under different wavelengths (black = darkness, red = 633 nm, green = 532 nm) of light. The fixed laser power for p-SiNWFET is (a) 0.4 mW and (b) 0.8 mW, and the fixed laser power for n-SiNWFET is (c) 0.4 mW and (d) 0.8 mW.
Figure 3(a) shows that the SiNW absorbs light through a transparent substrate. Figures 3(b) and (c) show the energy band diagram of n- and p-SiNWFET when a forward voltage is applied under illumination. This variation in the photocurrent with regard to the laser wavelength and power is more distinct in the subthreshold region, so the current ratio (Ion/Ioff) decreases as Ioff increases [39]. This indicates that the off state leakage current is higher under illumination. Figures 2(c) and (d) show the output (Ids-Vgs) plot of the n-SiNWFET. There is an increase in Ids similar to that seen in the p-SiNWFET, especially in the subthreshold region, because of the generation of EHPs. Because the SiNW CMOS inverter was fabricated in a 1:3 ratio representing the number of n-SiNWFET to the number of p-SiNWFET, the channel width (Wch) of the p-SiNWFET is three times longer than that of the n-SiNWFET. Therefore, the current variation in the n-SiNWFET when illuminated is smaller than that in the p-SiNWFET. The longer the channel width, the greater the area where the light can be absorbed, resulting in the availability of more photocurrent.
Fig. 3 (a) Schematic illustration of the SiNW under illumination. An energy band diagram of (b) n-SiNWFET and (c) p-SiNWFET when a forward voltage is applied under illumination.
The voltage transfer characteristic (VTC) of the SiNW CMOS inverter based on these n- and p-SiNWFETs for Vdd = 2 V is shown in Figs. 4(a) and (b). The inset shows the voltage gain curves with respect to each laser wavelength. Vinv under darkness and under 633-nm- and 532-nm-wavelength light are ~−0.7, ~0.3, and ~0.8 V, respectively, and the corresponding voltage gains are 2.57, 2.83, and 3.41, respectively, at the power of 0.4 mW, as shown in Fig. 4(a). At the power of 0.8 mW, Vinv under darkness and under 633-nm- and 532-nm-wavelength light are −0.9 V, 0.5 V, and 1.1 V, respectively, and the corresponding voltage gains are 2.38, 3.70, and 4.05, respectively, as shown in Fig. 4(b). The shorter wavelength and the higher laser power increase not only Vinv but also the voltage gain under illumination because the variation in each SiNW influences the electrical characteristics of the SiNW CMOS inverter. This is because more charge carriers in the SiNW channel are generated due to the decrease in wavelength and the increase in laser power. The higher voltage gain indicates that there is a much sharper transition slope of the SiNW CMOS inverter, resulting in a faster switching speed [40–42]. These characteristics demonstrate the potential for SiNW CMOS to be used in sensitive optoelectronic devices that can detect a specific wavelength within the visible light region.
Fig. 4 Voltage transfer characteristic curve (VTC) of the SiNW CMOS inverter for Vdd = 2 V under different wavelengths (darkness = 0 nm, red = 633 nm, green = 532 nm). The corresponding voltage gain curves are shown in the inset. The fixed laser power is (a) 0.4 mW and (b) 0.8 mW.
Next, we measured the current flow with a fixed wavelength under different laser powers for Vdd = 2 V. Figures 5 (a) and (b) show the Ids-Vgs characteristics of the p-SiNWFET for Vdd = 2 V under different laser powers (darkness = 0 mW, blue = 0.4 mW, pink = 0.8 mW) at the wavelength of 633 nm and 532 nm, respectively. Figures 5(c) and (d) show the output (Ids-Vgs) plot for the n-SiNWFET. As expected, the measured results show that Ids increases with higher laser power because of the increase in the generated photocurrent, as described above. This variation becomes larger as the laser power increases, and it is more pronounced in the subthreshold region. Figures 6(a) and (b) show the VTC of the SiNW CMOS inverter consisting of n- and p-SiNWFETs for Vdd = 2 V. The inset shows the voltage gain curves with respect to each laser power. Vinv and voltage gain gradually increase with higher laser power. This indicates that the intensity of light influences the operating characteristics of the inverter. The electrical characteristics of Figs. 5 and 6 follow the same trend as Figs. 2 and 4. Therefore, the rate of EHP generation is clearly affected by the laser power as well as the wavelength.
Fig. 5 Ids-Vgs transfer curve of the SiNWFETs for Vdd = 2 V under different laser powers (black = darkness, blue = 0.4 mW, pink = 0.8 mW) of light. The fixed wavelength for p-SiNWFET is (a) 633 nm and (b) 532 nm, and the fixed wavelength for n-SiNWFET is (c) 633 nm and (d) 532 nm.
Fig. 6 Voltage transfer characteristic curve (VTC) of the SiNW CMOS inverter for Vdd = 2 V under different laser powers (black = darkness, blue = 0.4 mW, pink = 0.8 mW). The corresponding voltage gain curves are shown in the inset. The fixed wavelength is (a) 633 nm and (b) 532 nm.
4. Conclusion
In summary, we have demonstrated the performance of a SiNW CMOS inverter on a transparent substrate under laser illumination. Our device clearly showed the variation in the electrical characteristics. For each SiNW, Ion/Ioff decreased and Vth shifted toward the positive direction with shorter wavelengths and higher laser power. We also demonstrated the excellent switching characteristics of the SiNW CMOS inverter when the wavelength is decreased and the power of light is increased. In addition, we showed that light was efficiently absorbed through the transparent substrates, which enhanced the rate of EHP generation. Moreover, highly sensitive optoelectronic devices can be realized due to the voltage variation, which is extremely competitive with other devices. Our results show the potential of the SiNW CMOS to be applied in optoelectronic applications such as photosensors, photodetectors, and imaging systems.
Funding
National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIP) (NRF-2016R1E1A1A02920171, NRF-2015R1A2A1A15055437); Brain Korea 21 Plus Project of 2017; Samsung Electronics.
References and links
1. X. Gong, M. Tong, Y. Xia, W. Cai, J. S. Moon, Y. Cao, G. Yu, C.-L. Shieh, B. Nilsson, and A. J. Heeger, “High-Detectivity Polymer Photodetectors with Spectral Response from 300 nm to 1450 nm,” Science 325(5948), 1665–1667 (2009). [CrossRef] [PubMed]
2. C. H. Lin and C. W. Liu, “Metal-insulator-semiconductor photodetectors,” Sensors (Basel) 10(10), 8797–8826 (2010). [CrossRef] [PubMed]
3. G. Konstantatos, I. Howard, A. Fischer, S. Hoogland, J. Clifford, E. Klem, L. Levina, and E. H. Sargent, “Ultrasensitive solution-cast quantum dot photodetectors,” Nature 442(7099), 180–183 (2006). [CrossRef] [PubMed]
4. L. W. Lai, C. H. Lai, and Y. C. King, “A Novel Logarithmic Response CMOS Image Sensor With High Output Voltage Swing and In-Pixel Fixed-Pattern Noise Reduction,” IEEE Sens. J. 4(1), 122–126 (2004). [CrossRef]
5. Y. M. Song, Y. Xie, V. Malyarchuk, J. Xiao, I. Jung, K.-J. Choi, Z. Liu, H. Park, C. Lu, R.-H. Kim, R. Li, K. B. Crozier, Y. Huang, and J. A. Rogers, “Digital cameras with designs inspired by the arthropod eye,” Nature 497(7447), 95–99 (2013). [CrossRef] [PubMed]
6. E. Mohammed, “Optical Interconnect System Integration for Ultra-Short- Reach Applications,” Intel Technol. J. 8, 115–127 (2004).
7. A. Jain, S. K. Sharma, and B. Raj, “Design and analysis of high sensitivity photosensor using Cylindrical Surrounding Gate MOSFET for low power applications,” Eng. Sci. Technol. an Int. J. 19(4), 1864–1870 (2016). [CrossRef]
8. O. Yadid-Pecht, R. Ginosar, and Y. Shacham-Diamand, “A Random Access Photodiode Array for Intelligent Image Capture,” IEEE Trans. Electron Dev. 38(8), 1772–1780 (1991). [CrossRef]
9. A. J. Mäkynen, J. T. Kostamovaara, and T. E. Rahkonen, “CMOS Photodetectors for Industrial Position Sensing,” IEEE Trans. Instrum. Meas. 43(3), 489–492 (1994). [CrossRef]
10. W. Zhang and M. Chan, “A high gain N-Well/Gate tied PMOSFET image sensor fabricated from a standard CMOS process,” IEEE Trans. Electron Dev. 48(6), 1097–1102 (2001). [CrossRef]
11. B. Ackland and A. Dickinson, “Camera on a chip,” Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International. IEEE, 22–25 (1996). [CrossRef]
12. R. A. Soref, “Silicon-Based Optoelectronics,” Proc. IEEE 81(12), 1687–1706 (1993). [CrossRef]
13. H. S. Wong, “Technology and device scaling considerations for CMOS imagers,” IEEE Trans. Electron Dev. 43(12), 2131–2142 (1996). [CrossRef]
14. W. Zhang, M. Chan, R. Huang, and P. K. Ko, “High gain gate / body tied NMOSFET photo-detector on SOI substrate for low power applications,” Solid-State Electron. 44(3), 535–540 (2000). [CrossRef]
15. K. Ping, “A Novel High-Gain CMOS Image Sensor Using Floating N-Well/Gate Tied PMOSFET,” Electron Devices Meeting, 1998. IEDM'98. Technical Digest., International. IEEE, 1023–1025 (1997).
16. Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, L. O. Shih-Hsien, G. A. Sai-Halasz, R. G. Viswanathan, H. J. C. Wann, S. J. Wind, and H. S. Wong, “CMOS scaling into the nanometer regime,” Proc. IEEE 85(4), 486–504 (1997). [CrossRef]
17. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. P. Wong,“Device scaling limits of Si MOSFETs and their application dependencies,” Proc. IEEE 89(3), 259–288 (2001). [CrossRef]
18. M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, “Scaling, Power, and the Future of CMOS,” Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International 7–15, (2005). [CrossRef]
19. R. Courtland, “Transistors could stop shrinking in 2021,” IEEE Spectr. 53, 9–11 (2016).
20. B. Cousin, M. Reyboz, O. Rozeau, M. A. Jaud, T. Ernst, and J. Jomaah, “A unified short-channel compact model for cylindrical surrounding-gate MOSFET,” Solid-State Electron. 56(1), 40–46 (2011). [CrossRef]
21. M. Lee, Y. Jeon, M. Kim, and S. Kim, “Flexible semi-around gate silicon nanowire tunnel transistors with a sub- kT/q switch,” J. Appl. Phys. 117, 0– 8 (2015).
22. M. Lee, Y. Jeon, T. Moon, and S. Kim, “Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS Inverters on plastic,” ACS Nano 5(4), 2629–2636 (2011). [CrossRef] [PubMed]
23. J. Yun, M. Lee, Y. Jeon, M. Kim, Y. Kim, D. Lim, and S. Kim, “Nanowatt power operation of silicon nanowire NAND logic gates on bendable substrates,” Nano Res. 9(12), 3656–3662 (2016). [CrossRef]
24. Y. Kim, Y. Jeon, M. Kim, and S. Kim, “NOR logic function of a bendable combination of tunneling field-effect transistors with silicon nanowire channels,” Nano Res. 9(2), 499–506 (2016). [CrossRef]
25. M. Lee, Y. Jeon, K. Sik Son, J. Hyung Shim, and S. Kim, “Comparative performance analysis of silicon nanowire tunnel FETs and MOSFETs on plastic substrates in flexible logic circuit applications,” Phys. Status Solidi Appl. Mater. Sci. 209(7), 1350–1358 (2012). [CrossRef]
26. T. Y. Chan, A. T. Wu, P. K. Ko, and C. Hu, “Effects of the Gate-to-Drain/Source Overlap on MOSFET Characteristics,” IEEE Electron Device Lett. 8(7), 326–328 (1987). [CrossRef]
27. R. Izawa, T. Kure, and E. Takeda, “Impact of the Gate—Drain Overlapped Device (GOLD) for Deep Submicrometer VLSI,” IEEE Trans. Electron Dev. 35(12), 2088–2093 (1988). [CrossRef]
28. H. Oh, K. Cho, and S. Kim, “Electrical characteristics of a bendable a-Si:H thin film transistor with overlapped gate and source/drain regions,” Appl. Phys. Lett. 110(9), 093502 (2017). [CrossRef]
29. Y. Hu, G. Dong, C. Liu, L. Wang, and Y. Qiu, “Dependency of organic phototransistor properties on the dielectric layers,” Appl. Phys. Lett. 89(7), 072108 (2006). [CrossRef]
30. S. H. Seo, K. D. Kim, J. K. Shin, Y. Cho, H. B. Park, and P. Choi, “PMOSFET-type photodetector with high responsivity for CMOS image sensor,” Proc. IEEE ICIA 2006 - 2006 IEEE Int. Conf. Inf. Acquis. 871–876 (2006). [CrossRef]
31. Y. Y. Noh, D. Y. Kim, Y. Yoshida, K. Yase, B. J. Jung, E. Lim, and H. K. Shim, “High-photosensitivity p-channel organic phototransistors based on a biphenyl end-capped fused bithiophene oligomer,” Appl. Phys. Lett. 86(4), 043501 (2005). [CrossRef]
32. S. Y. Huang, T. C. Chang, M. C. Chen, T. C. Chen, F. Y. Jian, Y. C. Chen, H. C. Huang, and D. S. Gan, “Improvement in the bias stability of amorphous InGaZnO TFTs using an Al2O3 passivation layer,” Surf. Coat. Tech. 231, 117–121 (2013). [CrossRef]
33. K. Wasapinyokul, W. I. Milne, and D. P. Chu, “Origin of the threshold voltage shift of organic thin-film transistors under light illumination,” J. Appl. Phys. 109(8), 084510 (2011). [CrossRef]
34. Y. Hu, G. Dong, L. Wang, and Y. Qiu, “Phototransistor properties of pentacene organic transistors with poly (methyl methacrylate) dielectric layer,” Jpn. J. Appl. Phys. 45(3), L96–L98 (2006). [CrossRef]
35. S. R. Raza, Y. T. Lee, S. H. Hosseini Shokouh, R. Ha, H.-J. Choi, and S. Im, “A ZnO nanowire-based photo-inverter with pulse-induced fast recovery,” Nanoscale 5(22), 10829–10834 (2013). [CrossRef] [PubMed]
36. S. H. Im, S. J. Kwon, and E. S. Cho, “Photoelectric Effects on the Photocurrent of an a-Si : H Thin Film Transistor due to the Spectral Properties of Backlight Sources,” J. Korean Phys. Soc. 54(5(1)), 1829–1833 (2009). [CrossRef]
37. H. Kavak and H. Shanks, “Stability of hydrogenated amorphous silicon thin film transistors on polyimide substrates,” Solid-State Electron. 49(4), 578–584 (2005). [CrossRef]
38. M. L. Simpson, M. N. Ericson, G. E. Jellison, W. B. Dress, A. L. Wintenberg, and M. Bobrek, “Application specific spectral response with CMOS compatible photodiodes,” IEEE Trans. Electron Dev. 46(5), 905–913 (1999). [CrossRef]
39. K. Wasapinyokul, W. I. Milne, and D. P. Chu, “Photoresponse and saturation behavior of organic thin film transistors,” J. Appl. Phys. 105(2), 024509 (2009). [CrossRef]
40. D. Wang, B. A. Sheriff, M. McAlpine, and J. R. Heath, “Development of Ultra-High Density Silicon Nanowire Arrays for Electronics Applications,” Nano Res. 1(1), 9–21 (2008). [CrossRef]
41. B. A. Sheriff, D. Wang, J. R. Heath, and J. N. Kurtin, “Complementary Symmetry Nanowire Logic Circuits: Experimental demonstrations and in silico optimizations,” ACS Nano 2(9), 1789–1798 (2008). [CrossRef] [PubMed]
42. G. Jo, W. K. Hong, J. Maeng, M. Choe, W. Park, and T. Lee, “Logic inverters composed of controlled depletion-mode and enhancement-mode ZnO nanowire transistors,” Appl. Phys. Lett. 94(17), 173118 (2009). [CrossRef]
