1. Introduction

The relative ease of fabrication of Silicon based integrated devices, enabled by over half a century of process development, has motivated the implementation of photonics in Silicon and has yielded first promising commercial applications in the DataCom segment [1]. While initial emphasis was placed on the joint integration of CMOS electronics with photonics, diverging technology requirements in state-of-the-art electronics and photonics is now also motivating substantial efforts in 3D and hybrid integration of Silicon based electronic and photonic chips [2]. High yield, high scalability, low cost and compatibility with existing 3D integration technology, as well as performance enhancements via co-integration with selected analog electronics [3,4] make Silicon based photonics an attractive technology platform. While rapid progress has been made with the analog bandwidth of Silicon Photonics (SiP) based electro-optic (E/O) modulators with demonstrated data rates in excess of 50 Gbit/s [5], comparatively high insertion losses and high nonlinearity have restricted the application space. In long distance communications in particular, that is particularly sensitive to performance metrics such as insertion losses and linearity, Lithium Niobate remains the technology of choice for E/O modulators even though interest in SiP based solutions for complex modulation has been growing [6]. Drive voltage requirements constrain the required voltage handling capability and thus the technology choices for driver integrated circuits (ICs) and are thus a cost factor reaching far beyond modulator fabrication with consequences on the entire system architecture. Low drive voltage and low power consumption are important requirements for 3D integration with standard high performance electronics and for the realization of electro-optic systems-in-a-package, in addition to being an important performance metric for datacenter system integrators.

Depletion type phase shifters relying on the modification of the free carrier density in a reverse biased diode have been established as a mainstream approach in SiP E/O modulators [7]. They are capable of extremely high-speed modulation fundamentally limited only by their RC time constant (transit time is typically not the limiting factor). The modulation efficiency of depletion type phase shifters is a function of the number of displaced carriers with respect to the applied reverse voltage, and thus ultimately of the device capacitance (with higher capacitances resulting in higher phase shift efficiencies in terms of phase shift per volt). Moreover, the capacitance of the phase shifters depends on the depletion width of the diode and thus on the applied bias. Consequently, both their cutoff frequency and their DC modulation efficiency depend on the applied signal levels, with resulting device nonlinearities limiting their compatibility with complex modulation formats. Very highly doped pin phase shifters may improve both aspects. The modulator behaves more linearly, since depletion width and thus capacitance are stabilized with respect to the applied voltage. Moreover, the capacitance, and thus also the modulation efficiency, are increased by the high doping levels and become independently adjustable by the width of the intrinsic region interposed between the p- and n-doped regions. The major drawback consists quite obviously in high free carrier absorption losses. Conceptually, this tradeoff can be simply alleviated by restricting the high doping concentrations to the regions in the immediate proximity of the diode junction, where they determine the diode capacitance, while reducing them elsewhere in the waveguide where they cause excess waveguide losses. The difficulty resides in the practical realization of such a structure. Here we propose the fabrication of depletion type phase shifters with a combination of selective implantation and epitaxial overgrowth that allows unprecedented control over the definition of the doping profiles and thus allows breaking previously limiting design tradeoffs. Special emphasis is placed on achieving high modulation efficiency (low V_π, defined as the voltage swing required for a single phase shifter to reach π phase shift) and low power consumption, while maintaining acceptable insertion losses and high bandwidth. In addition, the proposed phase shifters feature high linearity, making them more suitable for the implementation of complex modulation formats.

In section 2, we first introduce the basic geometry of the proposed phase shifter and compare its performance metrics with the state of the art. In section 3, the fabrication of the device is described and modeled with the Technology Computer-Aided Design (TCAD) process flow simulator from Synopsys. The expected performance of the phase shifter is simulated and fabrication tolerances are compared to those of previously realized devices. Design examples of complete lumped element and travelling wave (TW) modulators relying on the proposed phase shifter are given in section 4 to validate its applicability. We investigate the linearity of the devices and their suitability to 16-point Quadrature Amplitude Modulation (16-QAM) in section 5. Finally, a comparison between the power consumption of lumped element and TW modulators is derived in the appendix, in support of the literature review reported in section 2.

2. Phase shifter concept

The DC modulation efficiency of a depletion type SiP phase shifter is determined primarily by the capacitance of the junction (determining the number of free carriers transported in and out of the waveguide as a function of the applied signal) and its overlap with the optical mode. Higher doping levels lead to a higher capacitance. However, they also result in higher free carrier absorption and thus in increased insertion losses. For example, increasing the n and p doping levels by a factor 5 in the phase shifter shown in Fig. 1(a), from n, p = 5e17 cm⁻³ to n, p = 2.5e18 cm⁻³ (both reasonable doping levels [8]) results in the effective index change Δn_eff increasing from 8e-5 to 16e-5 for a 2 V_pp reverse voltage swing (applied from 0 V to 2 V reverse bias) and optical losses increasing from 1.2 dB/mm to 7.1 dB/mm (assuming a 400 nm wide and 220 nm high waveguide, a 120 nm etch depth and a 20 nm intrinsic region width). The loss increases by a factor 6 while Δn_eff is only doubled. The two quantities scale differently, primarily because the variation of the depletion region width (ΔW_Dep) versus applied reverse voltage decreases with higher doping levels, resulting in a reduced overlap between the optical mode and the region in which the free carrier concentration and thus the refractive index are modulated. Waveguide losses on the other hand scale directly with the dopant concentrations assuming most of the waveguide to be doped. At a fixed drive voltage, trading off insertion losses against modulation depth will result in an upper ceiling to the practical carrier density in such a configuration. On the other hand, the intrinsic RC bandwidth of depletion type phase shifters scales favorably with increasing doping levels. The low doped and high doped versions of Fig. 1(a) (n, p = 5e17 cm⁻³ and n, p = 2.5e18 cm⁻³) for example have intrinsic bandwidths of respectively 35 GHz and 61 GHz, with the improvement resulting from the series resistance dropping faster than the capacitance increases.

 

Fig. 1 Schematic cross-sections of different phase shifter configurations. (a) Conventional and (b,c) modified lateral junctions with (b) narrow highly doped regions in the vicinity of the junction and (c) doping compensation at the corners of the ridge waveguide. (d,e) Vertical junctions with narrow highly doped regions in the vicinity of the junction with (d) top contacting with polycrystalline or amorphous Silicon or (e) contacting by means of the highly doped n⁺ and p⁺ layers (the proposed phase shifter). (f) Silicon-insulator-Silicon capacitive phase shifter (SISCAP). In all the diagrams n⁺⁺ and p⁺⁺ refer to very highly doped wells implemented for contacting.

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These trends suggest that the highly doped regions should be restricted to the immediate proximity of the depletion region rather than to the whole phase shifter waveguide cross-section. In the limit where the highly doped region only extends in the region that is fully depleted when the highest reverse bias voltage is applied, waveguide losses and phase shift efficiency will follow similar scaling with doping concentrations, making it possible to freely trade them off against each other without “running into a wall”. The structure shown in Fig. 1(b) represents a conceptual (if impractical) realization of this concept. As an example, if the doping concentrations are set to n⁺, p⁺ = 2.5e18 cm⁻³ within 15 nm of a 20 nm wide intrinsic region (wherein the n⁺ and p⁺ regions are sufficiently thick for the depletion region to remain confined in the highly doped regions at a reverse bias of 2 V) and the rest of the waveguide is doped with n^-, p^- = 5e17 cm⁻³, simulations predict an optical loss of 1.7 dB/mm only slightly higher than for the low doped version of Fig. 1(a) and a Δn_eff of 16e-5 identical to the one of the highly doped version of Fig. 1(a). This results in a significant improvement while maintaining a reasonable RC cutoff frequency of 23 GHz. Effectively, the unnecessarily high cutoff frequency of the phase shifter has been reduced to a practical level (23 GHz is compatible with 28 GBaud state-of-the-art signaling rates) to improve both insertion losses and modulation efficiency.

Since this structure is, as is, impractical to fabricate (it requires extremely high control over the spatial implant distribution on a nanoscopic scale out of reach from features defined by implantation), alternative implementations have to be explored. Implementing a related concept, Tu et al. [5] used a doping compensation method to reduce the carrier concentration far from the junction by reverse doping the top corners of the ridge waveguide, resulting in the structure conceptually shown in Fig. 1(c). They reported improved optical losses of ~1 dB/mm with a modulation efficiency of V_πL = 2.67 V⋅cm (defined as the product of V_π with the phase shifter length L_PS), which corresponds to Δn_eff = 5.8e-5 after rescaling for a 2 V_pp signal, and an E/O bandwidth of 25.6 GHz. This method, however, still only allows for far less control over doping profiles than would be ideally desirable.

Figure 1(d) shows a cross-section of a modulator relying on the same concept as 1(b), but with a vertical junction. This structure can be fabricated e.g. by means of epitaxial growth of an in situ doped Silicon layer stack [9]. The height of each layer can then be controlled in the range of a few nanometers, since epitaxial growth of Silicon is a relatively slow process and dopant diffusion is minimal at the growth temperature. However, the structure shown in Fig. 1(d) requires planarization of the oxide cladding followed by the deposition of poly- or amorphous Silicon to define the top contact. Polycrystalline and amorphous Silicon are suboptimum in terms of optical losses per material conductivity [10]. While partial recrystallization is in principle possible since the amorphous or poly-Silicon is grown directly on single crystal Silicon [11], it is a complex process. The Silicon-insulator-Silicon capacitive phase shifter (SISCAP) shown in Fig. 1(f) [12] suffers from similar constraints in terms of electrical connectivity.

The structure shown in Fig. 1(e) on the other hand does not require an additional poly- or amorphous Silicon layer for contacting the device, since the thin p⁺ and n⁺ layers defining the pin diode can also be used for electrical connectivity. Most of the volume of the phase shifter is left undoped. Since reliance on epitaxial growth makes integration with low loss interconnect waveguides challenging [9], we rather rely here on an epitaxial stack definition based on sequential selective implantation and epitaxial overgrowth steps, as described in details in section 3. This has the additional benefit that the capacitor defined by the overlay of the n⁺ and p⁺ regions can be restricted to the waveguide core and further freely sized to trade off modulation efficiency against bandwidth.

A side effect of the proposed configuration is enhancement of the phase shifter linearity. Since over 80% of the phase shifter is left undoped, one may increase the doping levels to very high concentrations, up to 10¹⁹ cm⁻³ (with moderate effect on waveguide losses since the doped layer thicknesses can be reduced at the same time). In the limit of very high doping, the capacitance of the waveguide is primarily determined by the intrinsic region and remains almost constant over the entire signal range. Therefore, both the differential phase shift efficiency and the phase shifter bandwidth are stabilized in respect to the applied voltage.

Interdigitated doping patterns [13–15] have been used as another means to increase the phase shifter efficiency of depletion type modulators. This doping method can very effectively increase the capacitance and the mode overlap and thus significantly reduce V_πL. Moreover, such phase shifters can be relatively straightforwardly fabricated by dopant compensation. Since the capacitance is increased while maintaining low dopant levels, these devices also perform very well in terms of V_πL versus waveguide losses. In their moderately or low doped form, they do have, however, a much reduced linearity compared to the device proposed here.

We summarize the performance of published phase shifters and compare them to our own device in Table 1. Performance metrics include the phase shift efficiency per unit length (represented by V_πL), optical loss per unit length (α in dB/mm), the intrinsic E/O bandwidth of the phase shifter as limited by the RC time constant (f_c), as well as the V_πL⋅α product corresponding to the V_π of a phase shifter whose length is sized to result in 1 dB propagation loss. Assuming V_MOD to be the drive voltage, the energy consumption per bit of a dual drive lumped element modulator operated in push-pull configuration is E_bit = 2⋅CV_MOD²/4 [16], where each of the phase shifters have a capacitance C. Since a π/2 phase shift has to be reached in each modulator arm, the drive voltage V_MOD is approximately given by V_πL/(2L_PS) (assuming a linear response). The phase shifter capacitance is given by C_L⋅L_PS, where C_L is the phase shifter capacitance per unit length. Similarly to the commonly reported drive voltage × phase shifter length product V_πL, we introduce the energy per bit × phase shifter length product given by E_bit⋅L_PS = C_L⋅(V_πL)²/8. Moreover, the analogous quantity to the V_πL⋅α product is the energy per bit of a dual drive modulator sized to result in 1 dB propagation loss given by E_bit⋅L_PS⋅α = C_L⋅(V_πL)²⋅α/8. As derived in the appendix, these power consumption metrics are also representative for a well-designed TW modulator within a factor 5 penalty. Assuming the characteristic impedance of the TW modulator can be freely chosen (e.g. by co-designing the driver in a system-in-a-package), we show the power consumption enhancement of a lumped element or segmented modulator of equal length to reach a factor 5 when the TW device bandwidth f_TW is close to the intrinsic phase shifter bandwidth f_c, and to be 6f_TW/f_c < 5 when the intrinsic phase shifter bandwidth is significantly larger than required (and the TW modulator bandwidth limited e.g. by phase mismatch or radio frequency transmission line losses). Finally, as an overall figure of merit combining energy per bit and bandwidth, we introduce FOM = f_c⋅(E_bit⋅L_PS⋅α)⁻¹ = f_c⋅(C_L⋅(V_πL)²⋅α/8)⁻¹ in the comparison table.

Table 1. Comparison of different phase shifter designs based on loss, phase shift efficiency, speed and energy per bit. The waveguide height (h) and phase shifter length (L_PS) are indicated in the second column. Reported V_πL are either averaged over an operational voltage range or reported at a fixed average voltage. Except for [23], data is reported for λ = 1550 nm.

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The first six rows of Table 1 correspond to the geometry shown in Fig. 1(a). These rows are ordered in order of increasing linear phase shifter waveguide losses (α) and decreasing V_πL. As expected, linear losses increase and V_πL decreases with increasing doping concentrations inside the phase shifter, with a few exceptions: In [18], Li et al. report a V_πL that is significantly better than expected from the general trend due to the thicker Silicon-on-Insulator (SOI) device layer, which results in a larger junction area and thus in a higher capacitance for a similarly sized mode surface. Consequently, this also results in an enhanced α⋅V_πL product. The device bandwidth (f_c) is however reduced at the same time by the increased capacitance, so that this does not necessarily result in a net enhancement of the overall device metrics, but rather in a tradeoff between V_πL and bandwidth. In [20], Wang et al. report phase shifter characteristics well in line with the other reported devices in regards to the tradeoff between V_πL and linear phase shifter losses, however the reported implant concentrations are lower than expected. This may be due to a discrepancy between targeted and actual dopant concentrations. Moreover, the reported α⋅V_πL products are generally consistently between 30 and 40 V⋅dB for phase shifters with waveguide height h = 220 nm [8,17–21]. In [22], however, Tu et al. implemented a dopant compensation at the corners of the ridge waveguide as shown in Fig. 1(c), resulting in a reduction of the waveguide losses without sacrificing other metrics (other than a slight increase in diode series resistance) and improving the α⋅V_πL product to 21 V⋅dB without compromising the device bandwidth.

While the energy per bit × modulator length product C_L⋅(V_πL)²/8 improves at higher doping levels (it roughly scales as C_L⁻¹), the energy per bit of a dual drive modulator with phase shifter lengths sized for 1 dB excess loss, C_L⋅(V_πL)²⋅α/8, only shows a slight improvement with doping levels (compare [17,19,8]). Strikingly, the ratio of the intrinsic bandwidth f_c to C_L⋅(V_πL)²⋅α/8 (the overall FOM) is within a factor 2 for all the reported phase shifters. In [19], Ding et al. progressively increase the doping outside of the waveguide by adding an additional, intermediate doping region. This allows reducing the diode series resistance at fixed waveguide losses, resulting in an improved FOM. This refinement is a well-known technique that can be applied to any of the other devices.

The nonlinearity of SiP depletion type phase shifters makes an exact comparison of device performance in terms of V_πL notoriously difficult, since the reported V_πL depends on the applied voltage range or, equivalently, on the phase shifter length if the applied drive voltage is chosen for achieving full extinction. In order to facilitate the comparison of the devices, the device length for which the drive voltage was measured has been indicated in the table for references [8,17,19–22]. At higher doping levels, with higher waveguide losses and lower V_πL, the devices naturally gravitate towards shorter lengths, with typical lengths shrinking from 4 to 2 mm as the doping concentrations are increased from 1e17 to 1e18 cm⁻³.

Since interdigitated doping profiles enable a high device capacitance at low doping levels, a low α⋅V_πL product of 17 V⋅dB was achieved in [13] by Xu et al., however at the cost of a low bandwidth resulting from the high capacitance (including non-phase shifting capacitive elements outside of the waveguide core). In a subsequent design [14], a high bandwidth of 56 GHz was recovered, but at the cost of increased waveguide losses. The FOM (summarizing the overall envelope for all the tradeoffs) remains in line with the devices discussed above.

The SISCAP phase shifter [23] features a record low V_πL of 0.14 V⋅cm at the cost of high waveguide losses (8 dB/mm at the average bias point), a reduced bandwidth (15 GHz) and a high capacitance (32 pF/cm). While the resulting power consumption metric E_bit⋅L_PS⋅α = C_L⋅(V_πL)²⋅α/8 is by far the best (6.4 pJ⋅dB/bit), in relation to the bandwidth (FOM) it is in line with that of the other modulators (compare the FOM of [23] with e.g [8]. and [19]). It should be noted that the high phase shift efficiency of the SISCAP device results from it being operated in the carrier accumulation regime, and that operating the device at a lower bias point allows dynamically trading off waveguide losses, bandwidth and phase shift efficiency to some extent (lower waveguide losses, as well as higher bandwidth and lower phase shift efficiency in the transition region to the carrier accumulation regime).

While the performance metrics reported here are quite general – the power consumption metric C_L⋅(V_πL)²⋅α/8 is applicable to both lumped element and well-designed TW modulators (i.e., devices where the choice of lumped element or TW architecture is sensical and the device design is optimized) – we are showing in the appendix that the power consumption of a TW device is actually up to a factor 5 above that of a lumped element device of identical length (or of a segmented modulator of identical length driven by a distributed driver [24,25], if the phase shifter length is too long to ignore phase mismatch). In other words, once the V_πL of the phase shifter is sufficiently small to reduce the device size to a point where a lumped element modulator can be implemented within the constraints of the available voltage driving capabilities, a substantial improvement in power consumption can be obtained. Moreover, driving a lumped element load can facilitate driver design as compared to an impedance-matched driver (for example, the SISCAP driver in [12] is a simple CMOS inverter), allowing further reduction of the power consumption. From this point of view, a low V_πL is in and by itself a beneficial characteristic that is not fully captured by the FOM f_c⋅(C_L⋅(V_πL)²⋅α/8)⁻¹.

For high-speed next generation DataCom links (25 Gbit/s and above), it is desirable to realize an intermediate phase shifter with characteristics between those of the reported SISCAP phase shifter (very low V_πL but insufficient bandwidth) and the other modulators reported in the comparison table (very high bandwidth with a number of devices reaching a cutoff frequency above 50 GHz, but relatively high V_πL). In order to reach this set of device metrics, one may attempt to take the phase shifter configuration of Figs. 1(a) and 1(c) [8,17–22] and increase the dopant concentrations. The before last row of Table 1 summarizes the results for a simulated device assuming implant levels of n, p = 2.5e18 cm⁻³ (as also discussed earlier in this section). As can be seen, a low V_πL of 0.97 V⋅cm and a high bandwidth of 61 GHz can be reached. However, for the reasons explained above, the waveguide losses hit a wall (7.1 dB/mm) resulting in a poor α⋅V_πL of 69 V⋅dB (2x to 3x worse than the other devices), poor energy per bit C_L⋅(V_πL)²⋅α/8 and the lowest FOM of all the reported devices. Changing the geometry from Fig. 1(a) to the device proposed here (as shown in Fig. 1(e)) allows trading off the excess bandwidth, which, at 61 GHz, is substantially above the required bandwidth even for next generation optical links, in order to recover better waveguide losses and better power consumption.

The performance metrics for our device, as reported in the last row of the table, are derived from a modeling of realistic doping profiles via simulation of the fabrication flow with Synopsys TCAD, followed by E/O modeling with RSoft and COMSOL Multiphysics. The predicted V_πL is the lowest of all the diode based carrier depletion phase shifters (i.e., excluding the SISCAP device), thus facilitating the implementation of lumped element or of low drive voltage devices. V_πL⋅α is in line with that of the other carrier depletion devices (for h = 220 nm) and the intrinsic phase shifter bandwidth can easily support 25 GBaud (for InfiniBand EDR) and 28 GBaud (for 100G Ethernet and 32GFC Fibre Channel) signaling rates (complete device designs with analog bandwidths of 17 GHz and 20 GHz are reported in section 4). The details of the device design and of the fabrication flow modeling are reported in the next section. It should be noted that since our device relies on a vertical junction, the trends pointed out above on the dependence of lateral junction phase shifter characteristics on film thickness do not apply here.

3. Modeling of fabrication process and phase shifter performance

The approach taken for device fabrication is to alternate local (masked) ion-implantation with epitaxial overgrowth. In this section, we focus on modeling of the fabrication process to determine the doping profiles that can be reliably fabricated in view of obtaining robust devices with acceptable sensitivity to fabrication tolerances. Ion-implantation, ion activation and thermally activated dopant diffusion during surface cleaning steps and epitaxial growth of subsequent Silicon layers are modeled with Synopsys’ TCAD software (SPROCESS package), in particular in view of dopant diffusion. The obtained doping profiles are subsequently used for E/O performance simulation of the device.

Prior to modeling the device with the actual dopant distribution resulting from the modeling of a realistic fabrication flow, we performed a preliminary design study based on idealized dopant distributions with sharp interfaces (as represented in Fig. 1(e)). This design optimization served to target the process flow of the fully modeled device. As explained in section 2, the doping levels in the p- and n-doped regions inside the waveguide are the result of a tradeoff between optical loss, modulation efficiency and E/O cutoff frequency. In addition, the height of the intrinsic region, h_int, also affects the linear capacitance, and thus the cutoff frequency and the phase shift efficiency. It also affects the linearity of the device, as h_int >> ΔW_Dep is required for a high linearity.

Optimizing a lumped element modulator for a fixed dual drive (push-pull) voltage of 2 V_pp (between 0 V and 2 V reverse bias) one may maximize Δn_eff²⋅f_c/(αC_L). The insertion losses due to free carrier absorption αL_π/2 (where L_π/2 is the phase shifter length required to obtain a π/2 phase shift) are proportional to α/Δn_eff, and the energy per bit is proportional to C_LL_π/2 and thus also to C_L/Δn_eff. The maximization of Δn_eff²⋅f_c/(αC_L) thus strikes a balance between insertion losses, intrinsic phase shifter bandwidth and power consumption. Δn_eff²⋅f_c/(αC_L) is also proportional to the FOM = f_c⋅(C_L⋅(V_πL)²⋅α/8)⁻¹ introduced in section 2 with FOM = [Δn_eff²⋅f_c/(αC_L) ]⋅32/(V_MOD⋅λ₀)² (where λ₀ is the free space wavelength of the optical carrier) and is thus a metric for the intrinsic phase shifter bandwidth divided by the overall energy per bit of a modulator sized to obtain fixed insertion losses.

We evaluated the FOM for intrinsic layer heights h_int ranging from 30 to 90 nm, optimizing for each h_int the doping levels n⁺ and p⁺, as well as the overlay of the highly doped layers. The thicknesses of the highly doped layers were fixed to h_n+ = 20 nm and h_p+ = 35 nm as we did not intend to attempt the fabrication of thinner layers. The cumulative thickness of the bottommost intrinsic region (between the underlying oxide and the p⁺ layer, see Fig. 1(e)) and of the p⁺ layer was set to 70 nm, the waveguide height and width were respectively set to 290 nm and 470 nm since these numbers resulted in good modal confinement and optical overlap. The etch defining the slab regions on the sides of the waveguide was assumed to reach the top of the n⁺ layer. Moreover, the distance between the edge of the waveguide and the onset of the highly doped contact wells was assumed to be 800 nm, chosen as a tradeoff between waveguide losses and phase shifter series resistance. Trading off phase shift efficiency for device linearity, we found h_int = 40 nm and a p⁺/n⁺ layer overlay of 250 nm to yield good results, in which case n⁺ = 6e18 cm⁻³ and p⁺ = 5e18 cm⁻³ maximizes the FOM (resulting in ΔW_Dep = 17 nm at 2 V reverse bias). This results in an intrinsic RC limited diode cutoff frequency f_c = 49.2 GHz, waveguide losses α = 3.0 dB/mm, and a capacitance per unit length C_L = 1.14 pF/mm (all at 1 V reverse bias), as well as an effective index change Δn_eff = 22e-5 for a 2 V_pp drive voltage (resulting in a V_πL of 0.70 V⋅cm).

Figure 2 shows Δn_eff for a 2 V_pp voltage swing versus donor and acceptor concentrations n⁺ and p⁺ assuming h_int = 40 nm, h_p+ = 35 nm and h_n+ = 20 nm, as well as α, f_c, L_π/2, the total loss of a phase shifter sized to achieve π/2 phase shift with a 2 V_pp drive (α⋅L_π/2) and the maximized metric Δn_eff²⋅f_c/(αC_L), all at 1 V reverse bias. The calculated −3 dBe intrinsic cutoff frequency of the phase shifter (f_c = 1/2πR_LC_L, where R_L is its series resistance length product) improves at higher doping levels, since the capacitance asymptotically converges to that of a parallel plate capacitor with electrodes spaced by a separation h_int, while the series resistance continues to drop at high doping concentrations. Δn_eff also improves at higher concentrations, while the total loss improves at lower concentrations. As explained above, the FOM strikes a balance between these quantities.

 

Fig. 2 (a) Effective index change (between 0 V and 2 V reverse bias), (b) L_π/2 derived from (a), (c) linear phase shifter loss, (d) total loss of a phase shifter sized to obtain π/2 phase shift with a 2 V_pp drive, (e) intrinsic phase shifter cutoff frequency f_c = 1/2πR_LC_L and (f) the maximized metric Δn_eff²⋅f_c/(αC_L). In all graphs the horizontal axis shows the p-doping and the vertical axis the n-doping. Crosses indicated the doping levels maximizing the FOM, as also described in the text.

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Taking the optimized idealized device as a starting point, we investigated the performance of a device obtained from a realistic fabrication flow illustrated in Fig. 3. The evaluated process starts with SOI wafers with a 2 μm buried oxide (BOX) and a 220 nm thick Silicon device layer. After thinning down the device layer to 70 nm by wet oxidation followed by wet etching in a buffered HF solution, a local Boron implantation is applied through a 10 nm scattering oxide following a corresponding lithography step with a dose of 4.5e13 cm⁻², an implantation energy of 10 keV and a 0° tilt angle. Due to the high diffusivity of Boron atoms, and due to the difficulty of forming shallow, highly implanted wells, it is crucial to start with the p-doping at the bottom of the stack. After removal of the lithography mask and of the scattering oxide, a high temperature dopant activation step is applied for 5 s at 1030°C. Next, a medium temperature pre-cleaning step (4 min at 700°C) is applied under inert atmosphere followed by an 80 nm epitaxial Silicon overgrowth performed by reduced-pressure chemical vapor deposition (CVD) for 16 min at 800°C. Disilane (Si₂H₆) is used as a precursor and deposition occurs at a rate of 5 nm/min. The temperature of the process is kept at the lower end to ensure minimal Boron diffusion. The n-doped layer is defined by local Phosphorus implantation through a 10 nm sputtered scattering oxide layer with a cumulative dose of 8e12 cm⁻² applied in two steps, respectively with 15 and 30 keV and a 0° tilt angle. Since Phosphorus is a heavier atomic species, the implantation depth of the n-doped layer can be better controlled. After removal of the lithography mask and scattering oxide and following dopant activation and surface pre-cleaning, the Silicon stack is completed by a second 140 nm Silicon epitaxial overgrowth step. The total thickness of the Silicon stack was targeted at 290 nm and was jointly optimized with the partial Silicon etch depth of 140 nm stopping at the interface to the n⁺ layer defining the 470 nm wide ridge waveguides in order to maximize mode overlap. All feature sizes, including waveguide definition, are compatible with deep UV 193 nm optical lithography. In order to provide contacts to the back-end Aluminum interconnects, highly doped wells with doping levels of 1e20 cm⁻³ are defined on either side of the waveguides by ion implantation, here too spaced 0.8 µm from the waveguide edge. Finally, 2 µm thick metal lines are fabricated using lift-off of sputtered Aluminum to form the electrical contacts.

 

Fig. 3 Fabrication flow of the proposed phase shifter.

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Figure 4(a) shows the simulated dopant profile inside the phase shifter calculated by TCAD. This dopant profile is exported to COMSOL in order to calculate the free carrier concentrations using the drift-diffusion and Poisson equations, with results shown in Fig. 4(b). The latter are then converted into an effective index change based on the overlap with the optical mode shown in Fig. 4(c).

 

Fig. 4 (a) Realistic dopant distributions inside the phase shifter as simulated by TCAD, (b) free carrier distributions inside the phase shifter resulting from the realistic dopant distribution and (c) optical field profile of the guided mode. In (a) positive concentrations represent n-doping and negative concentrations p-doping.

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Average doping concentrations of 6e18 cm⁻³ and 7e18 cm⁻³ are respectively obtained for p- and n-doped regions over thicknesses h_p+ = 40 nm and h_n+ = 15 nm, with an intrinsic layer thickness h_int = 40 nm (defined as the region with dopant concentrations below 1e16 cm⁻³), reasonably close to what was initially targeted. The p-doped layer is thicker than initially targeted due to the difficulty of obtaining shallow Boron implantation and due to the high diffusivity of Boron atoms. The increased p-doped region width and peak dopant concentrations result in increased waveguide losses (4.2 dB/mm at 1 V reverse bias) as compared to the idealized device with abrupt dopant profiles described above. Moreover, the p- and n-dopant concentrations respectively drop from 6e18 cm⁻³ and 7e18 cm⁻³ to 1e16 cm⁻³ over 10 nm and 6 nm wide intermediate regions, the effect of both of which is to reduce the junction capacitance and increase V_πL by a few percent (1 pF/mm at 1 V reverse bias and 0.74 V⋅cm averaged over 0 to 2 V reverse bias).

Figure 5 shows the voltage dependent characteristics of the modeled phase shifter. The capacitance of the phase shifter is reduced by less than 17% for voltage levels varying from 0 V to 2 V reverse bias (from 1.16 pF/mm at 0 V to 0.97 pF/mm at 2 V reverse bias), resulting in low nonlinearities. The series resistance of the phase shifter also slightly increases with increasing reverse bias due to the partial depletion of the doped regions (from 3.0 mΩ⋅m at 0 V to 3.3 mΩ⋅m at 2 V reverse bias), stabilizing the intrinsic RC cutoff frequency of the device by partially compensating for the decreasing diode capacitance (Fig. 5(b)). Suppressing both dynamic and static nonlinearities is of importance for state-of-the-art long haul communications with complex modulation formats, as will be discussed in section 5.

 

Fig. 5 DC characteristics and bandwidth of the ion-implanted phase shifters: (a) Series resistance (green curve) and capacitance (blue curve), (b) RC limited intrinsic cutoff frequency, (c) optical insertion loss, and (d) effective index change versus applied reverse bias.

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Sensitivity of the device performance to misalignment of the doping layers relative to the waveguide and relative to each other is of crucial importance to assess device manufacturability. A detailed study by Gardes et al. [26] showed that conventional lateral phase shifters are very sensitive to the misalignment of the doping layers, with a misalignment of 150 nm increasing V_π by a factor 3 in the reported phase shifter. Figure 6(b) shows the simulated sensitivity to misalignment of the doped layers of both a lateral junction phase shifter and of the proposed ion-implanted vertical diode phase shifter. The misalignment is defined as the displacement of the n-layer in the direction perpendicular to the waveguide axis, wherein the displacement of the p-layer is assumed to occur by an equal amount in the opposite direction (i.e., the width of the intrinsic layer in the lateral phase shifter and the overlay between the n⁺ and p⁺ layers in the vertical phase shifter vary by twice the amount; note that overlapping as well as disjoint n- and p-doping layers lead to an increased intrinsic region in the case of the lateral phase shifter due to implant compensation in the former case). As shown in Figs. 6(b) and 6(c), for the vertical phase shifter (solid lines) 50 nm misalignment results in a modification of the modulation efficiency by less than 20%, while it results in a reduction of the modulation efficiency by 40% for the lateral phase shifter. It should be noted that an increase of the effective index change, as seen for the vertical phase shifter for negative misalignment, can be as detrimental as its reduction, since it is accompanied by a change of the junction capacitance reducing the intrinsic phase shifter bandwidth, as well as increasing transmission line losses in a TW device.

 

Fig. 6 Sensitivity of the modulation efficiency to misalignment of the doping layers. (a) Schematic of the lateral (up) and vertical (down) junction phase shifters. Zero misalignment is defined as zero gap and 250 nm overlay, respectively for lateral and vertical junction phase shifters. (b) Effective index change versus misalignment for a 2 V_pp drive signal and (c) percent change of the effective index change relative to the nominal value versus misalignment. In all curves, equal p- and n-doping concentrations are assumed, as labeled in the legend (in units of cm⁻³).

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4. Electro-optic modulator designs

In order to illustrate the device performance that can be obtained with the proposed phase shifter, we evaluate complete device designs for both lumped element and TW Mach-Zehnder Modulators (MZM), with special emphasis placed on obtaining relatively low drive voltages. Due to the low V_πL of the proposed phase shifter, compact modulators behaving as lumped elements can be designed while maintaining reasonable drive voltages. As described in the appendix, lumped element modulators can have superior power consumption by up to a factor 5 compared to well-designed TW devices. Furthermore, unlike long TW devices, the cutoff frequency of short lumped element modulators is in principle only limited by the RC time constant of the phase shifter 1/2π(R_L + R_Dri)C_L (also taking into account the output impedance of the driver, R_Dri) due to negligible internal radio frequency (RF) losses, with longer lumped element devices also limited by phase mismatch.

The main limitation of lumped element modulators arises from their small phase shifter lengths, which require use of higher bias voltages to achieve full extinction. In order to mitigate this to some extent we are proposing a meandered device that extends the waveguide length while remaining lumped element from an electrical perspective. The second device example is a comparatively long TW modulator, which results in smaller drive voltage requirements, but also in a reduced bandwidth limited by transmission line losses. A careful transmission line design is required in order to provide phase matching and to minimize RF losses [17]. Finally, a simple straight lumped element modulator is described as a baseline for comparison.

4.1. Meandered lumped element modulator

Figure 7(a) shows the layout of the investigated meandered lumped element modulator with a phase shifter length of 900 µm in each arm collapsed into a 260 μm device length. Metal extensions relay the electrical signal from the main electrodes to regions within the meanders, in which the signal is further conducted to the phase shifters by means of the implanted wells. Prior to each waveguide bend, the partially etched waveguides of the phase shifter sections are transitioned to fully etched waveguides by means of a 5 μm long tapered transition designed to have less than 0.02 dB losses per transition even in the presence of 50 nm overlay error between the partial and full etches (see inset of Fig. 7(a)), resulting in small excess losses on the order of 0.5 dB for the full device. The full etch allows compact bends with a 10 μm radius, which is particularly important here due to phase mismatch bandwidth limitations related to the total waveguide length inside the phase shifter.

 

Fig. 7 (a) Layout of the meandered lumped element modulator, (b) lumped element circuit model, (c) E/O frequency response of the device. The inset in (a) shows a detailed view of the waveguide transitions between shallow and deeply etched regions.

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From an electrical perspective, the device is compact enough to behave as a lumped element (as confirmed with RF modeling with Ansoft HFSS consisting in simulating the amplitude and phase of the RF signal along the phase shifter). On the other hand, the waveguide length is long enough for the absence of phase matching to play a significant role in limiting the device bandwidth. The general formula for the frequency dependence of the device’s E/O response (in the absence of RC time constant limitation treated as a separate pole) is given by [27]

The assumption of lumped element operation was verified with HFSS: The RF wavelength in the device, along the main electrode axis, is 2.24 mm at 20 GHz (the cutoff frequency of the device), 8.6 times larger than the device length. In order to further improve lumped element operation, the device can be contacted in the middle of the electrodes halfway along the device length. For a phase shifter length of L_PS = 900 μm, Eq. (2) results in a phase-mismatch limited bandwidth of 40 GHz. Combined with the RC bandwidth limitation, this results in a total device bandwidth of 20 GHz (12 GHz) derived by cascading the two corresponding filters, respectively assuming a lumped element driver with a 4 Ω (10 Ω) output resistance. The drive voltage required for reaching full extinction is 4.2 V_pp for each arm (differential signaling from 0 V to 4.2 V reverse bias), the insertion losses due to free carriers are 3.8 dB, the total device capacitance is 936 fF, and the series resistance of the device is 3.5 Ω. The metal contacts are assumed to be sputtered Aluminum with a thickness of 2 μm.

4.2. Travelling wave modulator

In order to further reduce the required drive voltage, we also designed a TW modulator based on the same phase shifter. Longer phase shifters enabled by phase matching reduce the drive voltage required to obtain full extinction. However, challenges such as maintaining phase matching, bandwidth reduction due to RF losses in the transmission line and increased optical loss in longer phase shifters have to be addressed. Since the RF wave is slowed down by the capacitive load generated by the waveguide [17,28], a mechanism has to be provided to also slow down the optical field when waveguides have a high capacitance per unit length, as is the case here. Periodically spaced optical delay lines increase the optical length in order to compensate for the velocity mismatch, as shown in Figs. 8(a) and 8(b). The total length of the phase shifter sections is 1.6 mm in each arm, consisting in four discrete sections interspaced by 280 µm long recovery loops (excluded from the aforementioned length, i.e., 1.6 mm corresponds to the cumulative length of the active phase shifter sections alone). At both ends of the recovery loops, waveguide transitions convert the shallow etched waveguides from the phase shifter sections into the fully etched waveguides of the recovery loops, similarly to the transitions implemented in the meandered lumped element device described above. A segmented transmission line with electrode extensions (spaced by 15 μm) is used in order to reduce the series resistance to the waveguide while allowing for the relatively wide electrode spacing (20 μm) required to reach a 25 Ω characteristic impedance (as described in details in [8,17]).

 

Fig. 8 (a) Layout of the TW device, (b) detailed view of the recovery loops used to obtain phase matching and (c) RF effective index of the transmission line as a function of frequency.

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The characteristic impedance of the transmission line is shown in Fig. 9(a). Since 50 Ω RF systems are the most common, a transmission line with a 50 Ω characteristic impedance is also a typical design target. However, for high linear waveguide capacitances, obtaining a large characteristic impedance is challenging and requires a large electrode spacing [8]. Moreover, decreasing the transmission line impedance, while increasing the power consumption of the device, also reduces the RF losses per unit length in the transmission line and enables longer devices for a given E/O bandwidth [17]. For these reasons we opted for a 25 Ω impedance target (per MZM branch, i.e., each of the dual drives are 25 Ω). This resulted in a 17 GHz E/O bandwidth, 6.7 dB insertion losses and a required drive voltage of 2.3 V_pp (0 V to 2.3 V reverse bias) to reach full extinction. It should be noted that while a longer modulator (4.2 mm long phase shifters) with a higher bandwidth (35 GHz) has been recently demonstrated by Samani et al. in [29] with a moderate drive voltage (8 V in single drive configuration and thus slightly below 4 V in dual drive configuration), the bandwidth of our device is ultimately limited by the very low targeted drive voltage (2.3 V). The latter results from the large junction capacitance, that in turns results in high frequency dependent transmission line losses. This enters the general trade-off between cutoff frequency, insertion losses and required drive voltage explained in the previous sections.

 

Fig. 9 (a) Characteristic impedance of the loaded transmission line and (b) RF loss per transmission line unit length as a function of RF modulation frequency.

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4.3. Straight lumped element modulator

The high phase shifter efficiency enables very compact, high bandwidth modulators based on a straight lumped element phase shifter. Here we consider a MZM with 250 μm long, slightly modified phase shifters in that the n⁺/p⁺ layer overlay was increased from 250 nm to 310 nm and the distance between the waveguide edge and the n⁺⁺/p⁺⁺ wells reduced from 800 nm to 550 nm. This results in a higher linear capacitance of 1.25 pF/mm, a decreased series resistance of 2.66 mΩ⋅m and the same intrinsic phase shifter bandwidth (48 GHz), all specified at 1 V reverse bias as for the previous configuration of the phase shifter. The phase shifter efficiency (V_πL = 0.6 V⋅cm) is slightly enhanced by the increased overlay in order to accommodate such a small device, at the cost of increased waveguide losses (6 dB/mm). The device has a total bandwidth of 34 GHz assuming a 4 Ω driver (taking into account the RC time constant and phase mismatch according to Eq. (2), as for the meandered MZM) and requires a 12 V_pp dual drive signal (0 V to 12 V reverse bias) in order to achieve full extinction. Due to the short length of the device, it remains lumped element even up to 35 GHz (the device length is 6 times smaller than the RF wavelength in the device, 1.53 mm at 35 GHz as determined by HFSS). Here too, lumped element operation of the device can be further improved by contacting the electrodes in the middle, halfway along the length of the phase shifter.

Table 2 summarizes the characteristics of the three devices. Assuming the analog bandwidth of the modulator (in GHz) to be 70% of the Baud rate (in GBaud), the TW MZM, meandered lumped element MZM and straight lumped element MZM are respectively compatible with 25 GBaud, 28 GBaud and 50 GBaud signaling.

Table 2. Characteristics of the TW and the lumped element modulators using the proposed vertical phase shifters.

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5. Linearity and constellation diagram for 16-QAM

In this section we evaluate the effect of phase shifter nonlinearity on the distortion of a 16-QAM constellation diagram and the resulting reduction in demodulated eye openings. The 17 GHz bandwidth TW modulator reported in Table 2 is benchmarked and compared to a 17 GHz bandwidth TW modulator based on a typical lateral junction phase shifter reported by Sharif et al. in [8].

We assume that a MZM based IQ modulator (Fig. 10(a)) is driven with a sufficiently large voltage swing (between 0 V and a maximum reverse bias V_π) to reach a π phase shift in either of its 4 arms, in which case the outer corners of the optical constellation diagram are fixed irrespectively of the phase shifter nonlinearity. As a first metric for the phase shifter nonlinearity, we assume that the applied phase at a voltage V_π/2 (≠V_π/2) is π/2 + Δφ, where Δφ is an additional phase resulting from the nonlinearity of the phase shifter as shown in Fig. 11(a). Furthermore, we assume that the phase shifter nonlinearity is dominated by the quadratic term (as confirmed for the benchmarked devices) and that the applied phase can be described by k₁V-k₂V², where k₁ is the small signal phase shifter response at 0 V and V is a reverse bias voltage expressed as a positive number. Δφ is essentially the integral nonlinearity (INL) of the phase shifter over the voltage range 0 V to V_π. Assuming the applied in-phase (I) and in-quadrature (Q) 4-level pulse amplitude modulated (PAM-4) signals to have equally spaced voltage levels 0, V_π/3, 2V_π/3 and V_π (Fig. 10(b)), the resulting symbols are

 

Fig. 10 (a) Diagram of an IQ modulator with two pairs of phase shifters each operated in push-pull configuration and a static π phase shift applied to one of the complementary arms, (b) eye diagram of one of the applied 28 GBaud PAM-4 signals, (c) constellation diagrams in the optical domain assuming infinite modulator bandwidth for different phase shifter INLs Δφ and (d) constellation diagram in the optical domain for Δφ = 0.37 rad, a modulator bandwidth of 17 GHz and 28 GBaud signaling. The black dots in (d) show the ideal constellation diagram only taking the cosine transfer function of the MZM into account. The rotations of the individual symbols under the effect of Δφ are indicated by arrows in (c).

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The assumption of equally spaced voltage levels done here leads to suboptimum symbol spacing in the optical domain even in the absence of (second-order) phase shifter nonlinearity due to the odd order (third-order and above) nonlinearities of the MZM cosine transfer function. The voltage levels can be adjusted to compensate for the latter by changing the equally spaced voltage levels (0, V_π/3, 2V_π/3, V_π) into (0, V_π⋅acos(1/3)/π, V_π⋅[1−acos(1/3)/π], V_π). Intersymbol distances are derived for both scenarios in the following, evaluating the penalty of the residual second-order phase shifter nonlinearity in both cases.

After computation of the distorted optical constellation diagrams, we determine for each case the optimum global rotation maximizing the contrast between the PAM-4 signal levels after projection on the I and Q axes. This rotation operation is equivalent to optimizing the phase of the local oscillator (laser) used for demodulation. After projecting the data on the axes, we extract the worst case intersymbol distance for any of the signal levels, i.e., the inner optical modulation amplitude (OMA), and plot it as a function of Δφ. This is shown in Fig. 11(b) for both infinite and finite (17 GHz, 28 GBaud) modulator bandwidths, as well as for equally spaced voltage levels and voltage levels adapted to cancel the odd order MZM nonlinearities arising from the cosine transfer function. As seen in the figure, the inner OMA drops to zero for INLs between 0.84 rad (equally spaced voltage levels) and 0.88 rad (odd order nonlinearities corrected) for the bandwidth limited IQ modulator. In the absence of bandwidth limitation, the tolerance to phase shifter nonlinearity increases to an INL of 0.95 rad (equally spaced voltage levels) and 1.06 rad (odd order nonlinearities corrected).

 

Fig. 11 (a) Phase shift versus the applied reverse voltage and the corresponding INL Δφ for the lateral (Δφ_L) and vertical (Δφ_V) phase shifters, as given by the deviation at V_π/2 from the linearized phase shift represented by the dashed lines. The inset shows Δn_eff versus the applied reverse voltage. (b) Inner OMA as a function of the phase shifter INL Δφ. The inner OMA is given as a fraction of the total (outer) OMA of an undistorted constellation diagram, with 1/3 being the theoretical maximum.

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Since the inner OMA is a direct function of the phase shifter INL Δφ, as defined above, it is a convenient quantity to assess the effect of the nonlinearity on complex modulation. It should however also be related to the metrics commonly used to specify the characteristics of phase shifters, such as the small signal response and the second order intercept point (IIP2 when referred to the input signal level, i.e., the input voltage). Defining the IIP2 second order intercept point as the input signal level at which the 2^nd harmonic intermodulation reaches the same level as the linear response of the phase shifter, one obtains IIP2 = k₁/k₂ and

The parameters for the TW modulator reported in Table 2 (the vertical junction modulator) are k₁ = 0.751 rad/V and k₂ = 0.0294 rad/V². This results in IIP2 = 25.5 V, V_π = 5.3 V and Δφ = 0.21 rad. The lateral junction TW modulator reported in [8] (see the high capacitance device in Table 1 of [8]) has similar characteristics in that it also has a cutoff frequency of 17 GHz and comparable insertion losses (6.5 dB vs. 6.7 dB calculated here). The effective nonlinearity of its phase shifters is however much larger: Its phase shifters’ characteristics are given by k₁ = 0.574 rad/V and k₂ = 0.0259 rad/V², resulting in IIP2 = 22.1 V, V_π = 10 V and Δφ = 0.65 rad. Even though the IIP2 levels are similar for the two phase shifters, the reduced driving range required for the vertical junction modulator results in a three times lower INL Δφ. Correspondingly the penalty introduced by the distortion of the constellation diagram is much higher. As can be seen in Fig. 11(b), in the case of equally spaced voltage levels and a 17 GHz bandwidth IQ modulator, the inner OMA drops from 0.2 (no phase shifter nonlinearity) to 0.15 for the vertical junction modulator and to 0.044 for the lateral junction modulator. Even in the case of corrected voltage levels compensating the cosine transfer function of the modulator (odd order nonlinearities) the lateral junction modulator has a significant distortion penalty: the inner OMA drops from 0.25 (no phase shifter nonlinearity) to 0.21 for the vertical junction modulator and to 0.075 for the lateral phase shifter modulator.

6. Conclusions

We have introduced a novel method for precisely engineering the dopant distribution in vertical junction depletion type Silicon photonics phase shifters based on a combination of epitaxial growth and selective implantation. This enables high modulation efficiencies as well as high linearity sufficient to support complex modulation formats such as 16-QAM with much reduced distortion penalties. Short devices behaving as lumped elements as well as longer travelling wave modulators using the proposed phase shifters were modeled and benchmarked for 16-QAM modulation. A fundamental comparison of the power consumption of travelling wave and lumped element modulators can be found in the appendix.

Appendix Comparison of the power consumption of lumped element and travelling wave Silicon photonics modulators

The argument is often made that lumped element devices have superior power consumption than TW devices since they do not have a termination resistor constantly dissipating power, but rather only dissipate power when switched. TW modulators on the other hand “recycle” the drive signal over the entire length of the modulator, allowing for very long and efficient devices in the absence of RF and optical losses, so that the comparison is not as straightforward. Even though lumped element modulators only consume power when a bit is switched, the impact on power consumption remains moderate since on average data is switching 50% of the time. Here we show that the length × energy per bit product E_bit⋅L_PS = C_L⋅(V_πL)²/8 introduced in section 2 applies to both lumped element and well-designed TW modulators, with a power consumption penalty below a factor 5 applied to the TW device, provided the characteristic impedance of the TW modulator can be freely chosen by adapting the MZM’s transmission line geometry and co-designing the driver.

The energy consumption per bit and per MZM arm for a SiP lumped element modulator is CV_MOD²/4 [16] where C is the total capacitance of the phase shifter and V_MOD is the drive voltage. The factor ¼ is due to the fact that the capacitor loads and unloads at most once every two bits and that transitions occur on average 50% of the time. The power consumption per MZM arm of a TW modulator on the other hand is given by V_MOD²/2Z₀, where Z₀ is the characteristic impedance of a single modulator arm. The factor ½ arises from assuming a push-pull configuration, in which one of the two arms is always in the high-voltage state and the other in the low-voltage state, exactly halving the power consumption per arm assuming the low voltage state to be zero, i.e., the voltage bias to be V_MOD/2.

The signal attenuation along the transmission line of a SiP TW modulator can be approximated as being primarily determined by RF losses associated with power dissipation within the series resistance of the waveguide. Neglecting the typically much smaller RF losses arising from the resistance of the metal lines, the RF losses can be described by [17,28]

(5)$$\frac{dV}{dz}=-\frac{1}{2}\frac{{\omega }^2{C}_L{}^2{R}_L{Z}_0}{1+{\left(R_L{C}_L\omega \right)}^2}V=-\frac{1}{4}{\omega }_c{}^2{C}_L{}^2{R}_L{Z}_{0}V$$

where V is the voltage across the phase shifter, ω is the angular modulation frequency, C_L is the capacitance per unit length and R_L is the series resistance length product of the phase shifter. The denominator on the right side of the first equality corresponds to screening of the capacitive waveguide load at high RF frequencies due to the finite RC time constant of the phase shifter. The second equality is taken at ω_c = 1/R_LC_L, the intrinsic −3 dBe E/O bandwidth of the phase shifter. Assuming the length of the TW modulator to be limited by RF losses and to be 74% of the 1/e decay length of the RF voltage at ω_c, the total RF propagation loss of the transmission line is −6.4 dBe, the expected RF loss in TW modulators at the E/O −3 dBe cutoff frequency when the latter is primarily limited by transmission line losses. Since the TW modulator bandwidth suffers in reality from both the intrinsic phase shifter cutoff and from RF transmission line losses, the actual bandwidth of the device is reduced and is close to ω_TW = 0.6/R_LC_L (as determined with a numerical model, an approximation as a filter with two poles each located at ω_c = 1/R_LC_L results in ω_TW = 0.64/R_LC_L). Since the bandwidth of a transmitter is typically required to be 70% of the data rate (in order for a transmitter – receiver pair to have an aggregate bandwidth close to the Nyquist frequency if the bandwidth requirements are equally allocated to the two ends of the link), we can assume the maximum data rate supported by the TW device to be D = 0.86/2πR_LC_L.

The modulator length is then given by

(6)$$L_{PS}=0.74\frac{4}{{\omega }_c{}^2{C}_L^2{R}_L{Z}_0}=\frac{2.96}{{\omega }_c{C}_{L}Z{}_0}$$

The power consumption per arm of a lumped element modulator of equal length (and thus having identical insertion losses and drive voltage) and at the data rate D is then given by

(7)$$P=\frac{1}{4}D{C}_L{L}_{PS}{V}_{MOD}{}^2=0.74\frac{D{V}_{MOD}{}^2}{{\omega }_c{Z}_0}=0.2\frac{V_{MOD}{}^2}{2Z_0}$$

In other words, the power consumption of a hypothetical lumped element modulator of equal length (and thus equal insertion losses) is ~5 times better than that of the TW modulator. While this is a substantial improvement, it remains within one order of magnitude. In other words, the length × energy per bit product C_L⋅(V_πL)²/8 introduced in section 2 is also relevant for TW modulators, within a factor 5 penalty.

A number of assumptions have entered this derivation that need to be critically discussed. For one, the equivalent lumped element modulator is only “hypothetical”, since it might be too long to ignore phase matching requirements, so that in reality a TW modulator might have a superior power consumption compared to the longest allowable lumped element modulator (i.e., the figure of merit C_L⋅(V_πL)²⋅α/8 is only significant for a lumped element modulator if the length 1/α is short enough to not excessively limit the bandwidth). However, a segmented modulator combined with a distributed driver can meet the power consumption of the hypothetical lumped element modulator while maintaining phase matching [24,25], so that the derived penalties remain a good baseline for comparison.

On the other hand, if the length of the modulators is primarily limited by waveguide losses, the RF wave will not substantially decay before reaching the end of the TW modulator and a large portion of the RF power will be dissipated in the termination resistor even at maximum operation speed. In that case the TW modulator will have a higher transmission line losses limited bandwidth than required and will have an energy consumption per bit penalized by a higher factor than predicted above (this is a situation where the bandwidth of the TW modulator is primarily limited by the intrinsic phase shifter bandwidth and the length of the modulator limited by waveguide losses). This can be remedied by increasing the impedance of the loaded transmission line (also increasing the RF losses as seen in Eq. (5)) until the 1/e decay length of the RF voltage is commensurate with the 1/e decay length of the light and the TW modulator bandwidth is once again limited by the transmission line losses. This can for example be achieved by increasing the distance between the metal electrodes or by using slotted electrodes [17,8]. The RF power consumption is then reduced due to the higher impedance, until it matches the power scaling derived above. While this requires being able to freely choose the transmission line impedance, this may be a practical design target if driver and modulator are co-designed for a system-in-a-package solution with short electrical paths between driver and modulator (or if the impedance of intermediate circuit board transmission lines can be matched). Other design parameters can also be adjusted to converge on a reasonable design with a 25 Ω or 50 Ω characteristic impedance, i.e., with the phase shifter characteristics (C_L, R_L) retargeted for the TW MZM transmission line losses to satisfy the above criterion.

Another assumption that entered the analysis was the intrinsic bandwidth of the phase shifter to be on the same order as the bandwidth of the TW device (i.e, the −6.4 dBe transmission line losses and the intrinsic −3 dBe roll off of the phase shifter were assumed to occur at the same frequency). This is the same as assuming the RC limited bandwidth of the lumped element phase shifter not to be over-performing relative to the targeted data rate. If we assume on the other hand that the intrinsic bandwidth of the phase shifter is significantly higher than required for the targeted TW operation (as is for example the case for the TW modulator presented in Table 2), the power consumption enhancement associated with a lumped element or segmented modulator will be smaller than the predicted factor 5. We can derive an analytical expression in the case of a highly over-performing intrinsic phase shifter bandwidth by making a couple of adjustments. Equation (5) converts into

(8)$$\frac{dV}{dz}=-\frac{1}{2}\frac{{\omega }^2{C}_L{}^2{R}_L{Z}_0}{1+{\left(R_L{C}_L\omega \right)}^2}V\approx -\frac{1}{2}{\omega }_{TW}{}^2{C}_L{}^2{R}_L{Z}_{0}V$$

where ω_TW is the cutoff frequency of the TW device (as limited by transmission line losses) and the right side of Eq. (8) is taken at ω = ω_TW under the assumption that the capacitive load remains completely unscreened. The length of the TW modulator’s phase shifters is then

(9)$$L_{PS}=0.74\frac{2}{{\omega }_{TW}{}^2{C}_L^2{R}_L{Z}_0}$$

Note that when evaluated at ω_TW = 0.6ω_c this length is a factor 1.4 larger than predicted by Eq. (6) due to the different assumptions (halving of the length due to higher RF losses in the absence of screening is overcompensated by the evaluation of the transmission line losses at the actual TW device cutoff frequency ω_TW - since there are no other bandwidth limitations in this case - rather than at the higher frequency ω_c due to the additional low pass filtering by the RC filter in the former case). This discrepancy is due to the fact that Eq. (9) is only valid for ω_TW <<0.6ω_c while Eq. (6) is valid for ω_TW ~0.6ω_c. The power consumption per arm of a lumped element modulator of equal length and at the maximum data rate supported by the TW modulator D = ω_TW /(2π∙0.7) is then derived as

(10)$$P=\frac{1}{4}D{C}_L{L}_{PS}{V}_{MOD}{}^2=0.28\frac{V_{MOD}{}^2}{2Z_0}\frac{0.6}{{\omega }_{TW}{R}_L{C}_L}$$

The additional factor 0.6/ω_TWR_LC_L is equal to 1 under the previous assumptions (ω_TW = 0.6ω_c) and larger than 1 if the phase shifter cutoff frequency is higher than required. In this case, the power consumption reduction for lumped element or distributed driver modulators is smaller than the previously predicted factor 5 and can be estimated as 6ω_TW/ω_c for ω_TW <<0.6ω_c .

We can use the device characteristics described in section 4 in order to verify the predicted trends. The total energy per bit (i.e., for both arms) of the meandered lumped element modulator is 7.9 pJ/bit, while the total energy per bit for the TW device, assuming a bit rate of 17 GHz/0.7 = 24 Gbit/s, is 8.8 pJ/bit. The length × total energy per bit product is 7.1 pJ⋅mm/bit for the meandered lumped element modulator (slightly higher than the 6.8 pJ⋅mm/bit reported in Table 1 due to the higher drive voltage required to reach a π/2 phase shift resulting from the slightly shorter phase shifter length, combined with the slight nonlinearity of the diode phase shifter) and 14 pJ⋅mm/bit for the TW modulator. The power consumption reduction factor for the lumped element modulator, after correction for device length, is thus 2.1 and is significantly smaller than 5 due to the high intrinsic phase shifter bandwidth (48 GHz) compared to the cutoff frequency of the TW device (17 GHz) limited much earlier by RF transmission line losses. In this case Eq. (10) should be applied instead, with a predicted power consumption improvement factor 6ω_TW/ω_c=2.1, which is on par with the enhancement factor extracted from the device characteristics.

In addition to comparing the energy per bit of a lumped element to a TW device, one may also investigate the enhancement of the device bandwidth per energy per bit ratio for devices of equal length. Assuming that the bandwidth of the lumped element device is the intrinsic bandwidth of the phase shifter (i.e., assuming no phase matching bandwidth limitation in a very short or segmented device, as well as an idealized zero driver output impedance), this enhancement is 5/0.6~8 in the first derivation (−6.4 dBe transmission line losses occurring at ω_c, i.e., ω_TW ~ 0.6ω_c) and 6 in the second derivation (ω_TW << 0.6ω_c). In reality, the enhancement is lower, since the lumped element bandwidth is always limited by the driver output impedance as well as by additional parasitic effects, such as for example the inductance of wire bonds. For example, comparing again the TW and meandered lumped element MZMs reported in section 4, the enhancement of the device bandwidth per energy per bit ratio is 2.5, more than a factor 2 smaller than the expected factor 6, due to the reduction of the lumped element device bandwidth resulting from the driver output impedance (20 GHz versus the intrinsic 48 GHz).

Since we derived the enhancement factors in two limits, it is conducive to also show the intermediate cases derived from a numerical model (Fig. 12). Here too, the derivation was made under the assumptions that (i) transmission line losses are dominated by ohmic losses associated to the series resistance of the phase shifter and RF losses occurring inside the metal lines are neglected (ii) phase matching is not a limiting factor for the lumped element or segmented modulator combined with a distributed driver. For the device bandwidth per energy per bit enhancement, it is further assumed that (iii) the driver ouput impedance is zero, making this second curve an upper limit rather than an actual enhancement. Furthermore, it is assumed that the compared TW and lumped element devices have the same length, and thus the same insertion losses (equivalently, the improvements are respectively for the energy per bit × device length product and the ratio of the bandwidth to the energy per bit × device length product). The grayed out area for f_TW/f_c > 0.6 corresponds to TW devices for which the bandwidth is primarily limited by the phase shifter, with transmission line losses playing only a very small role. As explained above, these devices have a high power dissipation that can be reduced by retargeting the characteristic impedance of the transmission line. Under assumptions (i), (ii) and (iii), the represented enhancements are universal curves relative to f_TW/f_c independently of the specificities of the phase shifters. However, to better exemplify the dependence of f_TW/f_c and thus of the enhancements on device length (longer devices result in higher transmission line losses and thus in a lower f_TW/f_c), we have also indicated a corresponding numerical example of device lengths (upper y-axis) based on the proposed phase shifter (the length 1.6 mm corresponds to the TW device reported in section 4). As expected, the power enhancement factor for lumped element modulators drops for longer devices, as the TW device becomes more power efficient (the RF signal is “recycled” over longer distances). In this specific example, the crossover between segmented and TW devices actually occurs at a device length of ~8 mm at which f_TW drops to 8 GHz and 6f_TW/f_c = 1.

 

Fig. 12 Enhancement of the energy per bit and the device bandwidth per energy per bit ratio for a lumped element modulator relative to a TW modulator of equal length as a function of f_TW/f_c. The upper y-axis shows the corresponding phase shifter lengths assuming the characteristics of the phase shifter reported in section 3 (last row of Table 1). The dashed black curve corresponds to 6f_TW/f_c and to the asymptotic limit of the model for small f_TW/f_c.

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Acknowledgments

The authors would like to acknowledge support by the European Research Council (ERC) for project “Frontiers of Integrated Silicon Nanophotonics in Telecommunications” (contract no. 279770), by the European Union’s Seventh Framework Programme (contracts no. 293767 and 619591) and by the German Ministry for Research and Education (BMBF) for the CELTIC + project “Safe and Secure European Router” (contract no. 16BP12504).

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