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A compact waveguide-integrated Germanium-on-insulator (GOI) photodetector with 10 ± 2fF capacitance and operating at 40Gbps is demonstrated. Monolithic integration of thin single-crystalline Ge into front-end CMOS stack was achieved by rapid melt growth during source-drain implant activation anneal.
©2010 Optical Society of America
1. Introduction
Optical interconnects integrated with complementary metal-oxide-semiconductors (CMOS) are becoming attractive for achieving communication bandwidth well beyond terabit-per-second for both on-chip and off-chip interconnects. While infrared light is envisioned to be routed on the chip by waveguides patterned in the same silicon layer as transistors, integration of an efficient absorbing material is required for making photodetectors. Available in standard front-end CMOS processes, Ge is suitable for making photodetectors due to its high absorption coefficient at 1.31μm and even at 1.5μm wavelengths. Additionally, integrating a compact Ge photodetector evanescently-coupled or butt-coupled to the Si waveguide enables efficient transfer of light into the Ge layer. As a result, waveguide-integrated Ge photodetectors amenable for integration within CMOS device layer stack have become a topic of intense research and development [1–7].
To build a monolithically integrated transceiver for an on-chip optical network, it is desirable to fabricate the photodetector simultaneously with and very close to the analog amplifier circuits within the same CMOS stack. However, monolithic integration of Ge photodetector into the CMOS process flow has proven very challenging due to process complexity and severe temperature constraints. The only successful monolithic integration of Ge waveguide detectors with CMOS was demonstrated by utilizing local area epitaxy at the end of the front-end CMOS process, after completing all the high temperature rapid thermal annealing (RTA) activation of CMOS implants [1].
This paper reports an approach for monolithic integration of Ge waveguide photodetectors much earlier into the front end of line (FEOL) CMOS processing before the activation of CMOS implants, by utilizing rapid melt growth (RMG) [8–10]. Single-crystalline GOI waveguides that are aligned to the substrate were formed on top of thin SiON insulator by melting the Ge during the implant activation RTA step. Metallization was performed using standard CMOS fabrication steps for building tungsten (W) plugs and copper (Cu) interconnect wires. The direct contact between the W plugs and the Ge waveguide results in the formation metal-semiconductor-metal (MSM) diodes. The waveguide-integrated Ge photodetector has ultra-low capacitance and operates at low bias voltage with bandwidth exceeding 40Gbps [11–15].
2. Design
The photodetector design consists of a Ge waveguide overlaid on top of a Si waveguide, but separated by a thin dielectric layer as shown in Fig. 1 . For optimal receiver performance, the waveguide-integrated photodetector has to achieve high bandwidth, low capacitance, high responsivity, and ideally single-mode operation at 1.5μm wavelength. These requirements are mostly contradictory to each other; hence, the photodetector has to be designed by evaluating and minimizing the tradeoffs.
Fig. 1 Schematics of the Ge photodetector consisting of Ge layer on top of SiON film, W plugs, and Cu interdigitated fingers.
Utilizing a thin Ge layer enables higher bandwidth, because the applied electric field penetrates the whole volume of the Ge waveguide resulting in drift-limited carrier transit time. However, the thin Ge layer has lower mode confinement factor (MCF) which leads to reduction in the responsivity of the photodetector. Increasing the length would enable more light to be absorbed, but it would also increase the capacitance and cause RC limitation to the bandwidth.
Thus, in order to maximize the responsivity for the 100nm thick Ge layer without large increase in length, optimization the mode structure in the combined Si and Ge layers was performed by utilizing a mode solver package (Fimmwave by Photon Design [16]). The calculations showed that a single mode can be achieved at 1.5μm for a Ge waveguide with width of 500nm and thickness of 100nm, on top of a Si waveguide that is also 500nm wide and 100nm thick. A MCF of 66% in the Ge waveguide was obtained, requiring an effective absorption length of 10μm to absorb over 97% of the light. Slight increase of the width of the Ge waveguide to 700nm results in two modes, with the MCF exceeding 70% for the fundamental mode. In this case, adiabatic coupling to the fundamental mode can be achieved by using a very short taper at the input of the Ge waveguide.
The electrode for the photodetector was designed to utilize standard CMOS metallization with W plugs. Unlike previous reports wherein continuous metal electrodes run along the sides of the Ge waveguide [5], this design uses a series of tungsten plugs running along the center of the Ge waveguide (see Fig. 1). As a result, the electrode size and separation is not limited by the width of the Ge waveguide, but by the critical dimension on the mask. This approach provides two major advantages. First, the design minimizes the amount of metal touching the Ge waveguide, thus enabling smaller capacitance. Second, high bandwidth operation at low bias voltage can be achieved by reducing the separation between electrodes.
The electric field in the 100nm thick Ge layer, with W plugs that are 150nm in diameter and separated by 300nm (pitch of 450), was calculated using ANSOFT Maxwell 3D electrostatic simulation package [17]. At applied bias of 2V, the electric field spreads throughout the Ge layer with the field magnitude exceeding 3x104V/cm. The field is high enough to sweep both holes and electrons at their saturation velocity, thus resulting in 3dB-bandwidth above 35GHz.
However, it is very well known that metal electrodes induce absorption and scattering of light that can significantly degrade responsivity. Especially, the above electrode optimization for bandwidth results in an unconventional design with W plugs directly touching the area of the Ge waveguide where the fundamental mode is confined. To carefully evaluate the tradeoff in responsivity due to the metal electrodes, 3D finite-difference time-domain (FDTD) calculations were performed on the photodetector design shown in Fig. 2 . The waveguide geometry in the simulations corresponds to the single mode case discussed above. First, to investigate only the scattering loss, the transmission spectrum through the Ge waveguide was calculated using 3D FDTD with the absorption coefficient for Ge and W set to zero. The scattering loss was found to be negligible, with higher than 98% transmission obtained for 1.5μm wavelength, which is a direct result of the high mode confinement factor in the Ge layer.
Fig. 2 Comparison of the effect of losses in metallic contacts on quantum efficiency calculated for 1.5μm wavelength. In regime 1, effective absorption by the Ge waveguide is much smaller than the absorption by the electrode. In regime 2, effective absorption by Ge waveguide is higher than the absorption by the electrode.
If scattering is neglected, then the responsivity is dependant only on αGe and αW, which represent the effective absorption coefficients per unit length for the Ge waveguide and W plugs respectively. The material absorption of Ge and the confinement factor of the mode in the Ge waveguide determine αGe. Also, the overlap of the mode with the W plugs determines αW. In order to obtain αW, 3D FDTD calculations were carried out by setting the Ge absorption coefficient to zero and describing W by a complex refractive index. The reduction in the amplitude of the transmission spectrum through the Ge waveguide was assigned to absorption by the W plugs, from which an effective absorption αW of 4000cm−1 was calculated. With these parameters, the quantum efficiency of the structure can be calculated by using the following equation:
where LGe is the total length of the Ge waveguide, N is the number of plugs, and DW is the diameter of the W plugs.The results of calculations using Eq. (1) are shown in Fig. 2 with two important regimes that can be identified. In the first regime (regime I), the effective Ge absorption is much smaller than the effective absorption in W (αGe<<αW). The solid red curve for regime I in Fig. 2 was calculated by setting αGe to be 400cm−1. The low effective absorption coefficient could be due to low mode confinement, or low material absorption such as in a SiGe waveguide with 10% Si concentration. As a result, the absorption of light by the W plugs is much more dominant than the absorption by the Ge waveguide. In regime I, for example, the calculated quantum efficiency is significantly degraded reaching the maximum value of 23% after 25μm length.
However, another regime (regime II) is possible if αGe>αW, with most of the light being absorbed by the Ge waveguide before being scattered or absorbed by the W plugs. For example, this can be achieved by utilizing 100% pure Ge to obtain very high absorption. In order to obtain αGe, 3D FDTD calculations were performed after setting the absorption coefficient of W to zero. The transmission spectrum through the Ge waveguide was calculated by using bulk absorption coefficients of 5300cm−1 at 1.5μm wavelength. By assigning the losses to absorption by the Ge waveguide, an effective absorption αGe of 4200 cm−1 was calculated. As shown by the black curve in Fig. 2, a high quantum efficiency exceeding 75% can be achieved.
To conclude, very high quantum efficiency is achievable in the structure presented in Fig. 1 by utilizing pure Ge for higher absorption of light and by optimizing the optical mode confinement in the Ge waveguide. The above results show that compact footprint, high responsivity, and high bandwidth at low voltages can be achieved simultaneously through careful optimization of both optical and electrical designs.
3. Monolithic integration with FEOL CMOS
3.1 Challenges in Ge integration
Various integration approaches reported [1–7] have relied on epitaxial growth of Ge directly on Si substrate. However, there are two main challenges when utilizing epitaxial growth of Ge for monolithic integration with CMOS stack. The first challenge is the formation of misfit dislocations due to the ~4% lattice mismatch between Ge and Si [18]. Techniques such as depositing graded SiGe buffer layers and post-growth cyclic anneal are common practice for lowering defect density [2–4]. However, epitaxial growth of a thin Ge layer still results in very high defect density thereby degrading the performance of the photodetector.
The second challenge is associated with the temperature budget in CMOS process modules. While the temperature for FEOL CMOS processes usually exceeds 1000°C, it has to be below ~550°C after the formation of metal contacts. On one hand, epitaxy has to be performed before the contact module because growth of Ge on dielectric requires SiGe buffer layers grown at ~600°C. On the other hand, the epitaxy has to occur after completing all the high temperature processes in order to avoid melting of the Ge film (937°C). As a result, previous demonstrations have utilized integration of Ge photodetectors after gate processing and implant activation, but before contact modules [1].
The photodetector in this paper was fabricated with an alternative approach, wherein Ge waveguides were monolithically integrated much earlier into the front-end CMOS process, before the activation of source/drain implants. Rapid melt growth technique was utilized to form thin single-crystal Ge waveguides by melting the Ge at the same step as implant activation RTA. The early introduction of Ge would potentially make integration cost cheaper, because hundreds of standard processing steps that already exist in front-end CMOS process could be utilized for fabricating the photodetector. The RMG technique also enables the utilization of cheaper Ge deposition methods, such as plasma-enhanced deposition, which do not require expensive ultra-high vacuum chambers.
3.2 Integration of Ge into FEOL CMOS utilizing RMG
Integration of photodetectors was performed on 200mm SOI wafers by utilizing photolithography and standard CMOS processes. The SOI (100) wafers were p-type with 10Ω-cm resistivity, having 220nm thick Si and 2μm buried oxide (BOX). First, Si waveguides were lithographically defined and etched simultaneously with CMOS shallow trench isolation (STI) features. While the etch chemistry resulted in small line-edge roughness, sidewall oxidation was performed with the goal of minimizing propagation losses further [19]. Then, a 600nm thick silicon oxide film was deposited on the wafer. To eliminate the resulting topography, the oxide was planarized to the Si by a chemical mechanical polish (CMP) process. During the CMP step, the area where the photodetector devices will be located was intentionally over-polished to achieve a final Si thickness of 120nm. Subsequently, a 40nm thick SiON layer was deposited on top of the flat surface and 1μm wide windows intersecting the Si waveguides were etched in order to expose the top surface of the Si waveguide as shown in Fig. 3a .
Fig. 3 (a) Top-down SEM image showing a tapered Ge waveguide. At the crystallization window, the Ge and Si waveguides are in direct contact. (b) Cross-sectional Z-contrast image (left), SAD (middle), and HRTEM (right) obtained from both Si and Ge waveguides 1μm away from the crystallization window. (c) Cross-sectional TEM image (left), SAD (middle), and HRTEM (right) obtained 30μm away from the crystallization window. The SAD patterns at 1μm and 30μm show identical crystal lattice orientation for the Si and Ge, thus demonstrating that single-crystalline Ge-on-insulator was achieved 30μm away from the crystallization window.
The pattering of the SiON layer was followed by deposition of 150nm thick Ge on the wafer. Because CVD deposition was utilized, a 20nm thick SiGe buffer layer was grown first both on the SiON and the exposed Si surface. The buffer layer helps to minimize columnar growth thus lowering surface roughness. The SiGe layer is in direct physical contact with the Si waveguide through the etched window. Outside of the crystallization window, the SiON blocks intermixing of Ge with Si and provides electrical isolation between the Ge and Si.
Next, waveguides were lithographically defined on the Ge film and etched down to the SiON, thus forming Ge waveguides overlaid on the crystallization window and the Si waveguide. The flat surface resulting from planarization during the STI module enables the formation of Ge waveguides aligned on top of the Si waveguides but independent in width. The width of the Ge waveguides was varied between 500nm and 700nm. The SEM in Fig. 3a illustrates a Ge waveguide after etching has been completed. On the left hand side of the figure, the crystallization window opens a region wherein the Ge waveguide touches the Si waveguide directly. On the right hand side of the figure, the Ge and Si are separated by the thin SiON layer. Additionally, the photodetector has a taper to facilitate adiabatic coupling of light from the Si waveguide.
After etching was completed, the Ge waveguides were encapsulated with SiN/SiO2 dielectric layers and the wafer was annealed utilizing the same RTA step as the activation of CMOS implants. The SiGe/Ge melts during the RTA step which is typically performed around 1000°C. A crystallization front starts from the crystallization window where SiGe is in direct physical contact with Si and then propagates along the waveguide. This results in the formation of a single-crystal waveguide with about 90% concentration of Ge.
To perform scanning transmission electron microscope (STEM) analysis on the Ge waveguide after crystallization, a 30μm long specimen was cross-sectioned by focused ion beam (FIB) along the lateral direction of the waveguide. Figure 3b shows a lateral cross-section Z-contrast STEM image taken at the crystallization window. The image shows defects, voids, and intermixing between Ge and Si; however, the defects and intermixing do not extend beyond about 100nm from the crystallization window. The selected area diffraction (SAD) patterns and the high resolution TEM (HRTEM) images in Fig. 3b are taken 1μm away from the crystallization window. Here, the intermixing between Si and Ge is blocked by the SiON insulator. The SAD patterns from the Ge and Si waveguides show identical crystal orientations even though being separated by the SiON, confirming that single-crystal GOI aligned to the substrate was achieved. Additionally, the HRTEM shows the Ge is defect-free 1μm away from the crystallization window.
Figure 3c shows a lateral cross-section Z-contrast STEM, SAD, and HRTEM images taken 30μm away from the crystallization window. The identical SAD patterns indicate the orientation of the Ge lattice is preserved with respect to the Si, hence confirming the formation of a single-crystal Ge waveguide. Also, the HRTEM shows the Ge waveguide is defect-free 30μm away from the crystallization window. Similar results were obtained from HRTEM analysis performed along the length of the specimen, confirming that the whole GOI waveguide specimen was single-crystalline and defect-free all the way to 30 μm in length. These results are similar to other studies on the RMG technique which have reported comparable results [8–10]. From over ten specimens that were analyzed, only one showed the formation a single twin boundary. This gives a rough upper estimate for the defect density of about 3x106 cm−2. The defect density is most likely much lower, but would require much more statistical analysis to confirm. Thus, defect-free GOI waveguides that are 30μm long have been successfully fabricated by introducing Ge much earlier into the front-end CMOS process before high-temperature implant activation steps.
3.3 Integration of metal contacts
After Ge crystallization was completed, the encapsulating dielectric was planarized by a CMP process and vias were etched to the top surface of the Ge waveguide. Next, W was deposited and then polished away from the field area by a CMP step. Figure 4a illustrates top-down SEM of the W plugs after CMP planarization has been completed. Subsequently, an additional dielectric layer was deposited and patterned to form Cu interconnects. The optical micrograph image of the photodetector after the formation of the Cu interconnects is shown in Fig. 4b. Cu fingers from the two pads extend across the Ge waveguide, overlapping in an interdigitated manner and contacting the W plugs along the length of the Ge waveguide.
Fig. 4 (a) Top-down SEM image of the photodetector after W plugs have been fabricated. The plugs, aligned in the middle of the Ge waveguide, have a contact separation of 300nm (pitch of 450nm) and diameter of 150nm. (b) Optical micrograph of the photodetector after the fabrication of copper interconnects. (c) Lateral cross-sectional TEM image of the photodetector. The roughness on top of the Ge film is attributed to CVD growth on dielectric.
Figure 4c shows a lateral cross-section Z-contrast TEM taken across the interdigitated fingers. As shown by the images, there is a direct physical contact between the W plugs and the Ge waveguide, as well as the Cu interdigitated fingers and the W plugs. The contact between the W plugs and the Ge waveguide results in the formation of Schottky barriers. Because neighboring plugs are connected to opposite pads by the interdigitated fingers, the series of back-to-back connected Schottky contacts form many parallel MSM diodes which span the length of the Ge waveguide.
3.4 Integration of SiON fiber couplers
Efficient coupling of external laser light into the Si waveguide is important for practical implementation of monolithically integrated receivers. Polymer-based fiber couplers have been demonstrated for low-loss coupling of light from a fiber into the nanophotonic silicon waveguide [20,21]. Also, replacement of polymer couplers with SiON couplers has been previously reported [22]. However, the proposed process is not suitable for monolithic integration because it requires the deposition of a very thick SiON film during front-end processing.
Here, the SiON-based fiber couplers were integrated by utilizing a single additional level of photolithography on top of a standard metallization level of a CMOS stack [23]. The couplers were incorporated without adverse effect on the front-end CMOS process or back-end copper metallization. First, 2μm wide trenches overlaying the tapers of Si waveguide were patterned in photoresist. Then, the trench patterns were transferred by etching through the dielectric layers in order to expose the Si waveguide tapers. Subsequently, the trenches were filled with conformal deposition of a thick SiON film. Finally, the film was removed from the copper metallization by a CMP process and wet cleaning steps, thus leaving behind SiON-based spot-size converters for efficient coupling to Si waveguides.
4. Device characterization
4.1 Capacitance
Decreasing the capacitance of waveguide photodetectors has two main advantages. First, the bandwidth of the photodetector would not be limited by the RC time-constant. Second, capacitance values in the order of a few femto-farads could allow the design of novel ultra-low-power receivers which help in reducing the power budget for optical interconnects.
The photodetector integration method discussed in Section 3 is advantageous for lowering the device capacitance. Unlike epitaxially grown Ge films which tend to be thick due to the buffer layers, RMG allows the formation of very thin Ge films which can significantly decrease the total volume. Also, utilization W plugs which have only 150nm diameter as a contact module helps in minimizing the capacitance further.
To confirm this experimentally, the capacitance of the photodetectors was characterized by using two methods (Fig. 5 ). The measurements shown in Fig. 5a were performed with HP4192A impedance analyzer at 10MHz. The capacitance measured on a reference structure consisting of two open-circuit probe pads was 7fF. A second reference structure consisting of open-circuit probe-pads with interdigitated Cu fingers had a capacitance of 10fF. Also, the capacitance measured on the photodetector together with the probing pads, Cu fingers, and W plugs was 23fF. De-embedding the parasitic probe pad and Cu finger capacitance, the photodetector with the W plugs has only 13 ± 2fF.
Fig. 5 (a) Results of capacitance characterization by an impedance analyzer. Black and red traces represent capacitance measured respectively for open-circuit probe pads, and probe pads with interdigitated Cu fingers. The blue trace represents the capacitance measured for a photodetector. (b) Real and imaginary impedance extracted from S11 measurement. The red traces show the impedance for an open-circuit probe pad with Cu fingers. The blue traces show the impedance for a photodetector. The dashed black lines represent the results of fitting performed using the equivalent circuit model shown in the inset.
To further characterize the capacitance, frequency-dependant reflection (S11 coefficient) measurements were performed up to 15GHz with an Agilent E8364C PNA Network Analyzer and the real/imaginary impedance was extracted from the amplitude and phase of the S11 coefficients. Then, the extracted impedance was fitted using the equivalent circuit model shown by the inset in Fig. 5b. RS represents the resistance of the substrate. CS represents the capacitance due to the coupling between the pads and the substrate. RP and CP are the resistance and capacitance due to the probe pads with interdigitated fingers respectively. Additionally, CPD represents the de-embedded capacitance of the photodetector including W plugs.
The reflection measurements were performed first on a reference structure consisting of open-circuit probe pads with interdigitated fingers. The extracted impedance was fitted by the equivalent circuit in the inset with CPD set to zero. Figure 5b shows fitting of the data obtained when CP has a value of 15 ± 2fF. Next, reflection measurements were obtained from the photodetector together with the probing pads, Cu fingers, and W plugs. The data was then fitted with the equivalent circuit model in the inset of Fig. 5b with fixed values for the parameters obtained from the first reference structure. A de-embedded photodetector capacitance CPD of 10 ± 2fF was obtained, which is in good agreement with the measurements performed by the impedance analyzer.
4.2 Dark current and responsivity
In order to characterize the dark current of the photodetector, I-V traces were measured at room temperature (300K) using Agilent 4156B semiconductor parameter analyzer. The dark current for a 30μm-long photodetector was 90μA for bias voltage of 1V. To investigate the source of the dark current, temperature dependant I-V measurements shown in Fig. 6a were carried out from 120K to 340K with a step of 20K. Subsequently, the dark current values at each bias voltage were fitted using a thermionic emission model [24]. For example, the inset of Fig. 6b shows the temperature dependent dark current data at 0.2V bias plotted as ln(J/T2) vs. (1/T). A barrier height of 140meV was then extracted from the slope of the linear fit. The small barrier height can be explained by Fermi level pinning close to the valence band due to metal-induced gap states (MIGS). Various approaches have been reported for depinning the Fermi level by modifying the barrier height [25–27]. For temperature below 200K, the experimental data shown in the inset is weakly dependent on temperature and deviates from the linear fit. Most likely, trap-assisted tunneling [28,29] is the cause for the dark current while thermionic emission or Shockley-Read-Hall generation mechanisms play a minor role at low temperature.
Fig. 6 (a) Temperature dependant dark current measured from 120K to 340K with a 20K step. (b) Barrier height data and fitting as a function of bias voltage. For each bias voltage, the barrier height was obtained by fitting the temperature dependent data with thermionic emission model as shown by the inset for 0.2V
Figure 6b shows the dependence of the barrier height on the bias voltage. For each bias voltage, the barrier height was extracted from the temperature-dependent dark-current measurements by using the method discussed above for 0.2V. The red trace in the figure represents the fitting performed by using the theory described in Ref. 30. The figure shows reduction of the barrier height from 140meV to 40meV when the bias voltage is increased from −0.2V to −1.95V. The reduction of the barrier height with increasing bias voltage can be explained by image force lowering and static lowering. For higher voltages, dark current contribution from tunneling is possible due to the lowering of the barrier.
To determine the responsivity of the photodetector, light from a CW laser was coupled to a polarization maintaining (PM) fiber, transferred through a polarization controller, and finally launched into the cleaved facet of the SiON coupler at the edge of the chip by using a microlensed PM fiber. The optical power at the input of the photodetector was determined by taking into consideration a total loss of 9.7dB due to waveguide propagation loss and coupling loss at the input facet of SiON coupler. The photocurrent was measured for the TE-like polarization (E-field parallel to the slab plane) by measuring I-V traces.
Fig. 7 (a) Photocurrent measured for −1V bias voltage while varying the input optical power at 1.31μm wavelength. Responsivity of 0.42A/W is obtained from the slope of the linear fit. (b) Responsivity as a function of voltage. Responsivity at each bias voltage was obtained using similar method as in Fig. 7a.
Figure 7a shows the photocurrent measured at −1V bias voltage while varying the input optical power from 2μW to 1mW at 1.31μm wavelength. The responsivity remains linear while the input power is increased over three orders of magnitude; from the slope of the linear fit of the data, a responsivity of 0.42A/W was obtained. To further characterize the responsivity, photocurrent was measured at each bias voltage while varying the input optical power. Then, the responsivity at each bias voltage was obtained from the slope of a linear fit similar to Fig. 7a. The result of the measurement for 1.31μm wavelength is shown in Fig. 7b. The responsivity at a bias voltage of 1V is 0.41A/W which corresponds to an internal quantum efficiency of 39%. For similar measurements at 1.5μm wavelength, the responsivity at 1V was 0.14A/W (internal quantum efficiency of 12 ± 3%).
The above quantum efficiency of 12 ± 3% is much less than the 75% calculated for pure Ge in regime II of Fig. 2. This is because the Ge waveguides in the experiment have only 90% Ge content due to the deposition of Si/SiGe buffer layers, which results in large reduction of absorption in the infrared compared to pure Ge. From experimental characterization of Ge waveguides of various lengths (with no W plugs), the effective Ge absorption coefficient αGe at 1.5μm was found to be only 400cm−1 for 1.5μm wavelength. The quantum efficiency calculated using 400cm−1 corresponds to regime I of Fig. 2. The figure shows a quantum efficiency of 23% for a 30μm long waveguide, which is higher than the measured value of 12 ± 3%. The reduced quantum efficiency in the experiment can be explained by the out-scattering of light due to the surface roughness of the Ge film (visible in the TEM images in Fig. 3 and Fig. 4).
In order to achieve an internal quantum efficiency of 75% over a short length, the absorption coefficient of the Ge used in the experiments has to be increased. By utilizing plasma deposition or physical deposition, a 100% pure Ge layer can be deposited without using Si/SiGe buffer layers. As a result, the effective Ge absorption coefficient αGe can be as high as 4200cm−1 at 1.5μm wavelength. The deposition techniques also provide very small surface roughness, which can help to minimize scattering out of light before absorption in the Ge layer.
4.3 Bandwidth
Owing to the ultra-small capacitance described in Section 4.1, the bandwidth of the photodetector is not limited by RC time constant; instead, the bandwidth is limited by the transit time required for carriers to drift between two contacts. Thus, by decreasing the distance between the two contacts, a very high electric field is obtained at low bias voltage. The field reaches 3x104V/cm at bias voltage of 2V for the photodetector with 300nm spacing, resulting in transit-time limited 3dB-bandwidth exceeding 35GHz [11,12].
The bandwidth of a photodetector with contact spacing of 300nm was characterized by measuring an eye diagram with 231-1 non-return-to zero (NRZ) pseudo random bit sequence (PRBS31). Light from a 1.5μm laser was modulated with an external 40Gbps LiNbO3 modulator by applying the RF signal from the PRBS generator. The output light from the modulator was then amplified with an Erbium-doped fiber amplifier (EDFA) and transmitted through a 2nm wide band pass filter to provide 2mW power at the input of the photodetector. A bias voltage of 1.5V was applied to the photodetector using 40GHz probes connected to a 50GHz bias-tee. Then, the photocurrent output from the photodetector was amplified with 45GHz amplifier and measured with an Agilent oscilloscope with 80GHz electrical plug-in. Figure 8 represent eye-diagram measurements measured at 20Gbps and 40Gbps. An eye for 20Gbps in Fig. 8a is open with rise and fall times defined by the modulator. Even for 40Gbps the eye in Fig. 8b remains open confirming the high bandwidth operation of the photodetector.
Fig. 8 PRBS31 eye-diagram measured at 1.5V bias for 1.5μm light at a) at 20Gbps, b) 40Gbps NRZ bit stream.
5. Conclusion
A compact, high-speed, CMOS-compatible waveguide-integrated Ge photodetector with ultra-low capacitance has been demonstrated. The photodetector has a measured capacitance of 10 ± 2fF and operates at 40Gbps at a bias voltage of only 1.5V. Defect-free single-crystal Ge waveguides were fabricated by introducing Ge into front-end CMOS process and utilizing rapid melt growth technique.
Acknowledgements
The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where the devices were fabricated. The authors also gratefully acknowledge Clint Schow for numerous discussions.
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