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This paper reports an integrated optical buffer consisting of a low loss silicon waveguide delay line and a silicon evanescent gate matrix switch. The integrated device demonstrates an error free operation at 40 Gb/s data rate with a packet delay of 1.1 ns. This demonstration also highlights the silicon evanescent device platform to realize new types of photonic integrated devices by combining the low loss silicon passive components with the silicon evanescent photonic active devices.
©2008 Optical Society of America
1. Introduction
Optical buffers are one of the important components to realize all optical packet switched networks to address contention and congestion of optical packets. Several approaches have been demonstrated including silicon coupled resonators [1], photonic crystals [2], and fiber delay lines [3, 4]. The first two approaches can be categorized into feed-forward buffers based on slow light technology while the last approach is based on feed-back buffers consisting of a recirculating delay line and an optical switch. The feed-back buffers offer several advantages over other approaches in terms of compact integration and large delay [5] even though a fixed delay line length sets some restrictions of a minimum delay and a maximum packet length.
This paper reports an integrated optical buffer consisting of a low loss silicon waveguide delay line and a silicon evanescent gate matrix switch. The demonstrated device is implemented with a 9 cm long delay line, silicon evanescent gate matrix switch and four silicon evanescent amplifiers [6]. A 2×2 gate matrix switch is chosen over interferometer based switches because it provides low crosstalk and high extinction ratio which are important metrics for cascadability and multiple recirculations [7]. Furthermore, the gate-matrix approach can be used to broadcast the packet in multiple time slots for broadcasting to multiple ports. The demonstrated gate matrix switch has a DC crosstalk of −34 dB and a DC extinction ratio of −41 dB. The integrated device operates at 40 Gb/s data rate, and a packet delay of 1.1 ns is demonstrated with a power penalty of 2.4 dB.
2. Device structure and fabrication
Figure 1(a) shows a layout of the integrated device. This is a recirculating optical buffer structure consisting of a silicon delay line and a gate matrix switch with additional boost amplifiers. Once optical packets are routed into the delay line, they are stored in the delay line until the gate matrix switch re-routes them to the output.
The 2×2 gate matrix switch consists of two MMI splitters and four switching amplifiers. Input packets are split into two output ports and one of the split signals is gated by the amplifiers to a desired output port as illustrated in Fig. 1(b). Since this is based on a broadcast-and-selection method, there is an inherent loss of 6 dB from the input splitters and the output combiners. However this loss can be compensated from the optical gain of the switch amplifiers. The gate matrix switches are important for high cross talk suppression and high extinction ratio from the high absorption by reverse-biasing the amplifiers. However, the amplifiers need to be designed properly to ensure operation with a low power penalty from amplified spontaneous emission (ASE) noise.
Fig. 1. Device layout (a) integrated buffer (b) gate matrix switch. The cross-over operation is illustrated as an example.
Figure 2 shows the process flow of the devices. After silicon waveguides are dry etched, a 0.5 μm thick SiO2 layer is deposited on the silicon sample without removing a SiO2 hard mask layer. Then, the silicon waveguide region for the amplifiers and the switch, where the III-V sample will be bonded, is exposed by wet-etching the SiO2 layer by buffered HF. After a cleaning procedure, the III–V sample is roughly aligned by tweezers and bonded on the opened silicon region. The SiO2 layer on the delay line region serves as a protection layer from scratches and any possible contaminations which can be caused by the bonding process. After anneal and InP substrate removal, the III–V layer for the amplifier and the switch is lithographically defined by a CH4/H/Ar-based plasma reactive ion etch. An additional 0.5 μm thick SiO2 layer is deposited for the protection of the silicon waveguides in the switch region.
Then the III–V region is opened by CHF3 based dry etching of the SiO2 layer. Finally the amplifiers are fabricated on the exposed III–V region using the self aligned process described in Ref. 8. The silicon waveguide in the delay line region is protected by ∼ 1 μm thick SiO2 layer. After all of the III–V processing is finished, ∼0.7 μm thick SiO2 layer still covers the silicon waveguides and is also used as a waveguide cladding.
Figure 3(a) shows SEM images of the fabricated amplifiers in the optical buffer. The fabricated silicon waveguide has a width of 2 μm, a height of 0.7 μm, and a slab height of 0.4 μm. The total length of the silicon delay line is 9 cm. The minimum bend radius of the silicon delay line is 500 μm so that the bend loss is minimized. On a ∼0.6x1 cm2 chip, four devices are integrated by interleaving four delay lines. The fabricated device is mounted on an aluminum nitride (AlN) carrier and the electrical pads of the device are wire-bonded to the carrier for device probing using a probe card. An image of the mounted device is shown in Fig. 3(b).
Fig. 3. (a). SEM image of 8 integrated silicon evanescent amplifiers (b) Microscope image of the 4 integrated buffers mounted on an AlN carrier.
3. Experiment and results
The device is mounted on a temperature controlled stage set to 15 °C. Lensed fibers are used for the input and output light coupling. The loss of a 9 cm long delay line is first measured to be 15 dB from a test structure which has the same waveguide design as the integrated device without the amplifiers and the couplers.
The gain of the amplifier is characterized by measuring photocurrents from an adjacent reverse-biased amplifier. The input and output amplifiers are 1200 μm long while the switch amplifiers are 800 μm long. Figure 4(a) shows the measured amplifier gain as a function of current. The maximum gain of the input/output and switch amplifier is 8 dB and 6 dB respectively. The ideal 3 dB loss of the MMI splitter is used to estimate the chip gain of the amplifiers. The available net gain from these amplifiers is enough to compensate the delay line loss (15 dB).
The crosstalk and DC extinction ratio of the gate matrix switch is measured to be -34 dB and 30 dB respectively. The rise and fall times are slightly under 1 ns for an input power variation of -9 to -1 dBm. In general, the switching time is dependent on the electrical circuit response and the carrier lifetime of the amplifier [7].
The integrated device performance was evaluated with a return-to-zero (RZ) pseudorandom bit sequence (PRBS). Figure 5 shows the test setup used for the measurements. A return-to-zero (RZ) 40 Gb/s data packet at a wavelength of 1560 nm was transmitted through a single mode fiber after amplification by an EDFA. An attenuator and a polarization controller are used between the transmitter and the device to control the input power and the polarization. The polarization is set to TE to maximize the optical gain of the on-chip amplifiers in the device. The output signal of the device is amplified by an additional EDFA and then is received by a high speed receiver. The ASE noise of the input and output signal is filtered by band pass filters with 1.2 nm spectral band width. The power level to the receiver is controlled by a VOA to facilitate BER measurements at different receiver input powers.
Figure 6 shows data packets (25−1) with two different switch configurations (through and cross-over). The figure shows a packet delay of 1.1 ns after one recirculation through the 9 cm long delay line [Fig. 6(b)]. The additional insertion loss after one recirculation is 2.6 dB because the signal wavelength (1560 nm), which is chosen for EDFA amplifications, is different from the gain peak of the on-chip amplifiers (1572 nm). The plots on the right side of Fig. 6 show a close-in view of the received packets. The packet after one recirculation has slightly more power fluctuations due to the ASE noise from three additional on-chip amplifications.
Fig. 6. (a). Data packet without recirculation (through switch state) (b) Delayed data packet after one recirculation (cross-over switch state).
To quantify the effect of the multiple amplifications, bit-error-rate (BER) measurements with 231−1 PRBS data streams were carried out. Figure 7(a) shows the measured BER as a function of power at the receiver with different input power levels to the device. In general, BER of the delayed signal is higher than non-delayed signal as shown in the figure. Figure 7(b) shows the power penalty at a BER of 10−9 as a function of the input power. The power penalty without the delay is less that 1 dB with an input power variation of −16 to −4 dBm. However, the power penalty with one recirculation increases up to 4.3 dB because of additional ASE noise and shows a bathtub curve minimized at an input power around −10 dBm. At a low input power, the power penalty is dominated by the ASE noise while at a high input power the power penalty increases again because of the saturation of the amplifiers. The input dynamic range for less than a 3 dB power penalty is 8.5 dB for one recirculation.
In order to understand the current device performance, a simple device model, shown in Fig. 8, is analyzed. The model is based on a cascaded amplifier link consisting of lossy passive components and amplifiers. The definition of each term is given in Table. 1. In this model, only the effect of the ASE noise is considered to simplify the problem.
Fig. 7. (a). Measured BER as a function of the received power with different input powers to the device. (b). Power penalty at a BER of 10−9.
The signal transmission in the device can be divided into three stages: 1) input stage, 2) recirculating stage, and 3) output stage. The effect of transmission through each stage is represented by an effective noise factor and a net gain, which can be calculated using a simple model of a cascaded chain of passive elements and amplifiers [9]. The detailed mathematical derivation is omitted here, and the resulted net noise figure of each stage is shown in Fig. 8. From the noise factor and the net gain of each stage, the effective noise factor of the entire device can be derived as a function of a number of recirculation (N), which is written as Eq. (1).
Since the device needs to be biased below the lasing threshold, there is another constraint that the net gain of the recirculating stage (GLOOP) should be less than unity. Applying this condition to Eq. (1), the minimum noise factor after N recirculations occurs when GLOOP is unity and is written as Eq. (2).
Table. 1. Device Definitions of the parameters used in the device model.
Equation (2) suggests several ways to minimize the signal degradation from the ASE noise accumulation. First, the noise factor increases linearly as the number of the recirculations increases with a rate of FLOOP/GIN which is de-emphasized noise factor by the input amplifier gain at the recirculating stage. Therefore the input amplifier gain (GIN) needs to be high enough to suppress the effect of the noise accumulation from the multiple recirculations. Next, the noise factor of the recirculating stage (FLOOP) needs to be minimized for the same reason. As shown in the equation in Fig. 8, FLOOP is primarily determined by a product of the loop loss and the gain of the loop amplifier (Gd Ld), which implies that signal power entering the loop needs to be preamplified with a higher gain.
The power penalty can be estimated by calculating receiver sensitivity for each recirculation. To simplify the calculation, it is assumed that ASE noise is dominant on the receiver sensitivity over other factors such as modulation format and timing jitter. Equation (3) is used for this calculation and the power penalty is defined as receiver sensitivity degradation at a BER of 10−9. A −27 dBm receiver sensitivity, which is estimated from the back-to-back BER measurements, is used as a reference. This equation also makes the approximation that the shot and thermal noise are negligible compared to the beat noise of the ASE against itself and the signal [10].
where h, ν, Δf, δν, and Q are Plank’s constant, optical frequency, electrical bandwidth of the receiver, optical bandwidth of the bandpass filter, and quality factor, respectively.
Fig. 9. Calculated power penalty as a function of a number of recirculation with a different loss of the delay line and gain of the input amplifier.
Figure 9 shows the calculated power penalty as a function of a number of recirculation with a different loss of the delay line and gain of the input amplifier. A quality factor (Q) of 6 is used which corresponds to a BER of 10−9. The optical and electrical bandwidth are assumed to be 2 nm (246 GHz) and 40 GHz respectively. As shown in the figure, the input amplifier gain and loop loss are crucial factors affecting the quality of the signal after many recirculations. With a lower loop loss and higher input amplifier gain, the effect of the noise accumulation can be suppressed further. It is predicted that 9∼10 recirculations with a power penalty of 2 dB can be achieved if a loop loss and an input amplifier gain can be 15 dB and 10 dB, respectively. However it is inevitable to have a more loss from a longer delay line. A delay of 10 ns corresponds to a ∼80 cm long silicon waveguide resulting in a typical loss of 20 ∼30 dB even with a sub-dB/cm waveguide loss. Therefore, adding one or two more amplifiers inside the delay line will lead to better performance in this case. Signal degradation from the pattern effects needs to be considered and weighted with the benefits from additional amplifications. In addition, the device layout has to be laid out carefully in order to suppress thermal run-away effect due to the integration of many optical amplifiers.
4. Conclusions
An integrated optical buffer operating at 40 Gb/s is demonstrated in this paper. The device consists of the silicon delay line and the gate matrix switch built on the silicon evanescent device platform. The silicon delay lines are designed to minimize the bend loss, yet they are still compact enough to enable the entire device to be laid out within a 0.6×1 cm2 space. The gate matrix switch is chosen over other types of optical switches because of a low cross talk of −30 to −40 dB. The fabricated device demonstrates a 1.1 ns delay of 40 Gb/s data packets. The minimum power penalty with a 1.1 ns delay is 2.5 dB with an input dynamic range of 9 dB. Further improvements on the waveguide loss and the amplifier gain should improve the device performance, leading to a longer buffering time, and will provide enough functionality as integrated optical buffers for all optical packet switched networks. In addition, this structure can be directly extended to integrated optical synchronizers with several gate amplifiers [11].
Acknowledgments
We thank H. W. Chen for dicing and R. Jones for useful discussions; Mike Haney, Jag Shah and Wayne Chang for supporting this research through DARPA contractW911NF-04-9-0001.
References and links
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