Josef Giglmayr, "Organization of k × k switches (k ≥ 4) interconnected by d-dimensional (d ≥ 2) regular optical patterns," Appl. Opt. 30, 5119-5135 (1991)
The concept for the generation of arbitrary permutations of d-dimensional data cubes in a multistage manner is presented. In particular, d-dimensional switching cubes are proposed, and the geometry of the ports of the switches and their locations within the switching cubes (d = 3,4) are discussed. A new addressing scheme for the ports of these switches is presented, which is called the horizontal coding of addresses because the ports of the switches are distributed to the subsequently arranged arrays of the cube(s) in a horizontal manner. This addressing scheme permits any desired organization of the switches and the ports by reordering the absolute d-tuple addresses. This reordering is described by permutation matrices and explained by means of several examples. Within this addressing scheme relative addresses of the ports of the switches (which are a subset of the common absolute addresses) are introduced. Relative addresses offer an additional saving of hardware if applied within the concept of rearrangeability.
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Address Code for Vertically Arranged 8 × 8 Switches on an 8 × 8 Arraya
The number of digits within the boxes indicates the size of the address window of the relative addresses. For the relative addresses the row major indexing is applied in Fig. 8(a).
Table 6
Address Code for the First 8 × 8 Switch on an 8 × 8 Data Arraya
The number of digits within the boxes indicates the size of the address window of the relative addresses. For the relative addresses (b) row major indexing, (c) shuffled row major indexing, and (d) column major indexing of the ports is applied in Figs. 8(b)–8(d).
Table 7
Address Code for 8 × 8 Switch on a 3-D Data Cube of Size 43a
The number of digits within the boxes indicates the sizes of the address window of the relative addresses. For the relative addresses cf. Fig. 9(a), for the absolute addresses cf. Fig. 11, and for the various organization schemes cf. Table 4. The triples are written in this order: page, row, and column.
Table 8
Collection of Addresses and Address Windows for the Multistage Interconnection of Different Data Arraysa
The number of rectangles expresses the length of the address (one for each bit). The absolute address means the d-tuple address. The mapped address is obtained by reordering the absolute address. The first component (presented) is the relative address applied to number the inputs/outputs of a switch, h means horizontally and υ vertically arranged 8 × 8 switches.
Tables (8)
Table 1
Interconnections of 16 × 16 Data Arrays
Realization
I
II
III
2-D
3-D
—
4-D
—
—
Transformed pattern
S(4, 64)
S(8, 32)
S(16, 16)
Table 2
Address Code for 4 × 4 Switches Applied to Map 1-D Data of Length 16a
The binary number within the boxes is the relative address, and the size of the address window is 2. Data length, 16.
Table 3
Address Code for 4 × 4 Switches on a 4 × 4 Data Array
The number of digits surrounded by the boxes indicate the size of the address window of the relative addresses redrawn from Fig. 7(b).
Address Code for Vertically Arranged 8 × 8 Switches on an 8 × 8 Arraya
The number of digits within the boxes indicates the size of the address window of the relative addresses. For the relative addresses the row major indexing is applied in Fig. 8(a).
Table 6
Address Code for the First 8 × 8 Switch on an 8 × 8 Data Arraya
The number of digits within the boxes indicates the size of the address window of the relative addresses. For the relative addresses (b) row major indexing, (c) shuffled row major indexing, and (d) column major indexing of the ports is applied in Figs. 8(b)–8(d).
Table 7
Address Code for 8 × 8 Switch on a 3-D Data Cube of Size 43a
The number of digits within the boxes indicates the sizes of the address window of the relative addresses. For the relative addresses cf. Fig. 9(a), for the absolute addresses cf. Fig. 11, and for the various organization schemes cf. Table 4. The triples are written in this order: page, row, and column.
Table 8
Collection of Addresses and Address Windows for the Multistage Interconnection of Different Data Arraysa
The number of rectangles expresses the length of the address (one for each bit). The absolute address means the d-tuple address. The mapped address is obtained by reordering the absolute address. The first component (presented) is the relative address applied to number the inputs/outputs of a switch, h means horizontally and υ vertically arranged 8 × 8 switches.