Abstract
Scaling computing systems to Exaflops will require tremendous increases in communications bandwidth but with greatly reduced power consumption per communicated bit as compared to today’s Petaflop machines. The new class of photonic devices is emerging that are made of silicon side-by-side with silicon transistors using the same tools and processes as CMOS front-end [1]. Substantial progress has been made recently in demonstrating such ultra-compact micron-scale silicon nanophotonic devices, as wavelength-division multiplexers [2-3], low-power modulators [4], temperature-insensitive low-latency switches [5] and photodetectors [6]. These silicon nanophotonic devices have a strong potential to increase tremendously the IO capacity for inter- and intra-chip connectivity up to a Terabit/sec data rates as well as lower significantly the overall IO power consumption below lmW per Gigabit/sec.
© 2009 IEEE
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