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Abstract
An InGaAs/GaAs quantum well (QW) structure was prepared by metal-organic chemical vapor deposition (MOCVD) via a new growth method, where the InGaAs well layer and the GaAs barrier layer were grown under a variable temperature. A GaAs protection layer was employed to avoid indium atom evaporation on the InGaAs surface during the temperature change. Room and low-temperature photoluminescence (RT/LT-PL), atomic force microscopy (AFM), and high-resolution X-ray diffraction (HRXRD) were carried out to investigate the effect of the variable temperature growth method. The theoretical and experimental results indicated that it could erase the 2D islands and rebuild the surface morphology to a step-flow mode surface. The quality of the InGaAs crystal layer was also improved because of the annealing-like treatment. In addition, the study found that when the thickness of the GaAs protection layer was 2 nm and the growth temperature of the InGaAs layer was 560°C, the maximal properties of the InGaAs/GaAs QW were achieved. Moreover, high-quality multiple QWs with five periods were grown with the tailored structure. The growth method will improve the properties of strained InGaAs/GaAs QW materials and provide technical support for a semiconductor laser's performance optimization.
© 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
InGaAs materials have been considered for decades as promising III – V semiconductors and are commonly used to fabricate optoelectronic devices, such as lasers, detectors, and solar cells [1–10]. When an InGaAs material is thin enough (usually less than 10 nm) in a quantum well (QW) structure, it acts as an excellent active layer for a laser because the quantum confinement effect could improve the device performance of the threshold current density, temperature stability, and quantum efficiency [11–15]. Additionally, by changing the InGaAs layer's indium concentration, an InGaAs/GaAs quantum well could cover the wavelength range of 880–1100 nm [16]. Nevertheless, a high indium concentration will result in the aggravation of the lattice mismatch of the InGaAs/GaAs substrate, which may be an origin of defects on the interface [17–19]. Unfortunately, the defects are often traps for carriers and produce non-radiation recombination centers, which reduces a device's internal quantum efficiency.
Much research has focused on the InGaAs/GaAsP QW to improve the luminous efficiency and prevent the dislocation caused by lattice mismatch [10,20–22]. However, due to the As-P atoms intermixing at the interface of InGaAs/GaAsP, such a strain-compensated structure is associated with the risk of forming an InGaAsP quaternary compound. This formation could cause an extra emission peak or broadened FWHM to some devices with a specific center wavelength or narrow bandwidth requirement, though the thin GaAs step layer's insertion between InGaAs and GaAsP has been proved effective to a certain extent [23]. However, the potential barrier of GaAsP is higher than GaAs. It may be an underlying problem that could deteriorate a device's carrier recombination efficiency. Another major disadvantage of the InGaAs/GaAsP QW is the greater lattice mismatch than in InGaAs/GaAs, leading to a rough interface or local micro-defects. Both will increase the scattering probability of photons, creating a broad spectral device with a higher working threshold and lower electro-optical conversion efficiency.
If the GaAs material is the barrier layer, these problems will not occur. Furthermore, the introduction of strain can change the band gap structure, cause a reduction of the effective mass of a heavy-hole, and a decrease in the density of states. As a result, only a small number of carriers are required to satisfy the population inversion condition for devices. Therefore, within the critical thickness, if the InGaAs layer is under elastic strain and defect-free, a high-quality InGaAs/GaAs QW with improved properties can be obtained. However, proper selection of the growth temperature becomes a critical issue. It is well known that a high temperature is crucial to improving the GaAs crystal quality, but not the InGaAs material [24–27]. Because of the indium atom's instability, evaporation will occur at a high temperature. As a result, the indium incorporation rate in the InGaAs material will decrease. However, the atom vacancy at the InGaAs surface will deteriorate the overgrowth layers’ quality. In practice, a medium temperature is selected to grow the whole QW structure conventionally, while GaAs’ better quality is neglected.
The possibility of integrated growth at variable temperatures in an InGaAs/GaAs QW structure was explored in this research to solve this problem. Considering both the InGaAs evaporation and the GaAs crystal quality, different materials were grown at a suitable temperature. The growth must be interrupted during temperature changes in the metal-organic chemical vapor deposition (MOCVD) chamber. Thus, after the InGaAs well layer's growth, a thin GaAs protection layer is employed to protect the InGaAs surface from being exposed to a high temperature. The InGaAs material's growth temperature and the thickness of the GaAs protection layer were also studied and optimized to ensure the InGaAs/GaAs QW structure quality.
2. Experimental
All the InGaAs/GaAs QW structure samples were grown in an MOCVD chamber (Aixtron 200/4, Germany) with a low pressure of 100 mbar. Trimethylgallium (TMGa), trimethylindium (TMIn), and arsine (AsH3) were used as precursors, and palladium-diffused high-purity hydrogen was used as carrier gas. All the samples were grown on an exact GaAs (100) substrate doped with Si. The schematic structure is shown in Fig. 1. Before the growth, the substrate was heated to 700°C for 5 min to remove native oxide. To obtain a better quality, the 500 nm GaAs buffer layer and the GaAs bottom barrier layer were grown at an elevated temperature of 650°C. The surface was then cooled to a relatively lower temperature, T1, to grow the InGaAs active layer with an indium composition of 27% and a thickness of 8 nm, followed immediately by the protection layer's growth at the same temperature; the thickness was h1 nm. As mentioned above, to improve the quality of the GaAs material in the QW structure, the temperature (T2) was raised higher than T1 to grow the GaAs top barrier with a thickness of h2 nm (h1+h2=20 nm). As a contrast, the reference sample (sample A) was grown under constant temperature. The details are shown in Table 1. For all the samples, the GaAs and InGaAs’ growth rates were 1.05 µm/h and 0.86 µm/h, respectively, already verified by other experiments.
Table 1. Growth details of the InGaAs/GaAs QW structure
In this paper, all the samples were characterized by ex-situ measurement. The room temperature PL characterization was performed by the Compound Semiconductor PhotoLuminescence System (Accent RPM2000). A 532 nm laser with 350 mW power was used as an excitation source. The low-temperature PL was recorded by the InGaAs detector with liquid helium cooling. The crystal structure was evaluated by an omega-theta scan type of high-resolution X-ray Diffraction (HRXRD, Bruker D8 DISCOVER) with a Cu Kα (λ = 1.5406 Å) radiation source. The samples’ surface morphology was measured by atomic force microscopy (AFM) (Bruker ULTIMODE8) in contact mode.
3. Results and discussion
3.1 Impact of the variable temperature growth method
The InGaAs/GaAs QW structures were prepared by MOCVD technology in two different growth methods, defined as samples A and B. AFM measured the surface morphology, and the results are presented in Fig. 2. There are steps on the surface of samples A and B; the step spacing is about 360 nm and 570 nm, respectively, as shown in the inset of Fig. 2(a) and (b). Compared with sample A, the wider spacing and fewer islands on sample B illustrate that a variable temperature has considerable influence on the surface morphology. According to the growth kinetics, there is a strong dependence between the diffusion coefficient D and the temperature T, as denoted by the following equation:
where ${D_0}$ is the pre-exponential factor, ${E_D}$ is the diffusion activation energy, and k is Boltzmann constant. Furthermore, the diffusion length can be written as where $\tau $ is the time of the adatom staying on the surface. Generally, there is no desorption after metal atom deposition on the surface under high AsH3 pressure. Therefore, based on the above equations, a higher temperature could provide a longer diffusion length. In sample A, due to the non-sufficient migration at T1, the gallium adatoms are more likely to bond with the nearby nucleation sites on the terrace of the InGaAs surface rather than on the step edge. Eventually, there are more small-scale 2D islands on the surface, as shown in Fig. 2(a). As for sample B, though the surface morphology of the protection layer is similar to the GaAs barrier of sample A when the growth temperature reaches T2, more atoms can nucleate on the step edge so that the step can gradually expand with continuous deposition.
Fig. 2. Atomic force micrographs in 3×3 µm2 scan of samples A (a) and B (b); the inset is AFM height profile from points a to b on step edge.
Meanwhile, the 2D islands on the terrace also attract more atoms and continue growing. They may also combine to form a new larger island, and then either the individual islands, as shown in area I of Fig. 2(b), or the combined islands, as shown in area II of Fig. 2(b), will merge into the neighboring step that is simultaneously advancing. Once the islands and steps contact each other, as shown in area III of Fig. 2(b), the new step will form, and the islands disappear. These new steps bring new nucleation sites. The kink sites by the side of the contact point are preferred, as shown in Fig. 3. Once the atom gets enough energy, it will give preference to site A rather than B or C because there may be more dangling bonds from the neighbor atoms on the initial step edge, the initial island, or the underneath terrace, respectively. When an atom adsorbs on kink site A and bonds, it will release more energy. The surface energy and total energy are minimal, which is the material system's optimal state. Therefore, the gap between initial islands and initial steps is filled first, and the entire new step edge gradually becomes straight, as shown in Fig. 2(b). The variable temperature growth method rebuilds the surface of 2D islands due to the lack of migration of atoms at low temperatures, and the modified surface morphology shown in Fig. 2(b) is similar to the step-flow-mode surface, which is the optimal growth mode to obtain the QW structure. Moreover, as mentioned above, the adatoms are preferred to nucleate on the terrace, the step edges are relatively stationary, therefore, the step morphology and characteristics of sample A are consistent with InGaAs well layer. The In-As bond is stronger than Ga-As, resulting in higher migration rate of indium atoms. Thus the InGaAs surface step spacing is smaller than that of GaAs, which is the result that the step spacing of sample A is much smaller than sample B, whose steps are newly formed.
Fig. 3. Schematic model of adatoms bonding selection on a new step; the red spheres are adatoms, the gray spheres are underneath terrace, and the blue spheres are initial step and initial island.
The X-ray diffraction measurement was carried out. The diffraction curves are logarithmic and are shown in Fig. 4. The GaAs peaks are set as 33.0239° on the angular scale. From Fig. 4, the signal of InGaAs is more evident in sample B, which gives strong evidence that this growth method can also impact the InGaAs layer. The QW structure of sample B undergoes an annealing-like process during the interruption term when the temperature is raised from T1 to T2. Some defects induced by the low-temperature growth or lattice mismatch could be relaxed, which is also why the PL peak intensity of sample B is stronger in Fig. 5, which reaches about two times that of sample A, indicating a decreased non-radiation center. Therefore, the GaAs and InGaAs materials’ quality is improved through the variable temperature growth method; it is essential to explore this method in detail.
3.2 Thickness of the protection layer
Subsequently, the GaAs protection layer thickness was investigated. The detailed experimental parameters of the four samples are listed in Table 1 as samples C to F. According to the analysis of the AFM measurement results in 3.1, T1 was increased from 540 to 580°C to improve the surface morphology further, while T2 was still 650°C. The AFM measurement images are shown in Fig. 6. The steps of sample C show a significant difference in irregular distribution, uneven edges, and a few large holes and islands. While the surface morphology of samples D and E are almost the same, which is a typical step-flow-mode surface. However, sample F shows an even greater difference with some clusters on the surface, as shown in Fig. 6(d); the inset is a 3D image. The clusters distribute mainly beside the step edge and are in discrete size, undesired for QW structure growth. And the clusters are conjectured to be In-rich 3D islands or impurities alloy, their formation causes require further analysis, which will be presented in later work.
Fig. 6. Atomic force micrographs in 3×3 µm2 scan of samples C (a), D (b), E (c), and 6×6 µm2 scan of sample F (d); the inset is the 3D image (the Z-axis aspect ratio is 0.07), the thickness of GaAs protection layer is (a) 1 nm, (b) 2 nm, (c) 3 nm, and (d) 5 nm, respectively.
From the PL measurement results (the inset of Fig. 7), it can be seen that the FWHM of sample F is widest, up to 43.3 nm, also caused by the influence of clusters. Except for sample F, the FWHM of sample C is relatively broad combined with the AFM measurement results in Fig. 6(a). It could be conjectured that 1 nm is too thin to be precisely controlled by MOCVD technology. The surface of the InGaAs QW may not be covered by the GaAs protection layer completely. During the temperature-raising pause, exposed indium atoms on the uncovered InGaAs surface evaporate and create atom vacancies, which destroy the surface microstructure.
Thus, after the GaAs top barrier's deposition, the morphology of steps is unusual, as shown in Fig. 6. However, the evaporation does not occur on the surface under cover, and the number of evaporative atoms is small; thus, there is no apparent blue shift of the center wavelength compared with other samples. On the contrary, the blue shift increases as the protection layer thickness increases because during the temperature raising period, the In-Ga atoms are intermixed on the interface. The intermixing also deepens with the increase in thickness. Furthermore, the FWHM of sample D is much broader than sample E, which also demonstrates that the intermixing range is deeper.
The crystal quality is evaluated through the HRXRD test, and the results are shown in Fig. 8. As expected, because of the clusters, there is no significant InGaAs peak on the left of the GaAs peak of sample F. There is no strong signal in sample C either. Compared with the other samples, there are not only InGaAs diffraction peaks but also interference fringes on samples D and E, illustrating that InGaAs’ crystal quality is better when the protection layer is about 2–3 nm. However, these interference fringes are not observed in sample B. Besides, a bump can be seen on the GaAs’ right shoulder in samples C to F. Table 1 indicates that the only difference between these samples and sample B is T1. Thus, it is necessary to grow them under different T1s to ensure the influence of temperature.
Fig. 8. HRXRD patterns of samples C (a), D (b), E (c), and F (d); the intensity is under the logarithmic treatment.
3.3 Growth temperature of the InGaAs well
Based on the HRXRD conclusion above, the InGaAs layer's growth temperature and the protection layer (T1) were optimized. The detailed experimental parameters are list in Table 1, and the AFM morphology images of these samples are presented in Fig. 9. All samples transform to the step-flow-mode surface completely. As mentioned in section 3.1, temperature determines the atom migration length. From Fig. 9, it is evident that when T1 is greater than or equal to 560°C, there may be less or even no island on the GaAs protection layer surface, which means less “work load” for the GaAs top barrier because there are fewer gaps among islands to fill. The AFM measurement results also show the surface roughness (Rq) of samples G, D, and H is approximately 0.11 nm, and that of samples B and A is 0.12 nm and 0.14 nm, respectively. The decreasing trend illustrates that the existence of 2D islands leads to a rough surface on an atomic scale.
Fig. 9. Atomic force micrographs in 3×3 µm2 scan of samples G (a) D (b), and H (c); the growth temperature of the InGaAs well is (a) 560°C, (b) 580°C, and (c) 600°C, respectively.
The HRXRD measurement results of samples B, G, D, and H are shown in Fig. 10. Compared with sample B, there are interference fringes on the InGaAs diffraction peak of the other three samples. The interference fringes are increasingly evident with the increase of T1, which indicates that the InGaAs crystal quality is improved when the growth temperature becomes higher because of the annealing-like treatment. The LT-PL results shown in Fig. 11 also show excellent quality. At 10K, there is only the 1e-1h exciton emission peak. The FWHM is narrow (8.48 MeV and 8.96 MeV for samples D and G, respectively). However, the interference fringes entirely disappear when T1 is 600°C, as does the InGaAs diffraction peak; 600°C is too high for the InGaAs material growth, and the quantum well structure may have deteriorated. As mentioned in section 3.2, there are two peaks around the GaAs diffraction angle when T1 is 580°C, as well as at 600°C. The main reason is that the InGaAs/GaAs strained quantum well structure is sensitive to temperature. Relaxation occurs in the compressive InGaAs layer under high temperature [28,29]. When T1 is higher than 580°C, the relaxed InGaAs introduces tensile strain into the GaAs protection layer and top barrier in the direction parallel to the interface, the lattice constant of which increases to the same as that of InGaAs. While in the growth direction, the GaAs layer must be compressed, and the lattice constant is smaller than the GaAs buffer, which causes the GaAs peak bump on the large angle side.
Fig. 10. HRXRD patterns of samples B (a), G (b), D (c), and H (d); the intensity is under the logarithmic treatment.
3.4 Effect of variable temperature on QWs
All the measurement results indicate that the morphology and crystal quality of the InGaAs/GaAs QW with the 2 nm GaAs protection layer and 560°C variable temperature were optimal. A multiple QW (MQW) structure based on sample C was grown; the structure contained five periods of InGaAs/GaAs MQWs as the referent. HRXRD characterized the heterogeneous interfacial quality. The rocking curves are shown in Fig. 12. The diffraction pattern with variable temperature growth shows distinctly periodic diffraction peaks, indicating a periodic structure and high crystal quality. In the constant temperature sample, the InGaAs signal is not clearly detected, which may be due to the strain accumulation of MQWs, resulting in a rough interface, which can be confirmed by the AFM images in Fig. 13. The variable temperature sample exhibits an obvious step-flow growth mode. In contrast, the 2D islands on the constant temperature sample show unsharp interfaces. In addition, the thickness can be deduced from the equation [30]:
where $\mathrm{\lambda }$ is 1.5406 Å, $\Delta \mathrm{\theta }$ determined from the angle between the satellite peaks is 0.1844°, and ${\theta _{sub}}$ = 33.0239° is the Bragg angle of the GaAs (400) diffraction. Thus, the periodic thickness T (the sum of InGaAs well, GaAs protection layer and barrier) is 28.55 nm, close to the designed 28 nm, suggesting that the interfaces are discrete and without thickness fluctuation.Fig. 13. Atomic force micrographs in 3×3 µm2 scan of the constant temperature sample (a) and variable temperature sample (b).
4. Conclusion
In conclusion, according to the analysis and discussion of the samples’ measurement results, it was certain that the quality of the InGaAs/GaAs QW structure, grown by the variable temperature growth method, was superior to the conventional method. The surface morphology had been changed to a step-flow-mode surface after the deposition of a high-temperature GaAs barrier, which was beneficial to the adjacent layers’ growth. The crystal quality of the InGaAs material was also improved through the annealing-like treatment during the temperature-raising period. Moreover, the GaAs layer was critical to protect the indium atom at high temperature. However, the thickness of the protection layer is limited. The results showed that a 2 nm or 3 nm thickness was suitable. The growth temperature of the InGaAs potential well also affected the quality of the QW. Once it was higher than 580°C, both the InGaAs layer and the GaAs layer deteriorated. The InGaAs/GaAs QW structure's high performance was also obtained by the variable temperature growth method with a suitable thickness and growth temperature selection. Therefore, this technology could be widely used in the epitaxial growth of semiconductor devices.
Funding
National Outstanding Youth Science Fund Project of National Natural Science Foundation of China (21707010); Jilin Science and Technology Development Plan (20180519018JH); Jilin Education Department "135" Science and Technology (JJKH20190543KJ); National Natural Science Foundation of China (11474038).
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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