1. Introduction

Neuromorphic Photonics (NP) has gathered increasing interest in recent years owing to its potential to disrupt performance for applications that conventional digital processors are challenged with attain [1]. Namely, AI-based applications can be mapped to either tensor operation ASICs [2] or brain-inspired circuits such as NNs. Photonic circuits are well suited to high-performance implementations of NNs for two predominant reasons: interconnectivity and high-bandwidth of linear and nonlinear operations. NNs require a large web of independent connections between layers containing individual neurons. Simply put, if the output of a neuron layer can be represented by a vector, each neuron in a subsequent layer masks that vector by applying a dot product with a scalar weight (or synaptic weight) vector. This results in a layout of interconnections that can be represented as a matrix-vector multiplication, or, for fully two-dimensional data, as a matrix-matrix multiplication. Implementations are possible via passive interferometric devices with tunable elements, exploiting wavelength-division multiplexed and tunable microring resonators (MRR) [3], even in a scheme called broadcast and weight [4], or MRR and Mach Zehnder interferometers (MZI) for nonlinearity activation functions [5].

Silicon photonics (SiPh) offers to integrate a high density of optoelectronic devices combined with high quality passive components [6,7], gaining momentum as a dominant platform for photonic integrated circuits (PICs). However, there are still lack of complex on-chip electronic circuitry for calibration and control, and solutions for generating light on-chip efficiently. To progress from early system demonstrations to fully integrated processors, NP systems require new materials and technologies. For example, memory circuits that are able to interact directly with light for more agile reconfiguration and self-learning capabilities, integration of optical sources, and high-efficiency modulators. In this paper, we discuss potential solutions for these limitations, outlining key emerging devices for NP processors.

2. Moving beyond silicon photonics

In an electronic-photonic AI accelerator, the function and performance of a NN processor relies strongly on the capability of realizing and implementing (i.e. WRITE, READ, RESET operations) the weights and biases. These have to be applied to each optoelectronic device, and, depending on the specific application, they require precise phase and/or amplitude tuning of each waveguide to realize the bit resolution of the selected ML task.

We can distinguish between weight requirements and hence implementation options for classification (inference) versus machine learning (training) applications of the underlying PIC accelerator [8] Fig. 1(a); while the update rate for classification is seldom (i.e. whenever a new data set is available producing updated weights), during training step the weights and biases need to be updated constantly. This naturally leads to non-volatile state-retention for classification as compared to rapid WRITE-RESET cycles for training applications. Specifically at the network edge, the size-weight-area-performance (SWAP) requirements of AI systems are demanding, including high energy efficiency, hence stressing the non-volatile capability of the deployed weight-memory; that is, once the weights are WRITTEN, they (ideally) are zero-power consuming static functions. For memory options, electronics offers a variety of memory options with the trade-off between WRITE-speed and energy vs. READ latency. As a state-of-the-art SRAM has an access latency of 0.3ns costing about 100fJ/access, a photonic memory based on Phase-Chance Materials (PCMs) requires only the photon creation and detection energies. Considering lasers sources, coupling losses, and photodectector reading, a memory READ (access) energy of a PCM photonic random-access memory (P-RAM) takes <1fJ/access for an on-off-keyed signal at 30GHz data rates, or, about 10fJ/access for a higher bit resolution (e.g. PAM16 for a 4-bit ML classifier). Thus, a generic photonic link offers MAC operations and memory access of 10-100x higher MAC/s/J/access than SRAM. Following this potential for MAC acceleration, electro-optic reconfigurable PIC have been predicted [9] and demonstrated [5]. In fact, PCMs have recently shown promising capability, both as amplitude and phase modulation [10], exploiting the non-volatile switching between their amorphous and crystalline states.

 

Fig. 1. Performance of the AI ASIC weights and biases rely on the material of the reconfigurable memory devices. (a) Memory requirements depend on the machine learning application [8]. (b) P-RAM options from the recent literature. i-ii) An unbalanced MZI and a MRR with $\text {Sb}_{\text {2}}\text {Se}_{\text {3}}$ cell [13]. iii) A 1x2 directional coupler with GST cell [14]. iv) Waveguide with GSSe cell and multiple double-sided heaters [10]. v) Schematic of the laser pulse to amorphized and crystallize the integrated phase-change photonic memory cell [15].

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Another energy inefficiency is due to the Free-Carrier Depletion effect for SiPh modulator being weak, as it requires high voltages to achieve significant index modulation. This inefficiency is problematic because neurons and tensor weight updates require a sufficient modulation so that small signals can span all features of the nonlinear activation function [11]. Better results could be obtained using proper E/O modulation materials such as Indium Tin Oxide (ITO) [12].

2.1 Emerging materials for non-volatile optical memory

2.1.1 Why is memory important?

Memory is key element of all the modern computer, as CPU keeps transferring data and instructions from and to it. On the optical side, P-RAM has the potential to play the same role, allowing to store phase and amplitude variation on a PIC, exploiting development of PCMs.

In recent days, the widely studied PCMs include transition metal oxide, chalcogen-based and antimony-based PCMs, such as vanadium $\text {VO}_{\text {2}}$, $\text {Ge}_{\text {2}}\text {Se}_{\text {2}}\text {Te}_{\text {5}}$ (GST), $\text {Ge}_{\text {2}}\text {Sb}_{\text {2}}\text {Se}_{\text {4}}\text {Te}_{\text {1}}$ (GSST), $\text {Ge}_{\text {2}}\text {Sb}_{\text {2}}\text {Se}_{\text {5}}$ (GSSe), and $\text {Sb}_{\text {2}}\text {Se}_{\text {3}}$. All those materials are embedded into PIC devices whose phase can be reversibly switched between crystalline and amorphous via heating processes. The photonic properties between the two phases are significantly different with distinct refractive index (n, k) contrast which divides PCM-based P-RAM into two groups: phase-shifting modulation, and amplitude modulation. For the phase-only modulation, a variety of PCMs is embedded into resonate-based devices and directional couplers [13,14,16]. Vanishingly small insertion loss, large index contrast ($\Delta$n) PCMs such as GSST and $\text {Sb}_{\text {2}}\text {Se}_{\text {3}}$ are preferred due to low insertion loss and small footprint. For amplitude-only modulation, the variety of large index contrast ($\Delta$k) and small insertion loss PCMs are covered over the waveguide, such as GSSe and GST [10,15]. To trigger the transition of PCM, local annealing has to be applied on the material which normally relies either on the external laser heating, or on heater. From the perspective of footprint and energy efficiency, external laser heating is a better option since the laser can be directly guided to the target material. On the other hand, micro-heaters have a programming setup simpler compared to the laser heating, though they need extra space for contact pads. A mix of the two approaches might combine the best parts of both, having larger post-fab trimming with laser heating, and fast tuning with local heaters.

2.2 Efficient modulator materials for silicon photonics

Current SiPh platforms do not support highly-interconnected NNs unless they use (a) more sensitive modulators, (b) integrated transimpedance amplifiers (TIAs), or (c) operate at a sub-GHz bandwidth [11]. This occurs because modulators need a large voltage swing to reach the nonlinear threshold, which suppresses the noise between neural layers – a requirement for cascadable analog links. Solutions as increasing optical pump power or providing electric transimpedance gain come with drawbacks, such as nonlinearities in waveguides or bandwidth limitations.

In order to construct O/E/O neurons that can operate at >10 GHz, we need a modulator that has simultaneously a low-capacitance (RC limited) and a low-Vpi (e.g. 50 mV). Comparing $V_{\pi }L$ parameter, while best p-n junctions have reached down to 360 V$\mu$m [17], other heterogeneously devices could reach the wanted performances, such as ITO-based modulator (95V$\mu$m [18]), or ITO-graphene device, that can implement high-bandwidth modulation up to more than 130 GHz [19], opening the possibility to implement Non-Linear Activation Functions on SiPh PIC.

3. System integration strategies for electronic-photonic AI ASICs

Dealing with optical and electrical I/O is another important aspect for NP system. In particular, optical components require their own electrical bondpads for external interfacing, and so for large-scale NP circuits, the chip’s footprint is dominated by electrical pads and routing, as well as thermal constraints. As the photonic devices are limited in size by the lightwave’s wavelength, PICs are expected to have a larger area than CMOS ASICs, and using the PIC as an interposer between the CMOS ASIC and the PCB can be the logical solution.

Optical I/O still lacks the maturity level reached by the electrical one, limiting the ultimate PIC-electronic integration, as shown in Fig. 2. Today, optical I/O is generally addressed by coupling structures such as grating or edge couplers. These solutions show low insertion loss (as low as 0.5dB for edge couplers [20]) but still rely on sub-micron alignment of fibers. More recently, promising solutions surfaced, such as photonic wire bonding (PWB) [21], which can connect arbitrarily placed devices on the same interposer or substrate. This approach has the most potential in the short term, enabling integration of existing solutions into one single platform.

 

Fig. 2. Example of I/O integration for PIC. a-b) Well-known coupling structures, such as Grating and Edge couplers [20]. c) Example of Photonic Wire Bonding [21]. d) Back-side-on-BOX heterogeneously integrated III-V-on-silicon [22]. e) Hybrid integration using Micro-Transfer-Printing [23]. f) Graphical representation of the Photonic Black-box concept.

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Full integration of lasers on silicon has been demonstrated by a different research groups, including Back-side-on-BOX heterogeneously integrated III-V-on-silicon [22], quantum dots on silicon [24], and hybrid integrated semiconductor [23]. Integration of optical sources represents a substantive push for NP hardware, because it can be miniaturized and deployed where edge AI processing is the most bottlenecked. Moreover, PICs can be assembled at-scale (volume) without requiring expensive optical packaging [25]. Our vision and ongoing explorations are to co-integrate photonics-inside, fully-packaged ’black-box’ photonic ASIC accelerators on the same circuit boards as electronic ICs (Fig. 2(f)). This will revolutionize not only photonic AI hardware, but also ripple through the entire PIC community; offering an stand-along photonic system (including source, programmable circuit, and O-E back-end) results in an ’photonic-hidden’ module that electronic circuit designers can use as a plug-and-play design module.

4. Concluding remarks

Here we review latest advances in photonic circuits and devices for electronic-photonic ASICs for ML applications. We discuss material- and device design options, and analyze the requirements for the ML weights distinguishing between classification vs. training applications. For network edge applications with rare weight-updating, implementing non-volatile P-RAM suggest a 10-100 times higher baudrate-energy performance. Furthermore, we show examples of how the nonlinear activation function that can be efficiently realized for NP, as ITO-based modulators show great promise, being 10,000 more compact than modulators based on thin-film Lithium Niobate. Finally, we share our vision and ongoing effort of developing the first photonics-inside fully packaged photonic AI processor. This co-design strategy leverages recent developments in PWB to same-chip integrate lasers onto PICs. With this, we believe, the future for photonic-electronic ASICs is rather ’bright’ as we are just starting to explore fully co-packaged AI systems. However, CMOS foundries still do not allow materials such as PCMs and ITO, due to low demand and process compatibility issues. Future works should face these challenges while considering new materials, as some of those will be overcome by the increasing demand in photonic ASICs.