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Abstract
A nonvolatile silicon photonic switch constructed by a hybrid integration of a back-gate flash-memory unit with a silicon waveguide is proposed. It can persistently maintain the switching state without continuous supplies due to the memory function of the flash unit, which makes it attractive to reduce the static power consumption. The single-gate control configuration is replaced by dual electrodes (back-gate and drain electrodes) to break the symmetrical electric field and ensure the success of the programming/erasing process. Additionally, a monolayer graphene is utilized instead of polysilicon as the floating gate of flash unit to alleviate the bandwidth-extinction ratio restriction with low insertion loss. Depending on appropriate voltage stimulus, the device either acts as an intensity switch or a phase switch. 26.7μm length is able to achieve 20dB extinction ratio, 1.4dB insertion loss and almost no phase change in a non-resonant configuration, which allows truly broadband performance; while a π-shift is achieved by 30μm length with 31dB/1.65dB extinction ratio/insertion loss incorporating into arms of a Mach-Zehnder interferometer.
© 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
Silicon photonic integrated circuits (Si-PICs) enables electronic-photonic systems to be integrated on chip, which provides a promising solution to the von-Neumann bottleneck [1]. One of the essential building blocks is the reconfigurable silicon photonic switch; however, it requires a steady supply to maintain the switching state. Essentially, it would benefit greatly if the photonic switch has nonvolatile functionality, i.e., persistently maintain the switching state without steady supplies. Recently, the phase change material (PCM) as one of the most promising memory materials has shown its potential in nonvolatile switching [2] by phase-transition between amorphous and crystalline states. However, the transition is caused by the change of temperature, which leads to the inevitable thermal crosstalk and poor figure-of-merit (FOM), somehow, limits applications [3].
An alternative approach to achieve nonvolatile switching is to integrate silicon waveguides with the most well-established and technological-maturity flash memory unit, a key component of integrated circuits [4]. In the flash unit, the floating-gate (FG) layer inserted in the traditional transistor is utilized as a media for persistently trapping charges; then the trapped charge is enabled to modify the refractive index (RI) of FG due to the plasma dispersion effect (PDE); while FG is located in closely proximity to the silicon waveguide, consequently resulting in nonvolatile variation in optical signals transmitted in the waveguide via the near-field effect. That is, the hysteresis of flash unit enables persistently maintain the switching state. The traditional FG material is polysilicon, whose PDE is quite weak, therefore, it undergoes poor extinction ratio (ER) and high-power consumption. To some extent, combining with resonators could be a solution, however, at the expense of bandwidth [5]. Therefore, FG material with strong light-matter interaction is preferred. From Ref. [6], indium tin oxide (ITO) replaces polysilicon as FG, which requires high carrier density (around 6.5×1020 cm-3) to exhibit large bandwidth and high ER, i.e. epsilon-near-zero regime. Obviously, it is quite difficult to achieve such high density due to the operation mechanism of flash memory (tunneling processes i.e., low-number trapped charge); meanwhile, the breakdown of tunneling/blocking oxides is also a major challenge [7]. Furthermore, in the flash-memory based silicon photonic devices mentioned above, all waveguides need to be pre-doped to ensure that enough charge can be tunneled into FG, which results in additional insertion loss (IL) and imposes a major hurdle to application. Therefore, the balance of high ER and bandwidth with quite low IL is the key issue for nonvolatile silicon photonic switches.
Here, we propose a hybrid configuration of a back-gate (BG) flash memory unit integrating with a silicon-strip waveguide. The nonvolatile functionality is realized by the flash unit with a monolayer graphene working as its FG, which could lastingly trap charges without persistent supplies. From Ref. [8] a small variation of the charge in graphene could significantly and dynamically tailor the optical modes in waveguides, i.e., alter the switching states over broad spectra without requiring plasmonic resonance or other resonators to balance the ER-bandwidth trade-off due to the unique properties of graphene; therefore, it enables to achieve true broadband performance. To ensure the feasibility of the programming/erasing process, the drain and back-gate electrodes are synchronously controlled to form an asymmetric electric field in the source and drain regions, while further reducing the switch-on/off power consumption as well; additionally, the back-gate electrode is formed by another monolayer graphene to avoid extra optical loss due to its transparent property.
2. Device structure and principle
The schematic structure of the nonvolatile silicon photonic switch is shown in Fig. 1. Avail ease of fabrication and potential CMOS integration, a 220nm×400nm silicon waveguide is built on silicon-on-insulator (SOI) platform. The BG flash-memory unit consists of drain, source and BG regions, capacitively located on the silicon-strip waveguide and separated by 30nm hafnia (HfO2, buffer layer); meanwhile, in order to simplify the fabrication process, the cladding layer is the same as the buffer layer. All metallic electrodes (aluminum, Al) are lateral ∼1μm away from the waveguide to avoid extra IL [9]. A monolayer graphene as the FG is inserted between tunneling oxide (TO) and blocking oxide (BO) layers, with HfO2 as both its TO and BO layers.
Fig. 1. (a) Schematic of the nonvolatile silicon optical switch. (b) cross-section of the device with band diagrams of drain and source regions for the isolated state.
When appropriate stimulus is applied on the drain and BG electrodes, respectively, the internal electric field establish simultaneously, as shown in Fig. 2. Then, the charge could be tunneled from drain into the FG, where it remains trapped for a long period even after removing the external stimulus due to its isolated surroundings (electrically isolated from the outside, as in a deep potential valley) [10]; in the meantime, it produces an opposite mirror-imaged charge in BG, leads to a quasi-capacitance effect and further enlarges the light-mater interaction [11]. The long-period trapped charge (ΔQFG) makes the Femi level (EF) of graphene dynamically and continuously shifted away from its Dirac point (ΔEF) [12], and consequently resulting in the variation of optical modes and switching states. Therefore, the nonvolatile tuning method could be realized by properly controlling the amount of the charge tunneling into/out FG. Due to the flash-memory unit, it possesses self-holding feature as described in Ref. [2], with no static power consumption required to maintain the switching state.
Fig. 2. (a) The electrostatic potential distributions with VD= ±4 V and VG suspended, and the corresponding tunneling processes (the red-solid/blue-dash line arrow indicates the programming (J1, J2 for VD = −4 V) /erasing (J3, J4 for VD = +4 V) states. (b) The electrostatic distributions with VD=${\mp} $4 V and VG=±1.5 V, and the corresponding tunneling processes (the red-solid/yellow-dash line arrow indicates the programming (J1, J2 for VD= −4 V and VG= −1.5 V) /erasing (J3, J4 for VD= +4 V and VD= +1.5 V) states.
The performance could be qualitatively expressed by the corresponding energy band diagrams. The diagrams of the hybrid configuration in isolated and biased states are shown in Fig. 1(b) and Fig. 2, respectively. Because of the weak interaction between Al and graphene, and the work function of Al (4.2 eV [13]) is much lower than that of graphene (4.7eV [4]), which is the key to ensure the success of programming/erasing process, Al is selected as the drain/source electrode. We chose HfO2 (2.0eV [7]) because of its high dielectric constant and large bandgap; meanwhile, as demonstrated Ref. [14], the physical assembly approach could effectively integrate an ultrathin layer of HfO2 with graphene. Potential barriers (ΦB1, ΦB2) are thus formed and ensure a high enough deep valley (HfO2/graphene/HfO2) to trap charges. Meanwhile, the nonvolatile performance (reliability, etc.) depends on the band offset and the quality of oxide layers, as detailed in the following section.
Due to the conductivity of graphene, a stimulus VD is applied to the drain with a grounded source and a suspended BG, creating an electric field with mirror symmetry in both the drain and the source regions, as shown in Fig. 2(a). That is, for the programming state (VD = −4V), the tunneling current density from drain to FG J1 is much larger than that from FG to source J2 due to the barrier height (ϕB1< ϕB2). That is, electrons could successfully tunnel into FG from drain with negligible flowing out to source. However, it is difficult to erase the electrons stored in FG due to the barrier height (ϕB3< ϕB4), i.e. the tunneling out current density from FG to drain J4 is much smaller than that tunneling into FG J3. The symmetry could be broken while a BG stimulus VG is added, as the tunneling processes shown in Fig. 2(b). In which, the potential differential is asymmetric in source/FG and drain/FG, that is, the electrons tunneling into FG could be mainly avoided, i.e. J3 << J4. Considering the peculiarities of graphene, the tunneling current density should be expressed by [15]:
According to Eqs. (1), (2), the larger the field, the easier it is to inject electrons, i.e. the higher charge density and the narrower programming/erasing pulse (Δt). Meanwhile, the fields could be enhanced by increasing biases or the ratio X=εBOWGdTO /(εTOWDdBO), as shown in Fig. 3(a). Obviously, it will weaken the charge storage reliability (the breakdown of TO/BO layer is easily caused by large electric fields).
Fig. 3. (a) The electric field in drain region ED as a function of the capacitance ratio X and the external stimulus on drain VD with fixed VG = ±1.5 V for programming and erasing states. (b) ED as a function of VD and VG with fixed capacitance ratio X = 3 (as white-dash line in (a)). The light blue dash line is for program state (VD = −4.5 V, VG = +1.5 V), while the yellow-dash line is for erasing state (VD = +4.5 V, VG = −1.5 V).
From the calculation, the electrical field |ED| = 6MV/cm is large enough for tunneling into/out charges (red-dash line). As shown in Fig. 3(a), the bigger X is, the smaller VD is required. However, the average power consumption Ebit = CTΔV2/4, ΔV is the voltage offset, RT and CT are the total resistance and the total capacitance, while CT is proportional to X. Then a trade-off has to be made, X=3, dTO=5nm and dBO=10nm. The high-κ dielectric HfO2 applied as TO/BO can significantly reduce the required switching voltage and is expected to better screen charged impurities located in proximity to the graphene layer, resulting in high mobility to ensure the high-quality reliability and efficiently tunneling processes [18].
When a stimulus is added on the drain VD= −4V, the BG suspended VG and the source grounded VS = 0, the electrostatic potential is symmetrically established, as shown in Fig. 2. The following time response of current density in programming (J1, J2) and erasing (J3, J4) states could be calculated from Eq. (1). In the programming state, electrons are tunneled into FG with negligible leakage to the source (J1>> J2); however, in the erasing state, due to the existence of mirror-symmetric electric field in drain and source regions, the electron density in the FG layer gradually increases as J4<< J3, therefore, electrons are hardly erased. The symmetry could be broken by adding another stimulus VG on the BG, as shown in Fig. 2(b). Meanwhile, to prevent the charge leakage, an appropriate VG can be selected to make VFG ≈ 0. It allows the charge to be tunneled in/out in the drain region, whereas that in the source region is negligible, i.e., the charge in FG could be easily injected into FG or returned back. As the Femi level of graphene varies with the charge density ΔQFG, ΔEF = ћνF (π|QFG−Q0|)1/2, here νF=106 m/s is the Fermi velocity of Dirac fermions, Q0 is the fixed charge density (for kB<uc, the value of chemical potential uc=EF). In the meantime, the programming/erasing speed is proportional to the electric fields (voltage potential VD and VG), as shown in Fig. 3(b); however, the switching efficiency as well as the reliability should be considered. As calculated in Fig. 4(a), to ensure that enough charge is tunneled and trapped in FG, VD = ${\mp} $4.5V and VG=±1.5V are set for tunneling processes. As the electrons tunneling into FG, the electric field ED drops while QFG gradually saturates, and therefore, VFG is no longer equal to zero due to electrons stored in FG, in Fig. 4(b).
Fig. 4. (a) Time responses of the charge density and tunneling current density with different VD and fixed VG. (b) Time responses of the electric field strength across the tunnel layer in drain region and the potential for FG; the insertion figure is the relationship for the chemical potentials of FG and the charge density.
3. Results and discussion
The hysteresis of Femi level ΔEF results in nonvolatile switching of the optical transmitted states in waveguides by sweeping the drain and BG biases (VD, VG) simultaneously. The evanescent interaction of the optical signals with FG results in variations in both real (neff,r) and imaginary (neff,i) parts of the complex effective index (Δneff = neff,r+ineff,i). The real part of the index change affects the phase of the transmitted optical signal, while the imaginary part affects the signal loss. The FEM eigenmode analysis is utilized to analysis the optical mode profiles, while the anisotropic index is considered for graphene. The real part of the effective index difference Δneff,r and the mode power attenuation (MPA=10log(4πneff,i/λ)) of TM modes are simulated. As shown in Fig. 5(a), hafnia as the buffer layer shows a much better phase-change performance than other oxides, whose FOM= Δn/Δk [19] is larger while its IL is less than others with shorter length to achieve π phase-change. If the chemical potential uc swings between 0eV and 0.5eV, MPA=0.75 dB/μm an quite minimum index-to-loss ratio (Δneff,r/Δneff,i = 0.045), as shown in Fig. 5(b), (c), the corresponding energy consumption is 0.33μJ/μm. In order to clearly exhibit, the finite-difference time-domain method (FDTD Solution, Lumerical) is utilized to perform the optical transmission, as shown in Fig. 5(d). The device length is set 26.7μm for 20dB ER, whose transmission arises from 9.7% to 82.7% with almost no phase change. If uc swings between 0.5eV and 1eV, Δneff,r=0.025 with almost fixed propagation loss (∼0.05dB/μm).
Fig. 5. (a) The performance with different oxides working as the buffer layer. (b) The real part of effective index difference Δneff,r and MPA of TM as a function of the chemical potential; the insertion is the performance of optical switch with different materials as its buffer layer. (c) The length of π shift and corresponding IL for the chemical potential swings to 1 eV. (d) The FDTD simulation for beam propagations at different switch states (ON/OFF).
The intensity switch simply needs a linear waveguide geometry, while some form of interferometric scheme is required for the phase switch, such as Mach-Zehnder interference (MZI) configuration. The nonvolatile cell is integrated on both arms of the symmetrical passive MZI and separated by buffer layer. The output power of the MZI with a push-pull method, Pout = Pin (α1e-iϕ1+α2e-iϕ2), here α1=exp(-4πneff1,i L/λ) and α2=exp(-4πneff2,i L/λ) are the loss in each arm, while ϕ1 and ϕ2 are the relatively phase shift in each arm, respectively. Then the transfer function is T = Pout/Pin = α12 + α22 + 2α1α2cos(ϕ1-ϕ2), as shown in Fig. 6.
In order to maximize the ER, the loss in both arms needs to be closely matched, i.e, α1≈α2. Then, the QFG is tuned from 2.05×1013/cm2 to 8.14×1013/cm2, i.e. uc from 0.5eV to 1eV. The length for Δϕ=π, Lπ=λ/2Δneff,r=30μm is set, ER=31dB, IL=1.65dB, and the energy consumption is ∼1.2μJ/μm.
4. Conclusions
In summary, a nonvolatile silicon photonic switch combining with a back-gate flash-memory unit and a silicon waveguide is proposed. The nonvolatile functionality is achieved by adding external stimulus on dual-electrodes to break the mirror symmetry electric-field distribution. Additionally, compared with the single-gate configuration, the pre-doping is no longer needed in our device, which sufficiently reduces extra IL and simplifies the fabrication process. Furthermore, a monolayer graphene is utilized as FG to alleviate the restrictions of bandwidth and ER; while another graphene is applied as BG to further enlarges the light-matter interaction due to the quasi-capacitance of the double-layer graphene. That is, it enables a truly broadband nonvolatile switch without relying on optics or material resonances. It will benefit lots of applications in Si-PICs with nonvolatile functionality, such as tunable-delay lines, optical networks, optical phased arrays and even in advanced neural networks.
Funding
K. C. Wong Magna Fund in Ningbo University; Department of Education of Zhejiang Province (Y201940876); Natural Science Foundation of Ningbo (2019A610078); Natural Science Foundation of Zhejiang Province (LQ20F050001, LQ21F040001, LY20F050003); National Natural Science Foundation of China (61675108, 61874078, 61875098).
Disclosures
The authors declare that there are no conflicts of interest related to this article.
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