Photonic integrated circuits (PICs), enabled by the various optical integration platforms, such as the silicon-on-insulator (SOI) platform, are now used in datacom, lidar, lab-on-chip, quantum computing, optical computing, and many emerging applications. Photonic integration on the SOI platform for such applications is increasing in complexity and requires a thorough understanding of the manufacturing processes and accurate modeling of the various photonic devices used [1,2]. The most common approach to pattern devices on an SOI platform is to use deep-ultraviolet (DUV) lithography due to its popularity in large-scale, high-throughput, commercial CMOS fabrication processes [3]. However, the geometries of devices fabricated using DUV lithography may differ significantly from the design geometry due to lithography smoothing and proximity effects [4,5]. Such differences in geometries are particularly problematic for photonic devices that require relatively fine features such as Bragg grating waveguides, photonic crystals, sub-wavelength grating devices [6], and inverse design-based devices [7], among others. While new silicon photonic fabrication process nodes enable smaller feature sizes [8,9], such processes remain expensive, with long turn-around times, due to the complexity of the processes and the many masks used following the initial patterning of the silicon device layer. Additionally, designing silicon photonic devices requires more than an understanding of the fabrication limits of the process; it requires accurate modeling of the fabricated device. Therefore, it is important to understand the effects of DUV lithography on the silicon photonic devices and to compensate for such effects prior to fabrication.

Electron-beam (EBeam) lithography (EBL) is an attractive and low-cost fabrication alternative that is commonly used for rapid-prototyping and/or low-volume PIC manufacturing [10,11]. Additionally, EBL can resolve very fine silicon device features such as Bragg grating-based devices and inverse design-based devices. Due to the cost of the masks and the tools used, fabricating low-volumes of PICs using DUV lithography is often very expensive compared with EBL [5]. However, EBL may have limitations such as stitching errors and pattern density effects. Currently, DUV lithography can be done at smaller volumes and more affordable prices through the use of multi-project wafer (MPW) services, which allow designers to share the cost of a mask reticle [8]. However, such DUV lithography MPW costs and turn-around times remain high compared with fabricating PIC prototypes using EBL.

Understanding the effects of DUV lithography is critical when designing devices and systems to be manufactured using such fabrication processes. In previous work, we have shown that it is possible to predict and simulate such effects by developing a computational lithography model that predicts the fabricated device geometry when DUV lithography is used [5]. While such predictive models are important in designing for DUV lithography, it can be challenging and impractical to model the complete optical performance of larger systems consisting of many devices, some of which may be susceptible to DUV lithography effects. To minimize the risk of using new and untested devices with a DUV lithography process, it is important to know a priori how the as-fabricated PIC will perform. One approach is to use a high-resolution process together with a predictive model for the DUV lithography process to experimentally verify the PICs performance.

Hence, in this work, we present a design flow that uses a predictive, computational DUV lithography model and a rapid-prototyping EBL fabrication platform in which the computational lithography model predicts the effects of the DUV lithography and the EBeam fabrication ensures that the post-DUV device geometries are faithfully emulated on an experimental prototype. Using Bragg grating-based devices as demonstration cases, we experimentally show that the emulated devices’ performances, fabricated using EBL, closely match the performances of the devices fabricated by the DUV lithography process.

The computational lithography model was developed using the available parameters provided by the foundry for the 193-nm DUV dry lithography process used in this work and feature size measurements using scanning electron microscopy (SEM) images of a set of fabricated test patterns (see [5]) that were, in turn, used to extract estimates of the process parameters not provided by the foundry. We used the test pattern set, consisting of 216 structures recommended by the lithography tool to extract the critical dimensions that are required to build the model. These structures included isolated lines with varying pitches, and isolated silicon islands and holes with varying radii. The model parameters were optimized such that the errors between the predicted feature sizes and the measured feature sizes were minimized. As the model was built using fabricated test patterns, it was foundry-process-specific and is based on the model presented in [5]. However, our methodology in building the model can be applied to any foundry process [5].

The periodic perturbations in a Bragg grating waveguide can be engineered to design wavelength-selective reflectors with central wavelengths and bandwidths determined by the ’strengths’ of the perturbations. The bandwidth ($\Delta \lambda$) of a Bragg grating waveguide can be determined by [12]

The EBL foundry used for the demonstration of our work is AppliedNanotools which uses a JEOL JBX-81OOFS EBL system. The computational lithography model used was developed for the Advanced Micro Foundry 193-nm DUV dry lithography process to pattern the silicon device layer, enabling minimum features down to 120 nm [8]. All of the devices presented in this work were tested using near-vertically coupled grating couplers designed for the C-band and for the TE polarization.

Bragg grating devices were used as cases to evaluate the accuracy of the DUV lithography emulation. The designed Bragg gratings are silicon strip waveguides (220 nm thick) with rectangular, periodic sidewall corrugations [shown in the legend of Fig. 1(b)]. Such sidewall-corrugated Bragg grating devices were used because they are particularly susceptible to DUV lithography smoothing effects. We used a 3-dB Y-splitter at the input (output) of a Bragg grating waveguide to obtain the reflected signal. While the corrugation widths vary, all of the Bragg grating devices shown in this work use strip waveguides with average widths of 500 nm, grating periods of 318 nm, and are 300 Bragg periods long. Figure 1(a) shows the reflection spectrum of a Bragg grating waveguide (with 35-nm-wide corrugations) as modelled using the transfer matrix method (in which the coupling coefficient was obtained using 3D finite-difference time-domain simulations) [15] and as measured after fabrication through a 193-nm DUV lithography process. A significant reduction in the bandwidth of the Bragg grating can be seen when comparing the ideal, simulated device with the device fabricated using the DUV process. The reduction in bandwidth can also be seen for other corrugation widths, as shown in Fig. 1(b). As expected, larger corrugation widths result in wider bandwidths due to the increased coupling coefficients. Therefore, a thorough understanding of the lithography effects is critical for first-time-right design of Bragg grating devices when using a DUV lithography process.

 

Fig. 1. (a) Reflection spectra of Bragg grating strip waveguides as-designed (simulated) and as-fabricated using a DUV lithography process (measured). (b) Bandwidths of various Bragg gratings with increasing corrugation widths as-designed (simulated) and as-fabricated using a DUV lithography fabrication process (measured).

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To emulate the optical performance of Bragg grating devices fabricated using a DUV lithography process, we mimic the devices using a rapid-prototyping EBL process. We create a design-of-experiment in which a set of Bragg grating devices with increasing corrugation widths are fabricated using both the EBeam and the DUV lithography processes. Two sets were fabricated on the EBeam process, a set in which the Bragg grating devices were made “as-designed,” and a set in which the Bragg grating devices were made with the computational lithography model predicted geometry. Shown in Fig. 2, we applied the computational lithography to the ideal “as-designed” geometry of a typical Bragg grating with 35-nm-wide corrugations, shown in Fig. 2(i). The output of the computational lithography model [shown in Fig. 2(ii)] is then fabricated using the EBeam process. Figure 2(iii) is an SEM image of the “as-designed” Bragg grating fabricated using the EBeam process, and it shows the high degree to which the rectangular profile of the corrugations is resolved. Figure 2(iv) is an SEM image of the DUV-emulated device geometry as fabricated using the EBeam process. It can be seen that the DUV-emulated device geometry closely matches that of the geometry of the Bragg grating fabricated using the DUV process shown in Fig. 2(v).

 

Fig. 2. Comparison of the geometries for a Bragg grating waveguide. (i) As designed geometry. (ii) Predicted geometry based on the computational lithography model output. (iii) SEM image of the fabricated “as-designed” device using EBL. (iv) SEM image of the DUV-emulated device fabricated using EBL. (v) SEM image of the device fabricated using DUV lithography.

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The reflected spectra of the Bragg grating devices shown in Fig. 2(iii)–(v) were then measured. For the three Bragg grating devices designed with 35-nm-wide corrugations, the reflection spectra for the devices are shown in Fig. 3(a). It can be seen that Bragg bandwidth of the EBeam-fabricated, “as-designed” geometry (15.4 nm) is nearly twice that of the DUV-fabricated device (7.4 nm). It can also be seen that the bandwidth of the DUV-emulated device (7.3 nm), fabricated using EBL, closely matches that of the DUV-fabricated device. Figure 3(b) shows that this relationship holds for other Bragg grating devices with varying corrugation widths.

 

Fig. 3. (a) Experimental measurement of the reflection spectra of fabricated Bragg grating devices (for one design) as fabricated using a DUV process (solid blue), an EBeam process (solid red), and an EBeam process with the DUV emulation applied (dot–dashed green). (b) Bandwidths of Bragg gratings with increasing corrugation widths as simulated (dashed red line), as simulated using the predicted geometry (dash–dot blue line), as fabricated using a DUV lithography process (blue cross points), as fabricated using an EBeam process (red dot points), and as fabricated using an EBeam process with the DUV emulation applied (green dot points).

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We then used the same computational model on another type of device, the contra-directional coupler (contra-DC). A contra-DC is a four-port, wavelength-selective, add-drop filter [13,16]. The device is made using two Bragg grating-based, asymmetric waveguides that are coupled evanescently, as shown in Fig. 4(a)(i). Such devices can be used to create low-loss, wideband add-drop filters on silicon for many applications and can be designed to work when using DUV processes [17]. In addition to the lithography smoothing effects that reduce the strengths of the gratings and narrow the bandwidth, due to the narrow gaps between the two coupled waveguides, the contra-DC device is also susceptible to lithography proximity effects that have different impacts on the inner and outer gratings of the waveguides [5].

 

Fig. 4. (a) Comparison of the geometries for a contra-directional coupler device. (i) As designed geometry. (ii) Predicted geometry based on the computational lithography model output. (iii) SEM image of the fabricated “as-designed” device using EBL. (iv) SEM image of the DUV-emulated device fabricated using EBL. (v) SEM image of the device fabricated using DUV lithography. (b) Comparison of the filter bandwidths of various contra-directional coupler devices with an increasing gap as simulated (dashed red line), as simulated using the predicted geometry (dash–dot blue line), as fabricated using a DUV lithography process (blue cross points), as fabricated using an EBeam process (red dot points), and as fabricated using an EBeam process with the DUV emulation applied (green dot points).

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For this demonstration, we created a similar design-of-experiment in which a set of contra-DC devices (using the design parameters reported in [18]) with increasing minimum gaps [shown in Fig. 4(a)(i)] is fabricated by both the EBeam process and the DUV process. Increasing the gap between the two coupled waveguides results in a reduced filter bandwidth due to the reduced coupling coefficient that is a function of the modal overlap between the two waveguides [13]. Figure 4(a) compares the designed device (i) with the predicted geometry based on the computational lithography model (ii). The fabricated “as-designed” geometry is shown in (iii) and (v) for the EBL process and the DUV lithography process, respectively. The emulated geometry fabricated using the EBL process is shown in (iv). The devices in each set were then measured, and the bandwidth of each is shown in Fig. 4(b). As predicted, due to the lithography effects, the bandwidths of the contra-DC devices fabricated using the DUV process are much narrower than those of the “as-designed” devices fabricated using the EBeam process. It can be seen that the bandwidths of the emulated devices fabricated using the EBL process much more closely match the bandwidths of the devices fabricated using the DUV lithography process.

In conclusion, we present a design flow that uses a predictive, computational DUV lithography model to emulate the optical performance of silicon photonic devices fabricated using an advanced 193-nm DUV dry lithography process. The emulated devices are fabricated using a rapid-prototyping EBL fabrication process. Using our design flow, we have demonstrated that the performance of devices particularly susceptible to optical lithography effects, such as Bragg grating waveguides and Bragg grating-assisted optical add-drop filters, can be accurately and experimentally emulated using an EBL process. Our method can be applied to emulate the behavior of other optical devices that present design challenges for fabrication using optical lithography processes, such as inverse-designed devices and photonic crystals, to achieve first-time-right designs. Further work is required to capture and mitigate additional fabrication-induced effects such as surface roughness [11] and sidewall angle, among others.