Open Access
Add to BibSonomy
Abstract
This paper presents a clock conversion scheme for burst-mode digital coherent QPSK receivers in an asynchronous PON upstream and confirms its validity. The scheme converts the number of samplings of transmitted signal based on the clock at Rx. We demonstrate the proposed scheme in a realistic environment that emulates a fixed clock difference by two independent synthesizers at Tx and Rx mixed together with clock jitter induced by 20-km fiber transmission. In the real-time demonstration, a digital coherent receiver employing the proposed clock conversion successfully receives 330-µs burst QPSK frames over 20-km transmission in the presence of a 100-ppm clock mismatch.
© 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
Whether it is to improve the capacity of the high-speed mobile fronthaul/backhaul or to extend the optical reach to reduce the operation and maintenance costs, applying digital coherent detection to benefit from its high sensitivity is an attractive option for access networks [1,2]. In access networks that employ time division multiplexing - passive optical networks (TDM-PONs) such as in the current Fiber-to-the-Home (FTTH) or most PON standards including the upcoming 50G-EPON in IEEE and High speed PONs (HSP) in ITU-T, the receiver (Rx) on the optical line terminal (OLT) side must be able to deal with burst-mode signals [3,4]. Although the fundamental methodology of digital coherent technology is already established and Rxs are now commercialized, they unfortunately do not cover burst-mode operation because digital coherent detection was originally developed assuming a long-haul system in continuous-mode operation [5,6].
Several studies have attempted to implement burst-mode digital coherent reception. They mainly focus on improving response times of components (ex. switching of wavelength tunable lasers used as local oscillators (LOs) [7]) and functions (ex. I/Q imbalance compensation [8] and adaptive equalization filter [9]) that are needed for general digital coherent reception. To cover another specific requirement for burst-mode digital coherent reception other than the rapid response time, which is leveling the burst signals before input to ADCs [10], optical pre-amplifiers [11] and LO followed by variable optical attenuator (VOA) [12] that offers auto gain control functionality have been developed. Furthermore, optimal preamble design [13,14] and CMOS ASIC implementation [15] have been studied. Some of the works presented above described real-time demonstrations [11,14].
A challenge to realizing a burst-mode digital coherent receiver is allowing asynchronous-operation of the transmitter (Tx) and Rx. Although burst-mode clock data recovery (CDR) designed for non-return-to-zero (NRZ) signals is implemented in currently deployed PONs [16], an equivalent function for phase shift keying (PSK) signals is needed for digital coherent systems because being able to obtain not only amplitude information but also waveform information using PSK is another advantage of digital coherent detection other than the high sensitivity, which most digital coherent systems try to benefit from.
Sampling synchronization of digital coherent Rxs for continuous-mode systems such as long-haul systems has been established. One representative technique that detects timing error is zero-crossing (ZC) detection; it uses zero-crossing points as an indicator to find the timing errors [17]. A general approach to compensating the detected timing errors is to set a feedback circuit in the Rx that adjusts the sampling rate of analog-to-digital converters (ADCs) to correspond to the clock frequency extracted from the transmitted signal [5,18]. Although this approach can recover large clock differences, they are not suitable for burst-mode systems due to their inadequate response speeds [7,19]. To realize burst-mode operation, interpolation or up-sampling has been utilized to increase the number of sampling points and find the optimal sampling timing [20]. Although it has been confirmed to work in a real-time demonstration, it is inherently unable to compensate large clock mismatch. It is also reported that adaptive finite-impulse-response (FIR) filter has ability to recover the clock mismatch [21]. However, it needs a large number of taps to handle severe clock mismatch which complicates implementation.
In our previous work, we proposed a clock conversion scheme for the burst-mode digital coherent Rx that offers rapid response and high clock mismatch tolerance [22]. Our proposal introduces maximum likelihood (ML-) type timing error detection to improve the response speed against a ZC-type system [19]. After ML-type timing error detection, the sampling sequence is regenerated by directly manipulating the number of incoming samples. This process can handle severe clock mismatch. We confirmed its feasibility with a real-time back-to-back demonstration that emulated a fixed clock difference between Tx and Rx [22]. In this paper, we add a detailed explanation about the impact of clock mismatch on system performance and the behavior of our proposed scheme. In addition, for a more practical performance evaluation than that in [22], we test the proposed scheme by adding the clock jitter induced by 20-km fiber transmission. Since our real-time digital signal processing (DSP) includes a 9-tap adaptive FIR filter with constant modulus algorithm (CMA) to compensate temporal impairments such as chromatic dispersion, we also show performance comparisons of the adaptive FIR filter and the proposed scheme.
The remainder of this paper is organized as follows. Section 2 describes the effects of clock mismatch on system and details our proposed clock recovery scheme. Section 3 introduces the real-time experimental setup used to evaluate clock mismatch tolerance. Section 4 summarizes and discusses the results of the demonstration. Finally, Section 5 concludes the paper.
2. QPSK burst-mode coherent receiver for an asynchronous system
2.1 Clock mismatch in a QPSK system
When clock mismatch between Tx and Rx exists, the symbol rate in Tx, STx, differs from that in Rx, SRx. As a result, the Rx recognizes more or fewer symbols than the actual number of symbols transmitted. We define here the difference in the numbers of symbols the Tx transmits and that the Rx recognizes within a burst frame as integer ΔNS; it is nearly equal to Lf (SRx - STx), where Lf is the burst frame length. ΔNS >0 means that the Rx recognizes more symbols than sent and the converse is also true. Impact of clock mismatch on system performance is determined by ΔNS, and shortening the frame length helps to ease the problem. However, shortening the frame length significantly is not a good solution since it degrades transmission efficiency.
Clock recovery is generally done using the samples output by the ADCs. Sampling timings of the ADCs are given by
where k=0,1,2…, m=0,1,2, …, M-1, TS is symbol duration, 1/SRx. This case indicates M times oversampling. The sampled value that is output at tk, m is u(k, m). A symbol is sampled M times in TS. For the same k, one of u(k, m)s is closest to the symbol point and remaining values are transition points. Term m, where u(k, m) is nearest to the symbol point, is called the optimal sampling timing or symbol timing. Their relationships are summarized in Fig. 1. A sinusoidal waveform is utilized for simplicity and M=3 in this figure. The rectangle blocks and the colored blocks depict sampled value u(k, m) and symbol timings, respectively.When interpolation or up-sampling is used to address clock mismatch, M is increased after the ADC, and the best symbol timing is chosen from the samples [20]. Those schemes presuppose that the total number of symbols per burst frame is the same at the Tx and Rx, i.e., |ΔNS|<1. In addition, its performance strongly depends on ADC sampling phase; there are the best case and the worst case whose performances are quite different under the same condition. The adaptive FIR filter can improve the clock mismatch tolerance and make the system insensitive to the initial sampling phase of the ADCs [21]. The clock mismatch tolerance of the adaptive FIR filter is determined by the number of taps, p, and M. The adaptive FIR filter absorbs the clock mismatch by shifting tap coefficients, w, as the sample timings shift. The allowed time delay that can be offset by w is p(Ts/M) as shown in Fig. 2 and the clock mismatch tolerance is -p/2M <ΔNS<p/2M. Although increasing M generally improves performance of the adaptive FIR filter, the number of taps has to be also increased in order to maintain the clock mismatch tolerance and it needs larger circuit size. Thus, p and M should be designed by trade-off between the required clock mismatch tolerance and the circuit size.
Fig. 2. Adaptive FIR filter. D: time delay of Ts/M, w: tap coefficients, e: error value, d: desired value.
Unlike the feedback circuit that adjusts the ADCs in Rx to suit Tx clock frequency, which is undoubtedly one variant of “clock recovery,” the two above methods convert the symbol timing of the transmitted signal to suit Rx clock frequency, and so is called “clock conversion.”
2.2 Proposed clock conversion
Our clock conversion proposal consists of two parts; timing error detection and sampling sequence regeneration. More details of each part beyond that in [22] is presented here.
As the first step of clock conversion, timing errors have to be detected. We employ ML-type estimation to improve the response speed [19]. The symbol timing is approximated by identifying n where
Here, b-a is the length of the window used to calculate accumulated value σ(m). Searching for symbol timing n corresponds to searching for an eye opening in the case of NRZ and n is utilized as an indicator to detect when timing errors occur. Figure 3 shows the behavior of n. Three times oversampling is assumed in this figure based on the real-time experimental setup described in Section 3. Although higher oversampling leads to more precise compensation of clock mismatch, the proposed clock conversion should, in principle, work with two times oversampling. In case 1, STx=SRx, n does not vary and the symbol timings appear at a constant interval, three samples in this case, which is derived from three times oversampling, as Fig. 1. In case 2, STx>SRx, the symbol timings appear at shorter intervals than expected, as Fig. 3(a). Then, n changes from 0 to 2, 1 to 0, or 2 to 1. In case 3, STx<SRx, the symbol timings appear at longer intervals than expected and n changes from 0 to 1, 1 to 2, or 2 to 0, as Fig. 3(b). Thus, we can detect the timing errors by tracking the change in n.Fig. 3. Behavior of n in the first step of clock conversion; timing error detection. Case 1: STx=SRx is shown in Fig. 1. (a) Case 2: STx>SRx, (b) Case 3: STx<SRx.
Note that we discussed clock conversion deriving the symbol timing here, but actually we down-sample u(k, m) in the CMA adaptive filter. This is in order to benefit fully from the ability of the CMA adaptive filter to compensate temporal impairments.
In the second step of the proposed clock conversion, the sampled value sequence u(k, m) is manipulated so that the symbol rate of the transmitted signal matches SRx, according to the timing errors detected in the first step. In case 2, the changes in n (0 to 2, 1 to 0, or 2 to 1) are recognized as a “shortage” in the number of samples within TS. Then, in order for this sample sequence to correspond to SRx, samples are added. The actual processes are 1) copy a sample and insert it into the sequence and 2) delay the subsequent samples accordingly for a sample duration, as shown in Fig. 4(a). In case 3, the converse process is performed. The changes in n (0 to 1, 1 to 2, or 2 to 0) are recognized as a “surplus” in the number of samples within TS. Thus, the number of samples is reduced. The actual processes are 1) eliminate a sample from the sequence and 2) advance the following samples accordingly for a sample duration, as shown in Fig. 4(b). The result is that the symbol rate of the transmitted signal corresponds to SRx and clock conversion is achieved. We can confirm that from the symbol timings that appear every three samples in both cases.
Fig. 4. The second step of clock conversion; sampling sequence regeneration. (a) Case 2, (b) Case 3.
To implement the “delay” and “advance” processes, a register to store the sample sequence is required. The clock mismatch tolerance is determined by the number of the samples that the register can store. For a severe clock difference, a large register is needed just as a large number of taps are needed in the adaptive FIR filter. Nonetheless, increasing register size in the proposal incurs a much smaller load for the circuit than increasing the number of taps in the adaptive FIR filter.
3. Real-time platform with a clock mismatch
The implemented real-time experimental configuration used to evaluate the proposed clock conversion is depicted in Fig. 5. The left and right sides show Tx and Rx, respectively. A variable optical attenuator (VOA) that emulates the power loss caused by power splitters and 20-km single mode fiber (SMF) connect the Tx and Rx sides as the transmission medium. Two independent synthesizers in Tx and Rx emulate a fixed clock difference. Since they are not synchronized using a low frequency clock reference, there is additional low clock jitter due to their individual differences.
The synthesizer for the Tx is adjusted to emulate an arbitrary clock difference and provides its clock to the frame generator to generate two frame pulses whose symbol rate is STx. The frame carries a $3.84 \times {10^4}$-symbol preamble (approx. 1.2%), a $3.2512 \times {10^6}$-symbol payload (approx. 98.4%), and a $1.28 \times {10^4}$-symbol end-of-burst (EOB) period (approx. 0.4%). The given percentages present occupancies of the whole frame, which is 330.24 µs when the transmitted signal is 10 GSymbol/s. The preamble length generally affects transmission efficiency because the payload has to be shortened if long preamble is required for a determined whole frame length. It should be noted that the proposed clock conversion is based on feedforward compensation and does not have feedback loop or other factors that need uncertain convergence time or set time. The calculation time of signal processing in the proposed clock conversion is mainly determined by three factors: 1) implementation configuration, 2) required clock mismatch tolerance and 3) whole frame length. In the case of our FPGA, it takes 10 clocks with 117-MHz clock, approximately 8.5 ns. We think this calculation time is negligibly short for 330-µs frame and does not affect the preamble length or transmission efficiency. The payload is a pseudo-random bit sequence (PRBS) of ${2^7} - 1$. The interval between frames is set assuming the same frame length for another ONU and the guard time between the frames is 2304 symbols. The frame generator provides these frame pulses to the IQ modulator to generate a QPSK signal, and a gate signal to the SOA as a shutter to generate the burst signals.
Burst frames generated in the SOA are transmitted to the Rx via the VOA, which emulates a power loss caused by optical power splitters and other network elements, and 20-km of SMF to confirm the tolerance of the proposed clock conversion against the low clock jitter created by fiber transmission.
In the burst-mode Rx, the synthesizer is set to 15.000 GHz throughout the experiments and its clock is provided to the two 30-GSa/s ADCs, the FPGA board, and the error detector (ED) via the clock distributer & divider to satisfy the allowed input clock range of each device. The Rx is designed to demodulate 10-Gsymbol QPSK signals by this 15.000 GHz setting. The burst frames that arrive at the Rx must be leveled before they are input to the ADC to fully utilize its resolution [10,11]. Although some methods have been reported that automatically maintain the output power of the digital coherent Rx at approximately a constant level [11,12], we adjusted the local oscillator (LO) power manually using the other VOA in the experiments. The lasers in the Tx and Rx are the same-model external cavity lasers (ECLs) with linewidth of 15 kHz. Although the polarization is controlled manually because the DSP in this system handles only single polarization, a practical system would utilize established DSPs that support polarization diversity [5,18].
The real-time signal processing done in the FPGA is shown in Fig. 6(a). The first block of frame detection (FD) which is not required in the continuous system finds the start and end of each burst frame. Clock conversion is indicated by the second colored block, and comprises timing error detection and sampling sequence regeneration as illustrated in Fig. 6(b).
Since the Rx is designed to demodulate 10-Gsymbol/s signals and the sampling rate of the ADCs is 30 GSa/s, the input signal is processed with three-times oversampling. We did not use interpolation in this experiment. The FD monitor signal is output from the FD block and sent to the frame generator (FG) which generates a gate signal for the error detector (ED) to count only errors in the payload. Although frequency offset and laser phase noise which rotate phase of signals are compensated in the carrier phase recovery part after the proposed clock conversion, there is almost no impact of them on the clock conversion because the timing error detection is based on ML-type and does not utilize the rotated phase information but uses only amplitude information of the signals as Eq. (2)-(4). As for inter-symbol interference (ISI), its impact on the system is also compensated after the proposed clock conversion in the adaptive filter (CMA) part. If the timing error detection part can find the symbol timing using Eq. (2)-(4) under the impact of the ISI, the clock conversion works. The real-time signal processing is done and the results are updated every clock of 117 MHz while signals are transmitted. The clock mismatch that changes over time can be tracked and compensated by this real-time signal processing.
4. Experimental results and discussion
4.1 Effects of a clock mismatch
First, we measured bit error rate (BER) of real-time transmission without the proposed clock conversion increasing the clock mismatch by 0.1 ppm to quantify the relationship between clock mismatch and system performance. We performed the experiment several times but results were inconsistent. Some results were reproducible but some results were not depending on the clock mismatch condition. Figure 7 shows only the consistent results. For clock mismatch values from 0 ppm to 0.2 ppm, the BERs falls rapidly. Although an error floor is observed below the BER of 10−4 at 0.2 ppm, there is only 0.5-dB penalty against the results at 0 ppm in the sensitivities at the BER of 10−3. After 0.7 ppm, the BER deteriorates dramatically against the results at 0.2 ppm and 10−2 is not attainable. From 0.3 ppm to 0.6 ppm, we could not acquire consistent results as mentioned above. For the same clock mismatch, the BER sometimes behaves as that at 0.2 ppm and at other times as that at 0.7 ppm. These results were too unreliable for inclusion in the figure.
We found that the results in Fig. 7 can be explained as follows. The system employs the adaptive FIR filter with CMA which should be able to compensate moderate clock mismatch [21]. The system uses three-times oversampling and the number of taps in the filter is nine which is supposed to yield the clock mismatch tolerance of |ΔNS|=1. Lf of our system is approximately 330 µs and the clock mismatch where ΔNS=1 is approximately 0.3 ppm.
The results in Fig. 7 wherein the 0.2-ppm clock mismatch is mitigated are consistent with the estimation. As for the range of 0.3 ppm to 0.6 ppm, although no compensation is supposed to be applied according to the above estimation, the adaptive filter sometimes happens to be able to compensate them. This may be due to some variable factors in the system such as initial sampling phase in the ADCs that happened to work advantageously in compensating clock mismatch. These are not reproducible results as mentioned above and certainly should not be included in the system design. The BER deteriorates consistently beyond 0.7 ppm. This is explained by noting that ΔNS=2 occurs between 0.6 ppm and 0.7 ppm.
From Fig. 7 and the estimation results, we conclude that the adaptive FIR filter without clock conversion can compensate for moderate clock mismatch and its limit is determined by the number of taps and Lf.
4.2 Proposed clock conversion with a 20-km transmission
Next, we measured the BER of the real-time 20-km transmission with the proposed clock conversion. The results are shown in Fig. 8. The results of 0 ppm without clock conversion, taken from Fig. 7, are shown as a reference. The BERs at 0.2 ppm, 0.7 ppm and 100 ppm fall below 10−3, which is the conventional FEC limit. 100 ppm with 10-Gsymbol/s and 330-µs frame corresponds to approximately |ΔNS|=330. Overall, the proposed clock conversion well mitigates the clock mismatch that the adaptive FIR filter could not. We confirm that the proposed clock conversion enables successful reception of the burst signal at the Rx in the presence of severe clock difference from two independent synthesizers and the low clock jitter induced by fiber transmission. On the other hand, while the BER at 0.2 ppm without the clock conversion incurs only 0.5-dB penalty against the BER at 0 ppm, see Fig. 7, the BER at 0.2 ppm with the clock conversion incurs an approximate 2.3-dB penalty. In addition, the BER at 100 ppm is improved from that at 0.2 ppm or 0.7 ppm, and incurs an approximate 0.9-dB penalty against that at 0 ppm. From those results, we can see that the proposed clock conversion is better at compensating large clock mismatch than small clock mismatch. It can be explained as that fluctuations across zero of the detected clock mismatch that is induced by quantization error of the calculation process in the proposed clock mismatch especially degrades the BER. In that situation, STx>SRx and STx<SRx (cases 2 and 3 in Fig. 3) alternately appear in the timing error detection and the following sampling sequence regeneration part has to alternately process as cases 2 and 3 in Fig. 4. We consider that this kind of behavior is what especially degrades the BER of the system with the proposed clock conversion. The “fluctuations across zero of the detected clock mismatch” could often occur when the actual clock mismatch is small while that would not occur when the actual clock mismatch is sufficiently large. The BER performance would be improved by switching on/off of the proposed clock conversion depending on the clock mismatch.
5. Conclusion
We presented a clock conversion scheme for burst-mode digital coherent QPSK receivers in asynchronous PON upstream and confirmed its validity. Our proposed clock conversion offers strong clock mismatch tolerance that enables transmission with long burst frame lengths even in the presence of severe clock mismatch. We presented the results of a real-time demonstration that set a severe fixed clock difference emulated by two independent synthesizers and a low clock jitter caused by 20-km fiber transmission. The results confirmed that a digital coherent receiver employing the proposed scheme successfully received 330-µs burst-mode QPSK frames in the presence of 100-ppm clock mismatch after 20-km transmission. Finding the symbol timing in a better granularity by increasing the sampling rate of the ADC or by using the interpolation in an allowed circuit size and device cost would improve the clock conversion performance.
Acknowledgments
The authors thank H. Mori and S. Yokoyama for helpful discussions.
Disclosures
The authors declare no conflicts of interest.
References
1. Y. Zhu, B. Yang, Y. Zhong, Z. Liu, Y. Guo, J. Wey, X Huang, and Z. Ma, “Performance comparison of coherent and direct detection schemes for 50G PON,” in Proc. of Optical Fiber Communication Conference (OFC), paper W1E.3 (2020).
2. J. Zhang, Z. Jia, H. Zhang, M. Xu, J. Zhu, and L. A. Campos, “Rate-flexible single-wavelength TFDM 100G coherent PON based on digital subcarrier multiplexing technology,” in Proc. of Optical Fiber Communication Conference (OFC), paper W1E.5 (2020).
3. IEEE 802.3ca 50G-EPON Task Force http://www.ieee802.org/3/ca/
4. ITU-T G.9804.1 Higher speed passive optical networks – Requirements https://www.itu.int/itu-t/recommendations/rec.aspx?rec=14024
5. M. Kuschnerov, F. N. Hauske, K. Piyawanno, B. Spinnler, M. S. Alfiad, A. Napoli, and B. Lankl, “DSP for coherent single-carrier receivers,” J. Lightwave Technol. 27(16), 3614–3622 (2009). [CrossRef]
6. N. Iiyama, M. Fujiwara, T. Kanai, J-I, Kani, and J. Terada, “The approaches of coherent technology for TDM-PON,” in Proc. of European Conference and Exhibition on Optical Communications (ECOC), paper M.1.F (2019).
7. R. Maher, D. S. Millar, S. J. Savory, and B. C. Thomsen, “Widely tunable burst mode digital coherent receiver with fast reconfiguration time for 112 Gb/s DP-QPSK WDM networks,” J. Lightwave Technol. 30(24), 3924–3930 (2012). [CrossRef]
8. R. Matsumoto, K. Matsuda, and N. Suzuki, “Fast, low-complexity widely-linear compensation for IQ imbalance in burst-mode 100-Gb/s/λ coherent TDM-PON,” in Proc. of Optical Fiber Communication Conference (OFC), paper M3B.2 (2018).
9. R. Koma, M. Fujiwara, J.-I. Kani, K.-I. Suzuki, and A. Otaka, “Burst-mode digital signal processing that pre-calculates FIR filter coefficients for digital coherent PON upstream,” J. Opt. Commun. Netw. 10(5), 461–470 (2018). [CrossRef]
10. A. Teixeira, D. Lavery, E. Ciaramella, L. Schmalen, N. Iiyama, R. M. Ferreira, and S. Randel, “DSP enabled optical techniques for PON,” J. Lightwave Technol. 38(3), 684–695 (2020). [CrossRef]
11. R. Koma, M. Fujiwara, J.-I. Kani, S.-Y. Kim, T. Suzuki, K.-I. Suzuki, and A. Otaka, “Demonstration of real-time burst-mode digital coherent reception with wide dynamic range in DSP-based PON upstream,” J. Lightwave Technol. 35(8), 1392–1398 (2017). [CrossRef]
12. S.-Y. Kim, J.-I. Kani, K.-I. Suzuki, and A. Otaka, “OLT receiver for power normalization of burst OFDM signals enabling OFDM/TDMA-PON,” IEEE Photonics Technol. Lett. 26(24), 2469–2472 (2014). [CrossRef]
13. J. Zhang, Z. Jia, M. Xu, H. Zhang, L. A. Campos, and C. Knittle, “High-performance preamble design and upstream burst-mode detection in 100 -Gb/s/λ TDM Coherent-PON,” in Proc. of Optical Fiber Communication Conference (OFC), paper W1E.1 (2020).
14. F. Vacondio, C. Simonneau, A. Voicila, E. Dutisseuil, J. M. Tanguy, J. C. Antona, G. Charlet, and S. Bigo, “Real-time implementation of packet-by-packet polarization demultiplexing in a 28 Gb/s burst mode coherent receiver,” in Proc. of Optical Fiber Communication Conference (OFC), paper OM3H.6 (2012).
15. B. C. Thomsen, R. Maher, D. S. Millar, and S. J. Savory, “Burst mode receiver for 112 Gb/s DP-QPSK with parallel DSP,” Opt. Express 19(26), B770–B776 (2011). [CrossRef]
16. J. Terada, K. Nishimura, S. Kimura, H. Katsurai, N. Yoshimoto, and Y. Ohtomo, “A 10.3125Gb/s burst-mode CDR circuit using a δσ DAC,” in Proc. of IEEE International Solid-State Circuits Conference (ISSCC) 2008, 226–609 (2008).
17. F. M. Gardner, “A BPSK/QPSK timing-error detector for sampled receivers,” IRE Trans. Commun. Syst. 34(5), 423–429 (1986). [CrossRef]
18. K. Kikuchi, “Digital coherent optical communication systems: fundamentals and future prospects,” IEICE Electron. Express. 8(20), 1642–1662 (2011). [CrossRef]
19. S. Sampei and K. Feher, “Improvement of delay spread immunity by using symbol timing synchronization based on maximum likelihood estimation for 16QAM/TDMA diversity receivers,” Electron. Lett. 29(22), 1917–1918 (1993). [CrossRef]
20. F. Vacondio, C. Simonneau, A. Voicila, J. -M. Tanguy, G. de Valicourt, E. Dutisseuil, L. Lorcy, J. -C. Antona, G. Charlet, and S. Bigo, “Experimental demonstration of a PDM QPSK real-time burst mode coherent receiver in a packet switched network,” in Proc. of European Conference and Exhibition on Optical Communications (ECOC), paper Tu.3.A.1 (2012).
21. K. Kikuchi, “Clock recovering characteristics of adaptive finite-impulse-response filters in digital coherent optical receivers,” Opt. Express 19(6), 5611–5619 (2011). [CrossRef]
22. N. Iiyama, M. Fujiwara, T. Kanai, H. Suzuki, J-I. Kani, and J. Terada, “Real-time demonstration of 20-Gb/s QPSK burst-mode digital coherent reception for PON upstream under clock frequency mismatch of 1.0 MHz,” in P roc. of Optical Fiber Communication Conference (OFC), paper W1E.4 (2020).
