1. Introduction

Integrated thermo-optic phase-shifters (TOPS), or optical waveguide heaters, have become widely employed in applications ranging from sensing to switching, advanced communications and neural networks [1–4], and on various platforms [5,6]. On silicon-on-insulator (SOI), increasingly popular for its compact devices, large wafers, low cost, high yields and complementary metal oxide semiconductor (CMOS) compatibility [7,8], heaters are now routinely embedded in the design of more complex devices and sub-systems such as ring resonators/modulators [9,10], Mach-Zehnder interferometers (MZIs) and Mach-Zehnder modulator (MZM) arrays [11]. Active ring-based devices typically have small footprint and low power consumption, and several SOI TOPS designs targeted at these devices were proposed lately [12–18]. However, the wavelength selectivity, thermal sensitivity and poor fabrication tolerance of ring structures explain why MZI-based (or other interferometric) designs are often preferred [19].

A summary of recently published SOI TOPS designs embedded in interferometric structures is presented in Table 1 [19–24]. MI and MZI are respectively Michelson and Mach-Zehnder interferometers,$V_{\pi }$and$P_{\pi }$are the voltage and electrical power leading to the temperature change$\Delta T_{\pi }$required in the optical waveguide for a $\pi$-shift, and$\tau$is the 1/e limiting time constant of heat diffusion (rise or fall). The figure of merit (FOM)$P_{\pi }\cdot \tau$, to be minimized, is accepted as a global heater performance measure [19,20]. The two best published designs in terms of this FOM employ respectively a doped-Si heater embedded directly in the optical waveguide [19] and a metal heater with substrate undercut [23]. However, undercuts are usually not part of standard processes or imply extra cost, same for the silicidation used in [22]. Moreover, TOPS designs based on direct doping of the Si waveguide [19,20] involve optical attenuation, which is a significant problem if several switches are cascaded, such as in switch networks.

Table 1. Recent SOI Thermo-Optic Phase-Shifters Implemented in Interferometric Structures

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Thus, the practical TOPS designs on SOI, i.e., low-cost and not involving waveguide doping, can be split into two main groups: those based on a metal heater layer above the waveguide [21,23], and those based on doped-Si strips laid out on both sides of the waveguide [24]. Unfortunately, since the designs reported in Table 1 were built at different foundries, implying different materials, layer thickness and doping levels, it is not clear which of the two approaches performs best. This question has partly been studied in [25] for the IMEC SOI process, however the designs are not optimized, and the doped-Si heater is lossy due to waveguide doping.

At the die level, the higher density of recent SOI photonic integrated circuits (PICs), such as advanced transceivers for digital communications [3], makes them more sensitive to heater thermal leakage [6]. Although thermal crosstalk on SOI has partly been studied in [13,20,21], we have not found a comparison of crosstalk between different heater types, nor across the different etches and trenches available in standard CMOS.

In this paper, we first optimize metal-based (TiN) and doped-Si based (N₊₊ Si) TOPS designs with thermal and optical simulations based on the finite element method (FEM). We then experimentally compare their performance at DC and for switching. Both TOPS designs are fabricated on the same die in the IME process (now AMF), and neither requires special fabrication steps such as undercuts, post-processing or small feature size. We also measure the thermal crosstalk between the two arms of a MZI switch for both TOPS types, for various heater powers and various pitches between the arms. Furthermore, we compare the thermal isolation provided by the default cladding oxide, cladding etches and deep trenches, by measuring the crosstalk between an aggressor heater and a nearby victim MZI, again for various power levels and aggressor-victim gaps. This paper thus reports comprehensively on heater design optimization and crosstalk mitigation on a standard SOI process, which to the best of our knowledge had not been presented in the literature.

2. Heater design

2.1 Theory

We start with a brief review of core concepts guiding heater design. Based on [19], to define heater efficiency and speed, we have$P_{\pi }=\Delta T_{\pi }G,$where G is the thermal conductance between the heated waveguide and the heat sink (Si substrate), and$\tau =H/G$, where H is the heat capacity of the heated arm. However, the formulas should include the area A traversed by the heat flow, i.e. the waveguide cross-section perpendicular to heat flux:

2.2 FEM simulations

A cross-sectional view of the two configurations, i.e. metal and doped-Si resistors, are shown in Fig. 1(a) [14,16]. In both cases, the current flow is through the page, parallel to the waveguide. Since we exclude TOPS designs involving direct doping of the waveguide due to cascaded optical losses, as mentioned in introduction, Fig. 1(a) is a rather general picture of ‘lossless’ heater implementation on SOI. In our simulations and experiments, the buried oxide (BOX) thickness is 2 µm. The material for the BOX and cladding is SiO₂.

 

Fig. 1 Thermal and optical simulation of the TiN and N₊₊ Si designs with the finite element method (FEM). (a) Temperature distribution at$P_{\pi }$for both heaters. 23.9 mW is applied on the TiN resistor (left) and 25.2 mW in total is applied on the N₊₊ Si resistors (right). (b) Temperature at$P_{\pi }$as a function of lateral distance, at mid-waveguide height (y = 0.11 μm). (c) Transient analysis: temperature vs time at the waveguide core for heater power turn-on and turn-off$(0\to P_{\pi }$and$P_{\pi }\to 0).$Dashed and full lines represent 1/e temperature changes for turn-on and turn-off. (d) Optical E field distribution (relative amplitude) for the fundamental mode at${\lambda }_0=$1550 nm in the TiN (top) and N₊₊ Si (bottom) designs. (e) Optical phase vs. total heater power for a 320 μm long TOPS.

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The heater metal is titanium nitride (TiN), and is located 2 µm above the Si strip waveguide [23]. The strip waveguide height and width are 220 nm and 500 nm to support a single TE mode at${\lambda }_0=$1550 nm. For the doped-Si heater, a 90 nm high Si slab is added to create a rib waveguide structure and connect it to the N₊₊ Si resistors on either side, which also have to be defined on 90 nm Si. The rib structure improves heater efficiency, as the thermal conductivity of silicon (148 $\text{W}/{\text{m}}^{\text{2}}\cdot \text{K}$) is much higher than that of SiO₂ (~1.4 $\text{W}/{\text{m}}^{\text{2}}\cdot \text{K}$) [15]. Note that all height values are constrained here by the fabrication process, but different Si slab heights could allow for further design optimization [15]. For the N₊₊ Si design, a 0.8 µm wide lateral buffer between the waveguide and the resistors is used to prevent free-carrier absorption of light. The strongest doping concentration available, 1E20 cm⁻³ [27], is chosen to reduce electrical resistance and for better ohmic heating [24]. The choice of N (phosphorus) versus P (boron) doping for the resistors is arbitrary since their specific heat is not expected to differ significantly. For both the TiN and N₊₊ Si heaters, the resistor width is the smallest allowed by fabrication: 2.0 µm for the TiN strip and 1.0 µm for each doped-Si strip. The TOPS total lengths L is arbitrarily set to 320 µm, and should impact neither$P_{\pi }$nor$\tau$as discussed in Section 2.1.

The cross-section of the TiN-based and the N₊₊ Si-based TOPS designs are simulated with the combination of a thermal solver and an optical mode solver in Lumerical Device, to compare their heat distribution, efficiency and transient response. The thermal and optical FEM engines respectively solve the Heat Diffusion equation in a wide area (40 µm wide x 18 µm high) around the heater, and Maxwell’s equations at${\lambda }_0=$1550 nm in the optical waveguide area. The temperature at the bottom of the thermal simulation region (in the Si substrate) is fixed to the ambient temperature of 300 K, and fixed convection of 10 $\text{W}/{\text{m}}^{\text{2}}\cdot \text{K}$ is defined between the oxide layer and air above it. The thermal and electromagnetic properties used for the different materials and layer thicknesses are listed in Table 3 in Appendix [28–38]. Key parameters include the strong dependence of the silicon thermal conductivity on layer thickness and doping, and free carrier dispersion and absorption in doped-Si. For each TOPS design, the simulation procedure is as follows:

For the TiN design, a single rectangular temperature monitor covering the strip waveguide was used to simulate the thermo-optic effect. For the N₊₊ Si design, two additional monitors overlapping the adjacent 90-nm-high Si slab sections were added.

Results are summarized in Figs. 1(a)–1(e). In Fig. 1(a), the temperature distribution is shown at$P_{\pi }$for both heaters. A temperature shift $\Delta T\approx +{13}^{\circ }\text{K}$in the waveguide core is necessary in both designs to induce a $\pi$shift over a 320 µm length. However, at$P_{\pi },$the TiN resistor reaches a much higher temperature than the N₊₊ Si resistors, because of its greater distance from the waveguide and bad oxide thermal conductivity. In Fig. 1(b), we show the lateral heat distribution at$P_{\pi }$and$y=$0.11 µm (mid-waveguide height) for both heaters. The two designs show a similar thermal decay profile, with substantial residual heat >10 µm away from the waveguide center. The corresponding crosstalk induced in waveguides laid out at various distances from the heater is studied experimentally in Section 3.1. In Fig. 1(c), the simulated transient response of both heaters is shown. The limiting 1/e time constants are ~10.2 µs and ~5.8 µs for the TiN and N₊₊ Si designs respectively. For each, the rise and fall times are similar. The faster response of the N₊₊ Si TOPS is due to the proximity of the heat source and the waveguide: a more compact design decreases the heated arm heat capacity H and therefore$\tau ,$per Eq. (2). The fundamental TE mode at${\lambda }_0=1550\text{ nm}$ in the strip and rib waveguides of the TiN and N₊₊ Si designs are shown in Fig. 1(d). The relatively tight optical confinement and the weak thermo-optic coefficient of silica,$\partial n/\partial T_{Si{O}_2}=1.0\text{E-0}5{\text{K}}^{-1}$ [15], ~18 times weaker than silicon, justify neglecting the thermo-optic effect in the cladding in our simulations. We also retrieve from optical simulations the complex effective index$\underset{\_}{n}=n+i\kappa .$The attenuation,$\alpha =4\pi \kappa /{\lambda }_0$ [39], where${\lambda }_0$is the free-space wavelength, is found to be negligible for the TiN design$(\alpha \approx 0),$meaning the metal is high enough above the waveguide. However,$\alpha =0.26\text{dB/cm}$for the N₊₊ Si design, which translates to a small ~0.008 dB loss for a 320 µm long TOPS. Finally, in Fig. 1(e), the optical phase versus heater power is shown for the TiN and N₊₊ Si designs. The extracted$P_{\pi }$are 23.9 mW and 25.5 mW respectively, in the same range as literature measurements for metal-based [40] and doped-Si-based [20,24] designs. In addition to geometry, the lower specific heat of TiN (598 J/$\text{kg}\cdot \text{K}$) versus Si (711 J/$\text{kg}\cdot \text{K}$) also explains its slightly better efficiency.

We now investigate the impact of resistor width on the performance of the designs. Figures 2(a)–2(c) show the efficiency, time constant (at$P_{\pi }$) and heater FOM from Eq. (3) for different resistive TiN and N₊₊ Si strip widths. The efficiency of both designs intuitively decreases as the resistor width increases, due to a larger fraction of the heat being diffused inefficiently. However, for both designs the lowest time constant is achieved for a total resistive width of 2.5 µm, or + 0.5 µm versus the minimum widths allowed by fabrication. In terms of the FOM, the optimal TiN strip width is 2.5 µm, and the optimal width of each N₊₊ Si strip is 1.0 µm. The FOM is significantly better for the N₊₊ Si design compared to the TiN design, due to its considerably faster response.

 

Fig. 2 Simulated impact of resistor width on the performance of both TOPS designs. (a) Switching power$P_{\pi },$(b) limiting time constant$\tau (0\to P_{\pi }$or$P_{\pi }\to 0),$and (c)$P_{\pi }\cdot \tau$FOM vs. total resistive strip width (sum of the 2 strips for the N₊₊ Si design).

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To finalize the optimization of the N₊₊ Si TOPS design, the last handle available is the width of the intrinsic silicon slab buffer between the heaters and the waveguide,$W_{buffer},$shown in Fig. 1(a). The efficiency, optical loss, limiting time constant and heater FOM as a function of$W_{buffer}$are shown in Figs. 3(a)–3(d). In Figs. 3(a) and 3(b), $P_{\pi }$and$\tau$expectedly decrease as$W_{buffer}$decreases and the heaters are brought closer to the waveguide. However, as seen in Fig. 3(c), decreasing$W_{buffer}$also drastically increases loss. This was expected from Fig. 1(d), where the optical field almost reaches the highly-doped (highly-attenuating) heater regions when$W_{buffer}=0.8\text{μm}\text{.}$Considering the FOM/loss tradeoff just described, we propose a modified, more complete figure of merit for heater design:

 

Fig. 3 Simulated impact of the intrinsic Si slab width W_buffer, shown in Fig. 1 (a), on the performance of the N₊₊ Si TOPS design. (a)$P_{\pi },$ (b) limiting$\tau ,$(c)$\alpha ,$ and (d)$P_{\pi }\cdot \tau$and$P_{\pi }\cdot \tau /I_r$FOMs vs. W_buffer.

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2.3 Layout and fabrication

Figure 4 shows the fabricated SOI TOPS designs. Since layout space was limited and a large fraction was dedicated to crosstalk test structures (described in Section 3), not all simulations of Section 2.2 could be verified experimentally. To validate the accuracy and robustness of our simulation method, we implemented the TiN design with a 7.5 µm wide resistor (widest simulated in Fig. 2), and the N₊₊ Si design with 1 µm wide N₊₊ Si strips (narrowest allowed). To make the N₊₊ Si design approximately lossless (<0.01 dB optical attenuation),$W_{buffer}$is set to 0.8 µm, based on Fig. 3(c). The cross-section of the two final TOPS designs are shown in Fig. 4(a). In the longitudinal direction, the TiN TOPS is implemented as a single resistive strip. Since the expected sheet resistance of the N₊₊ Si layer is several times that of TiN (Foundry data), the N₊₊ Si TOPS is instead implemented as 6 resistors connected in parallel [24]. This lowers the equivalent resistance of the design and the required voltage. The total length of both TOPS designs L is 320 µm to match simulations. The top view of both designs is shown in Fig. 4(b). Both were fabricated on the same die in a multi-project wafer at A*STAR’s Institute of Microelectronics (IME) Foundry.

 

Fig. 4 Final heater layouts. (a) Cross-section (not to scale) and (b) top view of the TiN and N₊₊ Si TOPS designs, plus metal contacts. W_strip = 0.5 µm, W_TiN = 7.5 µm, H_{clad .} = 2 µm, H_strip = 0.22 µm, H_BOX= 2 µm (TiN TOPS); W_{N + +} = 1.0 µm, W_Slab = 2.1 µm, W_rib = 0.5 µm, H_rib = 0.13 µm, H_slab = 0.09 µm (N₊₊ Si TOPS). Layer colors match in (a) and (b). Current direction is arbitrary.

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3. Experimental results

The typical test structure for heater characterization is shown in Fig. 5(a), and is comprised of a thermally-tuned MZI next to which is laid out a passive victim MZI. As the extinction ratio of a (1 x n) MZI switch is primarily function of the splitter/combiner design (outside the scope here), the tuned MZI has only one output. Light is coupled in and out of both MZIs with grating couplers, and a probe is landed on aluminum pads to contact the two heater leads. The pitch between the arms of the tunable MZI,$d_{intra},$the gap between both MZIs,$d_{inter},$and the material in-between are varied between test structures. A total of 15 structures like Fig. 5(a) are laid out, all in C-band. Measurements are presented in two parts: DC (resistance, stability, efficiency and thermal crosstalk), and AC (bandwidth and switching). For the first part, a constant-voltage signal is sent through a precision multi-meter then applied to the heater. The optical signal out of the device under test (DUT) is sent to a variable optical attenuator (VOA) and power-meter. For the second part, the electrical pattern generator signal is split in two, then sent to the heater and directly to an oscilloscope. The tunable MZI output is sent to a commercial photodetector AC-coupled to an oscilloscope. The experimental setup is shown in Fig. 5(b).

 

Fig. 5 (a) Typical test structure for performance and crosstalk characterization of TOPS designs. d_intra and d_inter are respectively the intra- and inter-MZI pitch. (b) Experimental setup. Solid lines and dashed lines are respectively used for DC and AC characterization.

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3.1 DC characterization

Figure 6 shows the basic electrical characterization of the TiN and N₊₊ Si heaters. In Fig. 6(a), the measured IV curves allow to extract total resistance values (<4 V) of 0.54 kΩ and 1.02 kΩ, respectively. From previous experience, the voltage drop across the cables and probe can be neglected. Since the voltage drop across the aluminum heater leads can also be neglected –aluminum resistivity is 2-3 orders of magnitude smaller than the resistor materials – the resistance values extracted are approximately those of the heaters alone. The small glitch at 6.5 V for the TiN IV curve is due to the power supply. The IV linearity of the TiN design is observed to be much better than the N₊₊ Si design. In Fig. 6(b), we show the evolution of the electrical power consumed by the heaters over 10 minutes for a fixed applied voltage. For both heaters, the decrease in power is limited to <0.1 mW over the test duration. The corresponding change in optical phase is negligible, masked by the ± 0.2 dBm caused by the random fiber array unit (FAU) drift. The probe drift, although lesser than the FAU drift due to the contact with the pads, hinders stability measurements >10 min.

 

Fig. 6 Electrical characterization of the fabricated TiN and N₊₊ Si TOPS designs. (a) IV curves. Linear references are extrapolated from the [0-1] V segments. (b) Measured electrical power consumption over 10 minutes for a constant applied voltage.

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The optical loss in a simple heated waveguide segment between two grating couplers, when compared to back-to-back grating couplers, is below the effective measurement resolution due to the FAU drift, but from simulations of Section 2.2 should be very small (<0.01 dB) for both designs. No voltage dependence is measured.

Figure 7 shows the raw transfer function (TF) for a tunable MZI based on the N₊₊ Si TOPS swept from 0 to 10 V. Similar data is obtained for the TiN TOPS. The same TF is shown vs. voltage in Fig. 7(a) and vs electrical power in 7(b), to show the impact of the heater bias point on efficiency. From Fig. 7(a), biasing the heater at a high potential reduces$V_{\pi },$however from Fig. 7(b) $P_{\pi }$ remains approximately the same regardless of bias. Hence, strongly biasing a TOPS is useless, unless the$V_{pp}$budget for switching is limited.

 

Fig. 7 Tunable MZI transfer function for the N₊₊ Si heater (d_intra = 200 μm). Optical power is shown vs. heater voltage in (a) and vs. heater power in (b). $P_{\pi ,1}$ = (23.2 ± 0.7) mW,$P_{\pi ,2}$ = (22.7 ± 1.1) mW,$P_{\pi ,3}$ = (22.1 ± 1.4) mW.

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After TF normalization, the optical phase$\phi$is extracted from the measured intensity $I$ with$I=0.5+0.5\cos (\phi ).$In Fig. 8, the relative phase$\Delta \phi$is plotted against heater power for both types of TOPS and 4 pitches d_intra between the two arms of the tunable MZI, of 50 µm, 100 µm, 150 µm and 200 µm. The extracted$P_{\pi }$are 29.2 mW - 31.5 mW for MZIs based on the TiN TOPS and 22.8 mW - 23.3 mW for those based on the N₊₊ Si TOPS. Reducing d_intra from 200 µm, to 50 µm increases$P_{\pi }$by 2.3 mW for tunable MZIs based on the TiN TOPS and by 0.6 mW for those based on the N₊₊ Si TOPS. This is due to enhanced heat crosstalk between the two arms, which partially cancels out$\Delta \phi$in the active arm. Hence, these results quantify the footprint (d_intra)-efficiency tradeoff in doped-Si and metal-based thermo-optic switches on SOI. Moreover, comparing with Fig. 2(a), efficiency measurements closely match and validate our simulations:$P_{\pi ,sim}=$ + 3.0 mW vs.$P_{\pi ,meas.}$for the 7.5 µm wide TiN resistor, and$P_{\pi ,sim}$ = + 2.7 mW vs.$P_{\pi ,meas.}$for the 2.0 µm wide (total) N₊₊ Si resistor. For both heaters,$P_{\pi ,meas.}$for the widest d_intra pitch is taken for the comparisons since crosstalk effects were absent from simulations. Finally, the good agreement between measurements and simulations suggests that a fabricated 2.0 µm wide TiN heater, the most efficient in simulations, could achieve a ~21 mW$P_{\pi },$or ~1.8 mW better than the N₊₊ Si design.

 

Fig. 8 De-embedded phase change and linear fit as a function of heater power for 4 pitches d_intra between the two arms of the tunable MZI, for the N₊₊ Si and TiN heaters.$\Delta P_{\pi ,N++}=$0.6 mW and$\Delta P_{\pi ,TiN}=$2.3 mW.

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Next, we characterize heat crosstalk between the heater (aggressor) and the unbalanced MZI (victim) shown in Fig. 5(a). Wavelength is set to bias the victim MZI at quadrature, to maximize its output optical power change for small parasitic heat flux and to better discriminate from noise. Figure 9 shows the de-embedded relative phase of the victim MZI as a function of heater power, for d_inter = 5 µm, 15 µm, 45 µm and 135 µm, after sinusoidal fits are applied to the normalized TFs. Note that the phase measured should be independent of the total heater length L, per Eqs. (4) and (5). Three material processing patterns between the aggressor and victim are tested, to investigate layout-based approaches to mitigate parasitic heat flux on the die. In Figs. 9(a) and 9(b), the default SiO₂ cladding fills the aggressor-victim gap, for TiN and N₊₊ Si heaters respectively. The phase change in the victim MZI is similar for both heaters at all d_inter values. Moreover, as simulated in Fig. 1(d), significant residual heat is present 5 µm away from the waveguide, and most of heat is scattered at 15 µm. However, depending on the heater power and the victim function in practice, the parasitic phase shift can still be significant – and is easily measurable – as far as 135 µm away from the heater. In Figs. 9(c) and 9(d), only the N₊₊ Si heater is tested. In Fig. 9(c), the SiO₂ cladding is etched across the heater/victim gap. In Fig. 9(d), the gap is a deep trench cutting through the SiO₂ cladding, 220 nm Si, BOX and Si substrate layers (partially). Comparing Fig. 9(c) with 9(b), etching the cladding has little impact on heat crosstalk. However, comparing Fig. 9(d) with 9(b), the deep trench reduces the phase change in the victim MZI by a factor of ~3, or by 0.31 rad ($\pi /10),$ 0.11 rad, 0.08 rad and 0.02 rad for gap widths of 5 µm, 15 µm, 45 µm and 135 µm, versus the default SiO₂ cladding when the N₊₊ Si heater power is ~23 mW$(P_{\pi }).$Deep trenches can therefore provide significant thermal insulation, and should advantageously be used in tight PIC layouts between heaters and other phase-sensitive devices such as resonators, MZIs, arrayed-waveguide de-multiplexers or coherent receiver hybrids. As noted in Section 2.1 and verified in [21], if using trenches very close to the heated waveguide, the$P_{\pi }\cdot \tau$heater performance tradeoff will also be affected.

 

Fig. 9 Measured phase change at quadrature in the victim MZI vs heater power for different aggressor/victim gap widths d_inter. (a) TiN heater and default oxide in the gap. (b) N₊₊ Si heater, default oxide in the gap. (c) N₊₊ Si heater, etched oxide in the gap (d_inter = 5 µm is absent because of layout rules). (d) N₊₊ Si heater, deep trench in the gap.

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3.2 AC characterization

Figures 10(a) and 10(b) show the measured bandwidth and time-domain switching of the TiN and N₊₊ Si TOPS. In Fig. 10(a), the pattern generator produces a variable frequency sine wave with$V_{\pi }/2$amplitude, and the amplitude response is read on the oscilloscope. The −3dB bandwidth is 33 kHz for the TiN TOPS and 85 kHz for the N₊₊ Si TOPS. In Fig. 10(b), a 5 kHz square wave with$V_{\pi }/2$ amplitude and the required offset to switch between the two first extrema of optical transmission is applied to both heaters. The 1/e rise and fall time constants are measured directly with the oscilloscope, and are $[{\tau }_{rise}=$3.7 μs,${\tau }_{fall}=$7.2 μs] for the TiN TOPS, and$[{\tau }_{rise}=$2.2 μs,${\tau }_{fall}=$2.0 μs] for the N₊₊ Si TOPS. For the TiN TOPS, the asymmetric time constants, i.e., significantly slower fall time, can be explained by the bad thermal conductance between the heater and the heat drain [21], itself arising from the relatively thick oxide layer and air surrounding the metal.

 

Fig. 10 AC measurements of the N₊₊ Si and TiN heaters (d_intra = 200 µm). (a) Frequency-domain: optical amplitude normalized to 1 kHz vs. frequency of the sine wave. (b) Time-domain: 5 kHz square electrical drive signal (top), and optical response of the TiN (middle) and N₊₊(bottom) heaters. Exact response amplitude depends on FAU coupling.

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From Fig. 2(b), the simulated time constant is offset by exactly + 3.6 μs versus the measured limiting$\tau ,$for both TOPS designs. Again, this correlation suggests that a fabricated 2.5 µm wide TiN heater, the fastest in simulations, would achieve a limiting$\tau$of ~5.6 μs. For optimized designs (in terms of the$P_{\pi }\cdot \tau$FOM from Fig. 2(c)), the limiting time constant is thus roughly 2.5 times better for the N₊₊ Si TOPS. Note that several pulse-shaping approaches have been suggested to improve time constants of heaters on SOI [42–47].

Lastly, the frequency response of both heaters in Fig. 10(a) features noticeable peaking, around 13 kHz and 17 kHz for the TiN and N₊₊ Si heaters. This peaking is believed to be the cause of the time-domain overshoot in Fig. 10(b), since the square wave modulation frequency is only 5 kHz. To quickly verify this assumption, Fig. 11 shows the filtering (in simulation) of an ideal square wave with the measured heater transfer functions from Fig. 10(a). In Fig. 11(a), the Fourier transform of an ideal 5 kHz square signal and the filter definitions are shown. In Fig. 11(b), time-domain square signals of 2 kHz, 5 kHz and 10 kHz are shown after multiplication with the filters in the frequency domain. It is readily seen that the peaking is the cause of the observed overshoot, since it disappears when the modulation frequency approaches the peaks in Fig. 10(a). These basic simulations don’t account for the physical directionality of time propagation, explaining the overshoot in both directions in Fig. 11(b). Note that heater ‘overdriving’ is not related to overshoot here, as it is still visualized experimentally at $V_{pp}=V_{\pi }/2$(not shown). The response of both the TiN and the N₊₊ Si heaters is thus typical of second-order systems [48,49]. From a circuit perspective, both heaters are analogous to under-damped RLC circuits, where the induction comes from the long metal traces (heaters and leads), and the capacitance is dominated by thermal diffusion. Note that overshoot is absent from transient simulations of Fig. 1(c) because the (longitudinal) inductance traces cannot be modeled.

 

Fig. 11 Switch overshoot characterization. (a) Ideal 5 kHz square signal fast Fourier transform (FFT), and measured filter response of the N₊₊ Si and TiN heaters. The FFT extends beyond 250 kHz, and filter definitions are extended (zero padding) to match the FFT length. (b) Ideal and filtered time domain signals (simulation) at 2 kHz, 5 kHz and 10 kHz. Modulation is done with a full$V_{\pi }$swing.

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4. Heater comparison summary

Table 2 summarizes the performance of optimal TiN and N₊₊ Si TOPS designs (320 $\mu$m long), based on simulations and experiments. $V_{\pi }$and heater resistance are excluded due to the dependence on the length.

In Table 2, $P_{\pi }$and$\tau$ could slightly be decreased for the N₊₊ Si design if the intrinsic Si slab width was decreased to 0.6 µm (instead of 0.8 µm), for an added ~0.1 dB loss according to Fig. 3. Also,$P_{\pi }\cdot \tau \approx P_{\pi }\cdot \tau /I_r$ since loss is small. Overall then, the TiN and N₊₊ Si TOPS designs have very similar efficiencies, but the latter shows significantly better speed, making it in our opinion the most practical and scalable TOPS on SOI among the ‘lossless’ (without waveguide doping) and fully CMOS-compatible designs. Furthermore, this design only requires 1 metallization layer, for electrical contacts.

Table 2. Comparison Summary between Optimal TiN-Based and Doped-Si-Based TOPS on SOI

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Finally, in terms of the$P_{\pi }\cdot \tau$FOM, the two designs summarized in Table 2 compare advantageously with TOPS designs of [21] and [24], both detailed in Table 1. Those are respectively metal-based and doped-Si based devices also built at IME, both avoiding direct waveguide doping and substrate undercuts. Our TiN design beats [21] by ~48.4 mW ∙ µs, and our N₊₊ Si design beats [24] by ~6.6 mW ∙ µs.

5. Conclusion

We optimized and compared the two main approaches to build thermo-optic phase-shifters on the SOI platform with negligible optical attenuation. Only standard and widely available fabrication steps were used. We first reviewed TOPS theory, and discussed implementation tradeoffs. We then optimized the design of metal-based and doped-Si-based TOPS for the IME process with thermal and optical FEM simulations. To minimize the$P_{\pi }\cdot \tau$FOM, the resistor widths must be ~2.5 µm for TiN and ~1.0 µm for N₊₊ Si (each resistor). In simulations the TiN design has approximately no optical loss, and the width of the intrinsic Si slab for the N₊₊ Si design has to be >0.8 µm to contain loss <0.01 dB (loss was too small to be measured for both designs). Optimal TOPS designs have$P_{\pi }$and limiting$\tau$of ~21.4 mW and ~5.6 µs using a TiN resistor, and 22.8 mW and 2.2 µs using N₊₊ Si resistors. Peeking in the frequency response of both heaters, likely caused by the inductive traces, causes overshoot in the time domain when the modulation frequency is low. Both designs show very good power consumption stability, <0.1 mW over 10 minutes. In summary, the two optimized designs have similar phase-shifting efficiencies, but the doped-Si design is best suited for switching applications due to its better speed. Both designs outperform comparable designs from the literature in terms of the$P_{\pi }\cdot \tau$FOM.

Furthermore, it was experimentally shown that$P_{\pi }$is increased by up to a few mW if the pitch between the arms of a thermo-optic switch is reduced from 200 µm to 50 µm in an effort to reduce footprint. In addition, we showed that except substrate undercuts (requiring special processing), deep trenches are the best structures to limit parasitic thermal phase shifts in sensitive devices at short distances from heaters. This phase shift is reduced by 0.31 rad, 0.11 rad, 0.08 rad and 0.02 rad for distances of 5 µm, 15 µm, 45 µm and 135 µm, versus the default SiO₂ cladding when heater power is$P_{\pi }.$

Appendix

Table 3 lists material constants used in FEM simulations. Properties are taken at 300 K. It is assumed that silicon specific heat is negligibly affected by layer thickness and doping. The electrical conductivity of intrinsic silicon is assumed constant for all film thicknesses as it is ~10⁹ x smaller than for N₊₊ Si. The optical attenuation and refractive index of N₊₊ Si are computed using relations of [30] and the doping dosage information provided by the Foundry. Attenuation is reported as the imaginary part of the refractive index,$\kappa =\alpha {\lambda }_0/4\pi ,$where$\alpha$is the linear attenuation coefficient an${\lambda }_0$is the free-space wavelength. Properties without explicit references are part of the Software database.

Table 3. Thermal and Electromagnetic Properties of Materials Used in FEM Simulations

View Table | View all tables in this article

Acknowledgments

We acknowledge the support of the Natural Sciences and Engineering Research Council of Canada (NSERC), the Fonds de recherche du Québec – Nature et technologies (FRQNT), CMC Microsystems, Lumerical Solutions and Advanced Micro Foundry (AMF).

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