1. Introduction

In recent years, superconducting nanowire single-photon detectors (SNSPDs) [1,2] have emerged as successful alternatives to traditional InGaAs/InP-based single-photon avalanche photodiodes (SPADs) in the realm of near-infrared single photon detection due to their excellent quantum efficiency [3–6], short timing jitter [6–8], ultralow dark count rates [9–11], fast reset time with only several nanoseconds [6,12,13] and photon number resolving ability [14–16]. To date, most of SNSPD systems tend to use fiber coupling method because of its advantages over free-space coupling, including lower dark count rates, more compact size and robustness to mechanical vibration. However, precise alignment between the beam-spot of a single-mode fiber (~10 μm in diameter) and the active nanowire area (typically 10-15 μm in diameter) still remains a challenge, in particular for robust, multi-cycle operation at low temperatures. Three dimensional cryogenic positioner in combination with fiber focuser is commonly employed for in situ matching of the beam waist to the detection area of the nanowire detector [17]. High-efficiency fiber-to-detector coupling can be realized in this way but only one detector can be addressed at a time. Recently, a self-aligned coupling method based on deep-etching of silicon wafer was proposed [18]. Using this technique, a front-illuminated WSi-based SNSPD was realized and achieved an impressive 93% system efficiency, boosted by a photon-recycling cavity embedding the superconducting nanowire [4].

Here, we demonstrate a backside silicon micromachining process that allows high precision placement of cleaved fibers in an array of etched pits in a self-aligned fashion while NbTiN superconducting nanowires are fabricated on the front side. Multiple fiber-detector pairs are integrated on a single detector chip. This approach enables back-illuminated detector structure which separates the optical access and electronic readout circuits on two sides of the chip and thus allows for compact integration of multi-channel detectors.

2. Device fabrication and packaging

Figure 1 illustrates the process flow for fabricating the detector chip. The fabrication begins with a double-side polished silicon wafer [Fig. 1(a)], on both sides of which 200 nm-thick LPCVD silicon nitride (Si₃N₄) is deposited [Fig. 1(b)]. Then, arrays of rectangular-shaped windows are opened in the nitride layer at the backside via optical lithography and following reactive ion etching (RIE) [Fig. 1(c)]. Using these nitride patterns as mask, the silicon substrate can be anisotropically etched into trapezoidal pits in a heated KOH solution [Fig. 1(d)]. In principle, the etching stops automatically when the silicon substrate is completely etched through, leaving free-standing nitride membranes. In practice, we stop the reaction in advance by precisely timing the etch and leave 20 μm-thick residue silicon layer, which is transparent at telecom bands and serves as supporting structure to enhance the mechanical rigidity of the membranes. By controlling the size of the windows patterned in the nitride mask layer, we are able to make the bottom of etched trapezoid slightly smaller than standard SMF-28 fibers (125 μm in diameter) so that fibers can be secured at certain height without breaking the membrane, as shown in Fig. 2(a). After the wet-etching process, a thin layer of NbTiN superconducting film is deposited by means of DC magnetron sputtering [Fig. 1(e)]. The silicon wafer is then diced into 8 mm × 11 mm dies, each of which contains a 4 × 5 array of etched membranes, for further device processing. Four extra calibration membranes, which are used for high-accuracy double-side alignment in the following e-beam lithography, are located at four corners of each die. We cut 20 µm × 20 µm square windows at the center of each calibration membranes using focused ion beam (FIB), etching through the 20 µm-thick silicon residue as well as the nitride layer. The alignment accuracy of this step is better than 1 µm as confirmed by the scanning electron micrograph (SEM). Using the etched-through windows as alignment markers, a total of 20 nanowire detectors are fabricated on each die via two following e-beam lithography steps. The first e-beam lithography exposes the nanowire pattern in 6% HSQ (~100nm thickness) negative resist [Fig. 1(f)]. The second e-beam lithography defines Ti/Au metal pads using a standard PMMA/MMA bilayer lift-off process [Fig. 1(g)]. Finally, the nanowire pattern of HSQ is transferred to underlying NbTiN layer by RIE using CF₄ plasma [Fig. 1(h)].”

 

Fig. 1 The process flow of back-illuminated superconducting nanowire detectors. See text for details on individual fabrication steps.

Download Full Size | PDF

 

Fig. 2 (a) Cross-sectional sketch of the nanowire detector with self-alignment structure (not to scale). (b) Top-view optical micrograph of the detector area with a laser spot illuminated from the backside fiber. The light rectangle is Si₃N₄/Si membrane with the nanowire detector at its center. (c) Photograph of fiber-coupled multi-detector package. Four fibers are connectorized with matched detectors on a single chip. (d) Optical micrograph of the detector chip. (e,f) SEM images of a series-2-SNAP and higher magnification image taken at the corner of the active nanowire detector area. The diameter of detection area is 10 μm.

Download Full Size | PDF

The completed detector chip is mounted on a printed circuit board (PCB) and fixed upside down on an inverted microscope for fiber alignment and packaging. The target etch pit is first filled with a tiny droplet of UV-curable epoxy. A cleaved fiber is manipulated by a 3-axis piezo-motorized stage with a minimum step size of 30 nm to approach the bottom of the pit. A red laser is launched through the fiber and creates an illuminated spot on the membrane to guide the alignment of the fiber to the nanowire detector as shown in Figs. 2(a) and 2(b). The epoxy is cured by exposing the chip using a UV beam for 1-2 minutes. Likewise, three other fibers are aligned and glued to different detectors. The four chosen nanowires are wire-bonded to the coplanar waveguides on the PCB which is in turn installed in a copper box shown in Fig. 2(c). As the last step, the backside of the detector chip is flooded with the UV epoxy and cured. This final step is important for achieving a very robust package of multi-channel detectors. One could in principle wire up all the 20 nanowire detectors but only four detectors are connected to match available coaxial cables in our cryostat. The epoxy we use is UV-22 from the Masterbond Company which features low shrinkage upon curing and optical clearness. The refractive index of the epoxy is 1.52 which is very close to 1.45 of the fiber, and hence there is negligible reflectance (~0.05%) at the interface between the fiber and the epoxy.

Figure 2(d) shows the optical micrograph of the detector array on the chip from bird’s eye view. Among the total 20 nanowire detectors fabricated, 10 detectors are standard SNSPDs and the other 10 are superconducting nanowire avalanche photodetectors (SNAPs). Different from the n-SNAPs reported by Ref [19]. and Ref [20], which employ current-limiting inductors serially connected with n parallel active nanowires, we adopted the modified structure of series-2-SNAP similar to Ref [21]. but with a much larger detection area. Two standard SNSPDs and two series-2-SNAPs were randomly selected among the 20 detectors for fiber connectorization.

Figures 2(e) and 2(f) show SEM images of a series-2-SNAP detector. The thickness of NbTiN film deposited on Si₃N₄-on-Si substrate is 6.5 nm covered by 2 nm-thick native oxide (confirmed by TEM). The nanowire width, spacing and the diameter of the circular-shaped active nanowire area is 40 nm, 80 nm and 10 μm, respectively. The floating nanowires outside the circular area is for proximity effect correction during e-beam exposure, which constitutes a 20 μm × 20 μm rectangle together with the active nanowires. The 180 degree bending between nanowire elements is designed as round corners for relieving current crowding effect [22]. In previous n-SNAP structure [19,20], the current-limiting series inductor L_s is connected externally and typically designed as 10 times larger than the kinetic inductance of one nanowire section L₀ to ensure stable operation without after-pulsing [23]. In the modified series-2-SNAP structure shown here, the external inductor is folded into the active detection area since all the unfired nanowire pairs can serve as current-limiting inductor L_s until the avalanche happens [21]. If the active area of the detector is large, e.g. 10 μm in diameter, the total length of the nanowire is more than 650 μm. This is equivalent to L_s > 16 × L₀, so that dedicated external inductor is no longer needed and hence the reset time can be shortened considerably.

3. Device characterization

The final device package is mounted on the cold plate of a closed-cycle refrigeration cryostat [24] and cooled down to ~1.7 K. 1550 nm laser light is sent through single-mode fibers installed in the cryostat, which are fusion-spliced with the fibers in the detector package. The photon flux is fixed at 100 kHz via a series of variable attenuators and a polarization controller is used to adjust the polarization of incident photons. Figures 3 (a) and 3(b) show the system detection efficiency (SDE) and dark count rate (DCR) as a function of the normalized bias current I_bias/I_sw, where I_sw is the switching current of the detector. We measure a saturated SDE of 16% with the DCR lower than 20 Hz for the best detector (series-2-SNAP), and the other three detectors demonstrate 12% (series-2-SNAP) and 5-8% (standard SNSPDs) SDE at similar dark count level. It can be seen that the two standard SNSPDs do not exhibit saturated SDE at high bias regime due to the constricted bias currents. Separate measurement on large-scale surveying of detectors on the same chip with different design indicates that series-SNAPs indeed have improved fabrication yield compared to standard SNSPDs, likely due to the shared risk of constrictions and further relieved current crowing at the bends in the series-SNAP structure. It is also noteworthy that we did not pre-screen the devices prior to the packaging, which could guarantee that all the packaged detectors show high performance.

 

Fig. 3 (a) SDE as a function of normalized bias current I_Bias / I_SW. The best detector (series-2-SNAP) shows a saturated SDE of 16% with the DCR lower than 20 Hz, while the other three detectors demonstrate SDE of 12% (series-2-SNAP) and 5-8% (standard SNSPDs), respectively. The switching currents I_SW of the four detectors are 18.6 μA, 18.0 μA (series-2-SNAPs) and 8.1 μA, 7.0 μA (standard SNSPDs), respectively. (b) DCR as a function of I_Bias / I_SW. The two curves measured separately with and without light sent to neighbor detector overlaps perfectly, indicating non-measurable cross-talk between the two adjacent detectors. The avalanche current of the series-2-SNAP I_AV is indicated by the red arrow. (c) Averaged output pulses from the series-2-SNAP and the standard SNSPD. The decay time constants are extracted from exponential fitting. (d) Histogram data obtained from the jitter measurement (empty circles) and corresponding Gaussian fit (solid line). The double-arrows indicate full width at half maximum (FWHM) obtained from the fits. The series-2-SNAP and the standard SNSPD are biased at 16 μA and 8 μA, respectively.

Download Full Size | PDF

The detector architecture presented here illuminates the detector from the backside in well-controlled geometry and therefore should produce a minimum cross-talk between detectors. To examine the cross-talk, we send 1 MHz rates of photons to an adjacent detector and measure the dark count again, the curve of which perfectly overlaps with the original DCR curve without light as shown in Fig. 3(b), indicating non-measurable cross-talk between the two detection channels. Figure 3(c) shows averaged signal traces measured by a 6 GHz oscilloscope for series-2-SNAP and standard SNSPD having the same detection area, respectively. As expected, the SNR of series-2-SNAP is almost doubled compared with standard SNSPD and the decay time is shortened from 10.2 ns to 4.9 ns, which are extracted from exponential fitting. As shown in Fig. 3(d), the series-2-SNAP also shows better timing performance with a reduced jitter of 62 ps full-width at half maximum (FWHM) compared to the standard SNSPD’s 79 ps owing to the improved SNR.

4. Conclusion and future work

We have demonstrated a self-aligned packaging scheme with four-channel nanowire detectors on a single silicon chip. To date, we have performed five thermal cycling during several months’ period without device failure, indicating high robustness of the packaged devices. The efficiency of the best SNAP detector show some discrepancies between 16% and 13% as shown in Fig. 4(a), whereas this difference is within the range of uncertainty in the insertion loss caused by the fiber-to-fiber splicing for each cool-down and different fiber adapters used.

 

Fig. 4 (a) SDE of series-2-SNAPs recorded at each cool-down. (b) Cross-sectional sketch of the nanowire detector embedded within optical cavity with self-alignment structure (not to scale). (c) Simulation results for the nanowire absorption efficiency as a function of the variation in the Si residue thickness. The red solid curve represents the efficiency of the design with optical cavity integrated, while the blue one is for the fabricated detectors in this work without cavity. The corresponding dashed lines represent the efficiency with the Si residue layer completely removed for each case of design. The simulation is done using COMSOL Multiphysics with the refractive indices provided by [3].

Download Full Size | PDF

Our approach also enables back-illuminated detector structure which effectively suppresses the cross-talk between detection channels and allows for more compact integration of multi-channel detectors by separating the optical access and the electrical readout on two sides of the chip, compared to existing front-illumination structures [18]. The footprint of each detector in our current design is only 1 mm × 1 mm, which is mainly limited by the size of the pit on the backside of the chip. This footprint could be further shrunk to 0.5 mm × 0.5 mm with the use of thinner Si wafer.

Meanwhile, saturated SDE is measured in the optimized SNAP detector, whose detection area is made as large as the core of a single-mode fiber. By integrating detectors of larger active area [3,4] with optical cavities and pre-screening before packaging, it is possible to realize state-of-the-art multi-channel single-photon detectors with larger array in an ultra-compact size. Here, we propose a structure, schematic of which is shown in Fig. 4(b), integrated with SiO₂ optical cavity and gold reflector to significantly boost the nanowire absorption efficiency. Using slightly thicker NbTiN film (8nm) and higher filling factor of the nanowires (50%), the highest absorption efficiency could reach 96% with an optimized SiO₂ cavity thickness of 258 nm and Si₃N₄ membrane thickness of 194 nm as shown in the simulation results in Fig. 4(c). However, due to the reflectance at the epoxy-Si interface and the Si-Si₃N₄ interface, there is interference oscillation in the nanowire’s absorption efficiency depending on the Si residue thickness, which is much more significant for the cavity-integrated design compared to non-cavity detectors fabricated in this work. The interference could in principle be eliminated by completely removing the Si residue layer leaving free-standing nitride membrane only. Removing the Si layer could also enable the detectors to work at visible wavelengths and near-IR wavelengths.