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We present the hybrid-integrated silicon photonic receiver and transmitter based on silicon photonic devices and 65 nm bulk CMOS interface circuits operating over 30 Gb/s with a 10−12 bit error rate (BER) for λ ~1550nm. The silicon photonic receiver, operating up to 36 Gb/s, is based on a vertical-illumination type Ge-on-Si photodetector (Ge PD) hybrid-integrated with a CMOS receiver front-end circuit (CMOS Rx IC), and exhibits high sensitivities of −11 dBm, −8 dBm, and −2 dBm for data rates of 25 Gb/s, 30 Gb/s and 36 Gb/s, respectively, at a BER of 10−12. The measured energy efficiency of the Si-photonic receiver is 2.6 pJ/bit at 25 Gb/s with an optical input power of −11 dBm, and 2.1 pJ/bit at 36 Gb/s with an optical power of −2 dBm. The hybrid-integrated silicon photonic transmitter, comprised of a depletion-type Mach-Zehnder modulator (MZM) and a CMOS driver circuit (CMOS Tx IC), shows better than 5.7 dB extinction ratio (ER) for 25 Gb/s, and 3 dB ER for 36 Gb/s. The silicon photonic transmitter achieves the data transmission with less than 10−15 BER at 25 Gb/s, 10−14 BER at 28 Gb/s, and 6 x 10−13 BER with the energy efficiency of ~6 pJ/bit at 30 Gb/s.
© 2015 Optical Society of America
1. Introduction
To meet demands of rapidly-growing data traffic and future Tb/s interconnect systems, it is necessary to develop high-speed low-power optical components operating over 25 Gb/s [1, 2]. Silicon photonic receivers and transmitters based on silicon photonics technology can provide cost-effective replacement for optical transceivers in data center and network applications by facilitating the mature silicon CMOS fabrication technology [3–9]. For the pursuit of high-speed and energy-efficient silicon photonic transmitters and receivers, which are the core components of the silicon-based optical communication systems, intensive efforts have been made to progress efficient silicon photonic device and CMOS interface circuit development. Recently, there have been remarkable progresses in silicon optical modulators [2–15] and Ge-on-Si photodetectors (Ge PDs) [16–27], which are the main active components in silicon optical transceiver circuits, and also in CMOS ICs for optical/electrical (O/E) interface and all-silicon photonic/CMOS receivers and transmitters [5, 6, 28–39].
The Ge PD, a key device for receiving optical data, has the compatibility of parallel processing with silicon and comprises a silicon photonic receiver with a CMOS front-end interface circuit (CMOS Rx IC). Recently it has shown impressive progress in performance, and is considered as cost-effective replacement for the conventional III-V compound–semiconductor based PDs. The reported Ge PDs [16–27] have achieved high performance comparable to conventional semiconductor PDs. Various CMOS Rx ICs based on SOI substrates or bulk silicon have been also demonstrated with high data rates [5, 6, 34, 35].
There have been reports on silicon photonic receivers where Ge waveguide (WG) PDs on SOI substrates and CMOS Rx ICs were monolithic- or hybrid-integrated [2, 28–33]. A receiver based on a Ge WG PD and a SOI-CMOS amplifier operating up to 40 Gb/s was reported [30]. In general, most of reported Ge PDs are waveguide-type defined on SOI [2–9, 16–21, 28–33], whereas most of CMOS ICs are based on bulk silicon technology. On the other hand, vertical-illumination Ge PDs are defined on bulk silicon [24–27], and are of interest since they can enable the monolithic integration with bulk CMOS ICs more realistic, and have a big advantage in packaging with optical fiber. However, it is rarely reported, since simultaneous achievement of both high-speed and high-responsivity characteristics in a vertical-illumination type PD is difficult due to the trade-off between responsivity and speed of the device.
The silicon optical modulator, a key device for transmitting optical data, comprises a Si-photonic transmitter with a CMOS driver circuit (CMOS Tx IC), and has also shown remarkable progress. Especially, silicon Mach–Zehnder modulators (MZMs) based on a PN junction in reverse bias modes on SOI substrates have shown potential for high-speed performance and low voltage driving with broad spectral response and high thermal tolerance [2, 6, 8–15]. Intensive work has been done in this area to achieve high modulation efficiency up to high data rates with low optical loss and high energy efficiency. Also, various types of modulator driver CMOS ICs have been reported demonstrating performance up to 28 Gb/s [2, 6, 31, 32, 36, 37].
In this paper, we present the silicon electronic photonic hybrid-integrated circuits of receiver and transmitter. We demonstrate the all-silicon photonic/CMOS receiver and transmitter operating over 30 Gb/s.
For the development of a high-performance silicon photonic receiver, we hybrid-integrated a vertical-illumination type Ge PDs defined on bulk silicon with a 65nm bulk CMOS Rx IC. Figure 1(a) shows a photographic image of a butterfly-packaged silicon photonic receiver module, and a microscope image of the high-speed sub-mount inside the receiver module housing, on which a vertical-illumination Ge PD with a mesa diameter (ϕ) of 30 μm and a 3 μm-thick Ge absorption layer (WGe) is wire-bonded with a CMOS Rx IC. The packaging designs for a high-speed sub-mount based on a duroid/PCB hybrid structure, the differential microstrip waveguides with a 100 Ω characteristic impedance and discrete components for the bias circuits, and the low-loss aluminum housing were performed using high-frequency structure simulator (HFSS). A single mode fiber with an aspherical lens and two GPPO connectors were packaged into a receiver module. Here, the achievement of high responsivity and large bandwidth of the integrated Ge PDs is essential for realizing a high-performance silicon photonic receiver. The vertical-illumination type Ge PDs employed a simplified device structure and fabrication process which can minimize the degradation of epitaxial layers grown by reduced pressure chemical vapor deposition (RPCVD). The 6” Si (100) silicon wafer was phosphorous-implanted with a doping level of 5 × 1019/cm3. A 0.1μm-thick Ge seed layer was grown at 400°C, followed by 3 μm-WGe layer grown at 650°C without thermal annealing process. A 0.1 μm-thick in situ boron-doped poly-silicon with a doping level of 5 × 1020/cm3 was deposited on the top of the Ge absorption layer at 650 °C, for a heavily and uniformly doped layer without ion implantation. The devices were fabricated with the CMOS compatible process of I-line photolithography, etching, metallization and alloying process with Ti/TiN/Al_1%Si/TiN. A SiO2 layer was used for passivation and anti-reflection coating. Figure 1(b) shows a top-view SEM image and a 52 degree-tilted cross sectional FIB SEM image of the fabricated Ge PD with a 30 μm-ϕ and a 3 μm-WGe. Figure 1(b) also shows the on-chip measured current-voltage (I-V) curves of the Ge PD and the frequency response curves characterized by the impulse response measurement [40], where a Menlo systems TC-1550 femtosecond laser, the Agilent 86100D digital communication analyzer (DCA-X) with a 86118A 70GHz electrical module were used at λ ~1550 nm, prior to the hybrid-integration. The light was delivered to the top of the PD by a lensed optical fiber probe for the measurement. In the I-V curve of Fig. 1(b), the black line indicates the dark current, and the red line indicates the photocurrent under illumination of λ~1550 nm. The device shows a low dark current of ~101 nA at −1V, and a high-responsivity of ~0.73 A/W at λ~1550 nm. The measured −3 dB bandwidth (f-3dB) is ~18.6 GHz at −1 V and ~20 GHz at −3 V. On-chip measurements of eye diagrams were performed by using the non-return-to-zero (NRZ) pseudo-random bit sequence (PRBS) 231-1 signal of the Anritsu MP1800A pulse pattern generator (PPG) with 4 channel MU181020A module and a MP2821A 50 Gb/s MUX connected to a λ ~1550 nm Oki 43 Gb/s EML modulator, using the Agilent 86100D digital communication analyzer with an 86109A 40 GHz electrical head module. Right figures in Fig. 1(b) show the on-chip measured eye-diagrams of the Ge PD at 25 Gb/s and 30 Gb/s data rate. The CMOS Rx IC is comprised of a transimpedance amplifier (TIA), a single-differential converter (SDC), a 4-stage limiting amplifier (LA), and an output driver, designed and fabricated with 65nm bulk CMOS technology. Figure 1(c) shows a microphotograph, a measured 25 Gb/s electrical eye diagram, and a schematic diagram of the fabricated CMOS Rx IC. The designed TIA is based on an inverter with resistive and inductive feedback, to extend the bandwidth by lowering the input and output impedances [41]. For a differential signaling, a single-to-differential conversion circuit is inserted after the TIA, where two cascaded differential amplifiers with the inductor shunt-peaking were used. The 4-stage current-mode-logic (CML) based LA employs a negative capacitance generation for the enhancement of a bandwidth and an offset cancelation circuit for a stable operation. The CML-based output driver for driving the high-speed signal off the chip is designed to have a termination impedance of 50-Ω with a shunt inductive peaking. The simulational input referred noise current of the TIA was 3.9 μArms. The TIA, SDC, and LA block exhibit a total transimpedance gain of 78 dBΩ, and a −3 dB bandwidth of ~13.5 GHz. The area of a CMOS Rx IC is 940 x 800 μm2.
Fig. 1 (a) A photographic image of a butterfly-packaged silicon photonic receiver module, and a microscopic image of the high-speed hybrid duroid/PCB submount in a housing, where a vertical-illumination Ge PD with a 30 μm-ϕ and a WGe ~3 μm is hybrid-integrated with a CMOS front-end circuit. (b) A top-view SEM image, a 52 degree-tilted cross sectional FIB SEM image, an on-chip measured I-V characteristic under illumination of λ~1550nm, an on-chip measured frequency response and eye diagrams of a fabricated vertical-illumination Ge PD. (c) A microphotograph, a measured 25 Gb/s electrical eye diagram, and a schematic diagram of the CMOS Rx IC, comprised of a transimpedance amplifier, a single-to-differential converter, a 4-stage limiting amplifier, and a output driver.
Figure 2 (a) displays the measured eye diagrams of the butterfly-packaged silicon photonic receiver module at λ ~1550 nm, with the input optical power near error free condition (10−12 BER) of −13.5 dBm, −11 dBm, −8 dBm, and −2 dBm for 20 Gb/s, 25 Gb/s, 30 Gb/s and 36 Gb/s, respectively. Here, the optical transmitter signal with 8.7 dB extinction ratio was used in the measurement. The measured jitter is ~2 ps for the data rate from 25 Gb/s to 30 Gb/s. The measurements of bit-error-rates (BERs) were performed with the Anritsu MP1800A 50 Gb/s PPG system connected to an Oki 43 Gb/s EML module (optical transmitter) for λ ~1550 nm, and the Anritsu 50 Gb/s error detector system with an MP1822A 50 Gb/s DeMUX and 4 channel MU18040A error detector. One of the differential electrical outputs of the receiver module was connected to the BER tester, and the other output was connected to the Agilent 86100D DCA-X with an 86109A 40 GHz electrical head module. Figure 2(b) displays the measured BER curves for various data rates from 20 Gb/s to 36 Gb/s, with NRZ PRBS 27-1 signals. Inset shows a 30 Gb/s eye-diagram of the optical transmitter (Oki modulator) used in the sensitivity measurement. Here, 27-1 PRBS input was used because the AC coupler used the receiver circuit cutoffs low frequency, and this design is relevant for applications with 8b/10b and similar coding schemes [30].
Fig. 2 (a) The measured 20 Gb/s, 25 Gb/s, 30 Gb/s, and 36 Gb/s eye diagrams of a photoreceiver module at λ ~1.55 μm near error free condition (10−12 BER). (b) Measured BER curves of the photoreceiver at various data rates from 20 Gb/s to 36 Gb/s. Inset shows a 30 Gb/s eye-diagram of the optical transmitter used in the measurement. ER was ~8.7 dB.
At a BER of 10−12, the receiver demonstrates the sensitivity of −11 dBm at 25 Gb/s, and −2 dBm at 36 Gb/s, as seen in Fig. 3(a) which depicts the measured sensitivity at a 10−12 BER versus bitrate curve of the silicon photonic receiver. Figure 3(b) shows the measured energy efficiency versus bitrate curve. Here, the energy efficiency was measured for the optical input power at a BER of 10−12 of each bitrate. The energy efficiency is 2.6 pJ/bit at 25 Gb/s with an optical input power of −11 dBm, and 2.1 pJ/bit at 36 Gb/s with an optical input power of −2 dBm.
Fig. 3 (a) The sensitivity at 10−12 BER .vs. bitrate curve. The sensitivities are −13.3 dBm, −11 dBm, −9 dBm, −8 dBm, −4.5 dBm, and −2 dBm at 20 Gb/s, 25 Gb/s, 28 Gb/s, 30 Gb/s, 34 Gb/s, and 36 Gb/s, respectively. (b) The energy efficiency was measured with the optical input power at a BER of 10−12 for each bit rate
For the all-silicon/CMOS-based transmitter, the PN depletion Mach-Zehnder modulator on a SOI substrate was hybrid-integrated to the CMOS driver IC (CMOS Tx IC) based on 65 nm bulk CMOS technology. Figure 4(a) shows photographic and microscopic images of the silicon photonic transmitter, where Si MZMs with 1 mm-long phase shifter were wire-bonded to CMOS Tx ICs on a PCB, and two fiber blocks were attached on the integrated grating couplers for optical input and output. The integrated silicon MZM devices were fabricated with CMOS-compatible process on a 6-inch SOI wafer. The ridge waveguides with 100 nm slab height is 0.5μm wide for the modulator waveguides were defined by I-line lithography and high dense plasma (HDP) dry etching process. The silicon grating couplers (GCs) with the pitch of 0.315μm and a 70 nm etch depth were defined on the waveguides for optical input and output. In designing the PN depletion diode for a modulator, the electrical speed of a junction, carrier-dependent loss, and index change efficiency were considered simultaneously. The target doping levels of the lateral PN junctions formed on the phase shifters of both arms were ~1 × 1018 cm−3 for the N-region and ~7 × 1017 cm−3 for the P-region. The P++, N++ implants for a Si modulator were performed to the doping concentration levels of ~1 × 1020 cm−3, followed by an activation process at 900°C for 30 seconds. Metallization with Ti/TiN/Al_1%Si/TiN and an alloying process were performed. Figure 4(b) shows a microscopic image of the fabricated MZM, the optical transmission spectra of the MZM device at various DC biases, and on-wafer measured eye diagrams of the MZM driven differentially with 2.5 Vpp NRZ PRBS 231-1 signals of the PPG, prior to the hybrid integration. Here, the input continuous wave (CW) beam from a tunable laser was passed through a polarization controller and coupled to an input GC to feed the MZM. The modulated output signal from the chip was coupled to fiber probe aligned with an output GC. The optical insertion loss of the MZM device excluding routing and coupling was measured to be ~4.5 dB, which includes a phase shifter loss of 2.7 dB/mm. The modulation efficiency (VπLπ) of the device was ~2.36 V·cm. The capacitance of the modulator was ~0.8 pF near −3 V. The RC-limit −3dB bandwidth, f-3dB = 1/(2πRC), of the modulator was ~24 GHz. The MZM device, differentially driven with 2.5 Vpp, demonstrated an ER of 3.3 dB for 30 Gb/s and an ER of 2.8 dB for 40 Gb/s operation, at quadrature. The same device also exhibited an ER of ~5 dB for 30 Gb/s operation, when differentially driven with 1.1 Vpp NRZ PRBS 231-1 signals and biased at ~8 dB below quadrature. Here, the measured ‘one’ level showed ~7 dB loss compared to the maximum optical transmission.
Fig. 4 (a) A photographic image, and a microscopic image of the hybrid-integrated silicon photonic transmitter, where 1 mm-phase shifter MZM modulator is wire-bonded to a CMOS Tx IC. (b) A microscopic image of the fabricated 1 mm-phase-shifter MZM with optical transmission spectra measured with only one phase shifter biased at various voltages from 0 V to −7 V, and the on-wafer measured 30 Gb/s, and 40 Gb/s eye diagrams, driven in differential mode of 2.5 Vpp NRZ PRBS signals, at quadrature, prior to hybrid integration.
The CMOS Tx IC to drive a MZ modulator is comprised of a pre-driver and an output driver. Figure 5(a) shows a microscopic image, and a measured 30 Gb/s electrical eye diagram, where one of the differential electrical outputs of the driver IC was connected to the Agilent 86100D DCA-X with an 86118A 70 GHz dual electrical module with remote sampling head. Here, ~1.3 Vpp was measured at 30 Gb/s. Figure 5(b) shows a schematic diagram of the CMOS Tx IC and the circuit implementation of a 2-tap FFE SCML driver and a pre-driver. The output driver is based on the combined structure of a 2-tap feed-forward equalizer (FFE) for bandwidth enhancement and the stacked current-mode-logic (SCML) designed to achieve a voltage swing of ~2.5 Vpp,Diff (that is, differential drive of 1.25 Vpp signal). The 2-tap FFE offering pre-emphasis compensates the distortion at the MZM and the interconnection. The pre-driver, transmitting the signal to the 2-tap FFE, employs the time-delaying buffer structure where each inductor is shared by two CMLs, and varactors are connected in parallel, which results in smaller size, lower inductance and parasitic capacitance. The supply voltage of HVDD in Fig. 5(b) can be varied from 2.7 V to 4V.
Fig. 5 (a) A microscopic image of the CMOS Tx IC, and a measured 30Gb/s electrical eye diagram with a HVDD~3.2 V. (b) A schematic diagram of the CMOS Tx IC and circuit implementation of a 2-tap FFE SCML driver and a pre-driver.
CW light from a tunable laser source was coupled to the fiber block which is attached on the input GC on a chip through a polarization controller to feed an integrated MZM of the silicon photonic transmitter. The external PRBS electrical signal was connected to the integrated CMOS Tx IC. The optical signal modulated by the integrated silicon MZM is transmitted off the silicon photonic transmitter through the fiber block which was attached on the output GC. This optical signal was measured by an Agilent 86100A DCA. An EDFA was used to boost the modulated output signal to compensate for the relatively large coupling loss to the silicon GCs and waveguide, and a tunable wavelength filter was used before light signal was detected with our 43 Gb/s photoreceiver based on a vertical-illumination type Ge PD hybrid-integrated with a commercial InP-based TIA [27]. The resulting O/E converted signal is sent to either an Agilent DCA with an 86118A 70 GHz remote sampling module for eye-diagram measurements or an error detector for BER measurements.
Figure 6(a) shows the measured eye diagrams of a hybrid-integrated silicon photonic transmitter based on a PN-depletion type MZM at 20 Gb/s, 25 Gb/s, 28 Gb/s, 30 Gb/s, 34 Gb/s, and 36 Gb/s with 1 Vpp PRBS 27-1 signals. The eye is open with 5.7 dB ER at 25 Gb/s and 4.2 dB ER for 30 Gb/s. Here, in order to achieve an ER larger than ~4 dB at 30 Gb/s for differential drive of ~1.1 VPP of the integrated CMOS driver IC, the hybrid Tx was biased at approximately 8 dB below quadrature. The HVDD of a FFE SCML driver IC was adjusted between 2.8 V and 3.6 V. For comparison, Fig. 6(b) shows the eye-diagram of the MZM device which was biased at 8 dB below quadrature and driven differentially with 1.1 Vpp NRZ PRBS-31 PPG signal, prior to the hybrid integration.
Fig. 6 (a) Eye diagrams of the hybrid-integrated silicon photonic transmitter, measured from 20 Gb/s to 36 Gb/s. (b) Eye-diagram of the MZM device driven differentially with 1.1 Vpp PPG NRZ signal, and biased at 8 dB below quadrature, prior to the hybrid integration, for comparison.
The power consumption of the silicon photonic transmitter was obtained by measuring the voltage and current of all the supplies of the driver circuits during PRBS data transmission at each bitrate. The silicon photonic transmitter shows an energy-efficiency of ~6 pJ/bit at 30 Gb/s, excluding the laser power. No error was observed in over 11 hours during which more than 1015 bits of data were transmitted (corresponding to a BER of < 10−15) at 25 Gb/s. The measured BER was less than 10−14 at 28 Gb/s, and ~6 x 10−13 at 30 Gb/s. Figure 7(a) shows the energy efficiency versus bitrate curve, and the measured BER versus bitrate curve of the silicon photonic transmitter. Figure 7(b) shows the BER measurement down to < 10−15 for 25 Gb/s data transmission between the silicon photonic transmitter and the 43G photoreceiver, which has a sensitivity of −10.15 dBm at 40 Gb/s [27]. Inset shows the 25 Gb/s eye diagram measured at a BER of 10−15. Further improvement in CMOS interface ICs can lead to more efficient silicon photonic receivers and transmitters for future network and interconnect applications.
Fig. 7 (a) Measured energy efficiency versus bitrate curve, and BER versus bitrate curve of the silicon photonic transmitter. (b) BER measurement down to < 10−15 for 25 Gb/s data transmission between the silicon photonic transmitter and the 43G photoreceiver. Inset shows the 25 Gb/s eye diagram measured at a BER of 10−15.
3. Conclusion
In conclusion, we present the silicon electronic-photonic hybrid-integrated circuits of receiver and transmitter, demonstrating the all-silicon photonic/CMOS receiver and transmitter operating over 30 Gb/s with a BER of 10−12 for λ ~1550nm. The silicon photonic receiver based on bulk silicon technology is comprised of a vertical-illumination type Ge-on-Si photodetector hybrid-integrated with a 65 nm bulk CMOS receiver front-end circuit on a high-speed duroid/PCB hybrid structure sub-mount. The receiver module shows high performance operation up to 36 Gb/s, with sensitivities of −11 dBm, −8 dBm, and −2 dBm for data rates of 25Gb/s, 30 Gb/s and 36 Gb/s, respectively, at a BER of 10−12. The measured energy efficiency of the receiver is 2.6 pJ/bit at 25 Gb/s with an optical power of −11 dBm, and 2.1 pJ/bit at 36 Gb/s with an optical power of −2 dBm. The silicon photonic transmitter is based on a depletion-type Mach-Zehnder modulator wire-bonded with the 65 nm bulk CMOS driver circuit, and exhibits 5.7 dB ER for 25 Gb/s, and 3 dB ER for 36 Gb/s. The silicon photonic transmitter achieves the data transmission with less than 10−15 BER at 25 Gb/s, 10−14 BER at 28 Gb/s, and 10−11 BER with the energy efficiency of ~6 pJ/bit at 30 Gb/s.
Acknowledgement
This work has been supported by the ICT R&D program of MSIP/IITP, Korea [grant no. 10038764].
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