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The wavelength band near 1300 nm is attractive for many telecommunications applications, yet there are few results in silicon that demonstrate high-speed modulation in this band. We present the first silicon modulator to operate at 50 Gbps near 1300 nm. We demonstrate an open eye at this speed using a differential 1.5 Vpp signal at 0 V reverse bias, achieving an energy efficiency of 450 fJ/bit.
©2013 Optical Society of America
1. Introduction
Mach-Zehnder silicon modulators are attractive for data communications due to their relative thermal insensitivity and wide optical bandwidth [1]. Furthermore, by fabricating these devices on a silicon platform, highly complex and integrated systems are possible [2, 3]. Significant progress has been made for Mach Zehnder modulators operating near 1550 nm, with devices that have been demonstrated to be suitable for high speed digital [4, 5], low drive voltage [6, 7], and analog applications [8, 9]. However, there have been relatively few presentations of silicon modulators operating near 1300 nm with similar performance. Most recently, Fujikata, et al. present a Mach-Zehnder modulator using a MOS junction to achieve 25 Gbps performance for light near 1.3 µm [10].
The wavelength band near 1300 nm is attractive for telecommunication systems, such as upstream/downstream communication in passive optical networks or working beyond the dispersion limit at long transmission distances in high-speed communications [11]. While many hybrid silicon modulators have also been demonstrated in this band [12–14], these geometries are not currently compatible with standard silicon photonic platforms. We present a 3-mm silicon traveling wave Mach-Zehnder modulator fabricated in a silicon-on-insulator (SOI) platform capable of operating at 50 Gb/s. Using a differential 1.5 Vpp drive voltage at a 0 V reverse bias, the device achieves an energy efficiency of 450 fJ/bit.
2. Traveling wave design
The device presented here is similar in architecture to that of [6] with several key modifications. First, the waveguides are scaled from 500 nm to 420 nm to support primarily the TE0 mode in the 1300 nm band and optimally overlap the optical mode with the pn junction. Secondly, intermediate p + and n + implants are used to decrease series resistance. The new junction profile is shown in Fig. 1. This device also utilizes components in the OpSIS PDK at 1.3 µm, such as a compact Y-junction and grating coupler [15]. Finally, thermal phase tuners are integrated into each arm of the Mach-Zehnder interferometer.
Fig. 1 (a) Micrograph of the device. (b) Simplified cross sectional diagram of the phase shifter, not to scale.
The intermediate dopants are found to result in drastic improvements in performance by significantly reducing junction series resistance, Rpn. There is a fundamental tradeoff in the design of the pn junction between bandwidth, modulation efficiency, Vπ, and optical loss. From the derivations in [16], in a traveling wave modulator with well-matched RF and optical modes, the bandwidth is limited by RF attenuation, αrf. Furthermore, the electrooptic 3-dB bandwidth is related to the RF 6.4 dB bandwidth by , where Ldev is the length of the device.
From the derivation in [17], RF attenuation can be expressed as:
where f is frequency, Cpn is the junction capacitance, Zdev is the device characteristic impedance, and RTL is the transmission line series resistance. In the case where losses due to the shunt conductance from the pn junction dominate, the above relationship indicates that the electrooptic 3-dB bandwidth is proportional to . Thus, it is clearly advantageous to reduce Rpn to enhance bandwidth. While the simplest method to reduce Rpn is to reduce the clearance between the waveguide and high dopant concentration regions, this results in a tradeoff between insertion loss and bandwidth. Instead, by introducing intermediate dopants, we are able to primarily sacrifice process complexity for bandwidth. We have chosen the dopant exclusions such that the simulated waveguide loss is not expected to increase from the geometry of what is reported in [6].The implant layout as reported in [6] resulted in 1.6 Ω-cm series resistance in the partially etched silicon due to sheet resistance from the n-type and p-type silicon. From simulation, the sheet resistances of the p + and n + intermediate dopants in partially etched silicon are expected to be 3.8 kΩ/☐ and 1.5 kΩ/☐, respectively. With the junction as depicted in Fig. 1(b), this corresponds to a series resistance in the partially etched silicon of 0.65 Ω-cm. Using the scaling proportionalities defined above, this reduction in series resistance should improve the previous 3-dB bandwidth of 18.5 GHz for the 3 mm long device to approximately 29 GHz.
The transmission line is designed to have a 33 Ω impedance when loaded with the pn junction. Each arm of the Mach-Zehnder consists of a 3 mm long lateral pn-junction phase shifter. To insure the current travels through the metal rather than laterally through the silicon, each 10 µm of phase shifter length is broken into a 9.2 µm length with the pn-junction followed by 0.8 µm of undoped silicon. The transmission lines are driven by a set of GSGSG input pads and terminated by a set of GSSGSSG output pads. Additionally, a 250 µm long thermal phase tuner is also appended on each arm of the interferometer after the pn junction phase shifters to enable the bias point to be appropriately set. Resistors for the phase tuners are integrated into the waveguides by overlaying the n-type implant with the waveguide.
3. Fabrication
Fabrication occurred at the Institute of Microelectronics (IME), A*STAR, Singapore [18] in a multi-project wafer run through the OpSIS foundry service [19]. The fabrication process follows the flow reported in [20] and in all cases 248 nm photolithography is utilized. The starting material is a 220 nm top-silicon thickness SOI wafer with a 2 µm thick buried oxide layer and a high-resistivity 750 Ω-cm silicon substrate, necessary for high-speed RF performance [21]. First, a 60 nm anisotropic dry etch is applied for the grating couplers, followed by additional etch steps to define the 90 nm slab layer. The p + + , p + , p, n, n + , and n + + implants were performed next on the exposed silicon before oxide deposition. The peak doping densities for the p + , p, n, and n + layers were chosen to be 2e18/cm3, 7e17/cm3, 5e17/cm3, and 3e18/cm3, respectively. The implants were followed by a rapid thermal anneal at 1030 °C for 5 seconds. Finally, two layers of aluminum vias and interconnects were formed.
It should be noted that although this device could theoretically be designed and fabricated with only a single layer of metal, due to inclusion in a multi-project wafer shuttle run through OpSIS, both of the offered metal layers were utilized. Thus, the thicker top aluminum layer (M2) is used for the transmission lines and the via-stack from M2 to silicon is determined by design rules as well as via and contact resistance considerations.
4. Device characterization
4.1 DC measurements
Light is coupled onto and off of the chip via grating couplers. A pair of grating couplers near the device is used to extract the insertion loss of the testing apparatus. Device insertion loss is then measured as the difference between the response of the test loop with no Mach-Zehnder modulator and the response of the loop with the device. The total insertion loss of the device is measured to be 5.5 dB. Of this 5.5 dB, 1.6 dB excess loss is due to two Y-Junctions, 0.1 dB is due to tapers from ridge to rib waveguides, 0.16 dB is due to the thermal tuner, and the remaining 3.34 dB is due to the 3 mm long phase shifter. Within a 2π phase shift in the thermal tuners, the variation in thermal tuner loss as a function of applied phase shift is insignificant relative to the loss due to the implanted silicon.
The Mach-Zehnder interferometer is intentionally unbalanced by 100 µm to enable easy testing by tuning the input wavelength. To test the DC performance of the phase shifters, wavelength sweeps are measured at various reverse bias voltages. Due to the unbalanced interferometer, the phase shift may be tracked by observing the shift in null points of the fringes in the spectrum. A typical spectrum at different DC bias voltages is shown in Fig. 2(a) and the phase shift versus reverse bias is shown in Fig. 2(b). The small-signal VπL between 0 V and 1 V reverse bias is 2.64 V-cm and 2.43 V-cm for the bottom and top arm, respectively. Additionally, since the device is intended to operate with no or low bias, C-V and I-V curves are presented in Figs. 2(c) and 2(d).
Fig. 2 (a) Typical spectrum at various reverse biases. (b) Phase shift vs reverse bias of typical phase shifter. A small-signal Vπ is measured to be 8.8 and 8.1 V for the bottom and top arms, respectively, between 0 V and 1 V reverse bias. (c) C-V curve of the pn junction of the phase shifter. (d) Measured I-V curve of the device without RF termination.
The cross section of the thermal tuner is shown in Fig. 3(a). The n-type doped waveguide core acts as a heater and is measured to have a resistance of approximately 42 Ω. The shift in null point is also used to test the efficiency of these thermal phase shifters. A constant DC bias is applied to the resistor and the power required to achieve a π-phase shift is measured to be 27 mW. The phase shift versus power into the resistor is shown in Fig. 3(b). Based on the primarily linear dependence between phase shift and power, the total phase shift is dominated by thermal effects, rather than carrier refraction due to injected carriers.
Fig. 3 (a) Simplified cross section of the thermal phase tuner. (b) Tuning efficiency of the thermal tuner. The power required to shift the wavelength by π is measured to be 27 mW.
4.2 High speed characterization
The high speed performance of the device is characterized by an electrooptic S-parameter sweep, and a typical trace is shown in Figs. 4(a) and 4(b). In order to test the bandwidth, the wavelength was biased at the optical −3 dB point in the spectrum. An Agilent N4373C Lightwave Component Analyzer and a Newport 1414 photodetector were used to test the device. Each arm was driven individually with a GSGSG probe, where the arm not under test was connected to a 50 Ω termination resistor. A GSSGSSG probe is used to terminate the device, where each signal path is connected to two 50 Ω termination resistors in parallel, resulting in an equivalent 25 Ω termination impedance. Terminating with a lower impedance suppresses modulation depth at low speeds, which then improves operation bandwidth [22]. The bandwidth is shown in Fig. 4(a), where the electrooptic response of the photodetector alone is removed from the measurement EOS21. Although there appears to be ripples on the order of 2 dB in the S21 of the bottom arm that fall below the −3dB point, as will be shown below, this does not prevent the device from achieving 50 Gbps performance.
Fig. 4 (a) Electrooptic S21 of each arm at 0 V reverse bias. Input light is set to the −3 dB point in the optical spectrum. (b) S11 of the device.
To demonstrate high speed digital performance, a 50 Gbps PRBS signal is driven through the device. An Anritsu MP1822A Pattern Generator is used to generate a differential 215-1 PRBS signal, which is then applied to the input pads using a GSGSG RF probe. Light at the −3dB point, in this case 1301.91 nm, is input into the device and then received by a Picometrix AD-10ir photodetector connected through a DC block to an Agilent Digital Communications Analyzer (DCA). Although the received electrical signal is AC coupled, the extinction ratio may still be extracted. Knowing the responsivity of the photodetector, the DC optical power into the photodetector (Pavg) can be recorded through a current monitor on the AD-10ir photoreceiver. Similarly, the peak-to-peak voltage amplitude measured by the DCA can be converted to the peak-to-peak optical power, Pp-p. If we then assume that the PRBS signal consists of an even distribution of “1” and “0” bits, the extinction ratio is calculated as:
Also of interest is the “1” bit excess loss of the device, defined as the additional loss incurred for output representing a digital “1” bit compared to the maximum transmission. This loss is calculated based on the optical bias point, Pbias, as:
We demonstrate eye diagrams using three different drive voltage conditions. Driving with a signal amplitude of 1.5 Vpp and 0 V bias yields an energy efficiency of 450 fJ/bit, extinction ratio of 3.4 dB, and “1” bit loss of 1.6 dB, shown in Fig. 5(a); driving with a signal amplitude of 2.0 Vpp and 0 V bias yields an energy efficiency of 800 fJ/bit, extinction ratio of 4.6 dB, and “1” bit loss of 1.3 dB, shown in Fig. 5(b); and by driving with a 3.0 Vpp signal with a 1.0 V reverse bias we achieve an energy efficiency of 3.4 pJ/bit, extinction ratio of 4.2 dB, and “1” bit loss of 1.4 dB, shown in Fig. 5(c). Note that with an equivalent 25 Ω termination resistance, energy per bit is calculated by:
where Ninput is the number of electrical inputs and B is the data rate in bits per second. Since the PRBS signal generator uses a 50 Ω output impedance, this value is used for estimating power consumption. Note that since the transmission line impedance is 33 Ω, the on-chip drive voltage is less than the drive voltage that is reported here. A comparison of the performance of our modulator to other Mach-Zehnder modulators, including results at 1550 nm, is shown in Table 1.Fig. 5 50 Gbps eye diagrams using a differential pseudorandom 215-1 signal. (a) 1.5 Vpp amplitude and 0 V reverse bias. (b) 2.0 Vpp amplitude and 0 V reverse bias. (c) 3.0 Vpp amplitude and 1.0 V reverse bias. In all eye diagrams, input light is biased at the −3 dB optical point, 1301.91 nm.
Table 1. Comparison to Other Traveling-Wave Modulators in Silicon at 40 Gbps and Above
7. Conclusion
Since the wavelength band near 1300 nm is important for many telecommunications systems, silicon devices that can modulate light in this band are desirable. We present the first silicon modulator to operate at 50 Gb/s near 1300 nm. We measure a small-signal VπL as low as 2.43 V-cm, as well as demonstrate a thermal phase tuner with tuning efficiency 27 mW/π. By introducing intermediate dopants in the phase shifter to reduce series resistance we are able to improve bandwidth while maintaining a small VπL and low insertion loss. We have demonstrated a 50 Gb/s eye diagram using a differential 1.5 Vpp signal at a 0 V reverse bias, and achieved a power consumption of 450 fJ/bit.
Acknowledgments
The authors would like to thank Gernot Pomrenke, of the Air Force Office of Scientific Research, for his support under the OPSIS (FA9550-10-1-0439), PECASE (FA9550-10-1-0053), and STTR (FA9550-12-C-0079). The authors gratefully acknowledge support from Brett Pokines, of AFOSR SOARD (FA9550-13-1-0176), and from the Singapore MOE under ACRF Tier 1 and the Singapore NRF Fellowship (NRF2012NRF-NRFF001-143). The authors would also like to thank Mentor Graphics and Lumerical for their ongoing support of the OpSIS project.
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