1. Introduction

Slot waveguides were initially proposed by Almeida et al [1], and consist of two high index ridges separated by a low-index trench. While ridge waveguides tend to confine the majority of the optical mode to the high index material forming the ridge, slot waveguides instead confine the majority of the optical mode to the low-index cladding slot between the two ridges, due to the discontinuous boundary condition on the dielectric interface for the horizontal electric field. On a silicon-on-insulator (SOI) platform, slot waveguides are ideal for certain applications. When using active polymers for a low index cladding, it can be beneficial to have high field intensities concentrated in this material instead of the silicon ridge. This is essential for sensing applications [2–6], as well as electro-optical modulation [7], and nonlinear optics [8,9]. Asymmetric slot waveguides have been used to maintain this high optical field concentration around sharp 1 µm bends [10]. Asymmetric slot waveguides filled with a magnetooptic material have also been investigated as a method to achieve a high nonreciprocal phase shift [11]. Additionally, extraneous loss caused by two-photon absorption in silicon ridges can potentially be lowered with the use of slot waveguides, since more of the optical mode is concentrated in the cladding material between the silicon.

A significant limitation with slot waveguides has been the high levels of waveguide loss typically encountered. The current best literature result for standard slot waveguides is 10 dB/cm [12], and 4.0 dB/cm [13] has been demonstrated for segmented slot waveguides. However, these results were obtained with electron-beam lithography. Strip-loaded slot waveguides have been photolithographically fabricated with as low as 6.5 dB/cm loss [14], but these waveguides are intended for electro-optic modulator applications where electrical contact to the waveguide arms is necessary and do not have as good mode confinement in the slot. By contrast, ridge waveguides and shallow ridge waveguides have been fabricated that achieve optical losses as low as 0.92 dB/cm [15] and 0.274 dB/cm [16], respectively. Etchless silicon waveguides have also been fabricated with optical losses of 0.3 dB/cm [17]. High propagation losses have typically been seen as a fundamental limitation to vertical slot waveguides, and this has led to the pursuit of horizontal slot waveguides as an alternative; recently 2 dB/cm losses were obtained [18]. But horizontal waveguides will likely be impractical for a number of applications, such as situations that involve polymer claddings. Here we show that low losses can be obtained with a vertical slot waveguide; we demonstrate asymmetric slot waveguides with a 130 nm slot that achieve optical propagation losses as low as 1.7 ± 1.1 dB/cm, when coated with Poly(methyl methacrylate) (PMMA).

2. Geometries

A key design goal for many applications in integrated optics is the suppression of higher order modes, while maintaining a large distance between the TE0 cutoff and the wavelength regime of interest. Asymmetric waveguide designs tend to suppress the TE1 mode nearly as well as an equivalent symmetric design while better extending the cutoff for the TE0 mode. The dispersion relation showing the range in which these modes are guided is shown for different slot positions in Fig. 1 . Dispersion relations were simulated with commercially available RSoft software [19]. This in turn increases the range of cladding indices over which the waveguides function, and increases tolerance of fabrication error, since the TE0 mode can be kept far from cutoff, without risking multimode behavior. This is especially important in situations where the precise size of the eventual slot is not known prior to fabrication, as was the case in our work. We report on three different slot waveguide designs, as shown in Table 1 . The design with the smallest slot (design A) had a slot dimension of 130 nm, with arms 320 and 100 nm. The cutoff wavelength for the TM0 mode is near 0.93 µm, while the TE0 mode is cutoff near 1.67 µm. Design B had a 180 nm wide slot with arms 310 and 100 nm wide. Design C also had a 180 nm wide slot with arms 290 and 80 nm wide.

 

Fig. 1 (a) A Dispersion diagram showing TE0 and TE1 modes for various slot offset amounts of design A. Design A implies a 110 nm slot offset from an initial symmetric design of two 210 nm wide arms and a 130 nm slot resulting in a 130 nm slot with 320 and 100 nm wide arms. The corresponding dispersion curve for design A is shown in red. Adding an offset to the location of the slot extends the guiding range for the TE0 mode greatly, while minimally changing the TE1 cutoff. (b) A similar dispersion diagram for varying degrees of asymmetry of design B (shown in red). (c) A similar dispersion diagram for varying degrees of asymmetry of design C (shown in red).

Download Full Size | PDF

Table 1. Waveguide Propagation Loss for Three Different Waveguide Geometries

View Table

A large portion of the electric field remains concentrated in the slot region, as shown in Fig. 2 a . The χ3 effective area for cladding interaction, A_eff, is defined in reference 13 and characterizes the intensity of the electrical field traveling through the active polymer-clad slot region, and therefore the degree of nonlinear enhancement from a waveguide design [20]. A smaller effective area is desirable as it implies a greater χ3 nonlinear response for a given amount of power. For our asymmetric slot design with the 130 nm slot, design A, A_eff is 0.60 µm², which can be compared to an effective area of 0.19 µm² for a comparable symmetric 130 nm slot design with 210 nm arms – in this case, performance is slightly decreased by a factor of 3.2. However, compared to a 500 x 220 nm ridge waveguide, the performance of this asymmetric design is still very attractive. The ridge waveguide achieves an effective area of 5.61 µm², or almost 9.4 times the A_eff for design A. The effective areas for 130 nm slot waveguide designs with varying degrees of asymmetry from design A are shown in Fig. 2. A_eff for 180 nm wide slot designs B and C are 0.51 and 0.43 µm² respectively. If further slot shrink can be achieved, then the effective areas for asymmetric slot waveguides become even more favorable, while still suppressing the TE1 mode and extending the range where TE0 is guided. For example, the effective area of a design with a 60 nm slot, and 360 nm and 140 nm arms is 0.32 µm².

 

Fig. 2 (a) Optical mode pattern of reported 130 nm slot waveguide with 320 and 100 nm arm widths (design A). This design implies a slot offset of 110 nm. The electric field intensity, |E_x|, is indicated by the contour colors and is normalized to a total mode power of 1 W. (b) Mode pattern for 130 nm slot with slot offset of 80 nm. (c) Mode pattern for 130 nm slot with slot offset of 50 nm. (d) Mode pattern for 130 nm slot with slot offset of 20 nm. (e) Mode pattern for perfectly symmetric 130 nm slot. χ3 effective area, A_eff, is shown for each geometry.

Download Full Size | PDF

3. Fabrication

Figure 3 shows the lithographic process flow. Waveguides were fabricated on 6” SOI wafers on a 248 nm ASML Scanner at BAE Systems. Wafers began with 220 nm Si on a 3 µm SiO₂ layer, on a silicon handle. An oxide layer was grown via thermal oxidation followed by a 119 nm SiN_x hard mask. Resist was deposited, and then a first photolithography step was applied for all waveguide slots of various dimensions, which were etched through both hard masks and Si. The slot etch was separated from other lithography steps in order to implement a BAE Systems proprietary resist shrink technique process to shrink the slot size beyond lithography resolution.

 

Fig. 3 Lithographic process flow. Second partial etch step for unrelated devices, and BAE Systems proprietary resist shrink technique process are not shown: (a) Begin with 220 nm Si on 3 µm SiO2 (b) Deposit 119 nm SiNx hard mask (c) Deposit resist and apply first photolithography step (d) First etch through both hard masks and Si (e) Deposit resist and apply third photolithography step (f) Third etch through both hard masks and Si (g) Oxide layer grown around slot arms (h) Nitride and oxide layer are stripped.

Download Full Size | PDF

A second photolithography step was applied for partial etching for unrelated devices. A third lithography step was applied and slot waveguide arm sidewalls were fully etched through the Si layer. A thin oxide layer was then grown around silicon slot arms for sidewall smoothing, followed by removal of the nitride via phosphoric acid. Finally, the oxide layer was stripped, resulting in 200 nm thick Si slot waveguides. Oxidation resulted in the consumption of around 30 nm of silicon on slot arms, increasing the slot widths to 130 nm and 180 nm. The alignment variation between the two photo steps caused the slot asymmetry to vary between runout sections of each device and device-to-device. Reported waveguide arm dimensions seen in Table 1 had a standard deviation of up to roughly 20 nm, which is a function of the linewidth variations of two photo steps and the alignment of these two steps. Waveguide slot sizes were much more consistent, with standard deviations up to roughly 10 nm. Waveguide dimensions were measured in a scanning electron microscope.

Devices were then clad with PMMA in order to closely match the optical index of a typical electro-optic polymer that might be used for nonlinear optical experiments [21]. MicroChem 950PMMA A (11% solids in Ansole) was spun at 2000 rpm for 45 seconds and baked at 180 degrees Celsius for 90 seconds, resulting in an expected thin-film thickness of around 3 µm [22]. The optical index of the PMMA used is approximately 1.49 and has optical losses around 0.9 dB/cm at 1550 nm wavelengths [23].

4. Measurement

Five slot waveguide devices for each of the specified geometries were placed on each chip. Grating couplers were used to couple light into devices. Typical couplers have a 3 dB bandwidth of 35 nm. Devices begin with a 0.44 µm wide ridge waveguide section before butt-coupling (for designs B and C) or curve-coupling (for design A) into slot waveguide sections. FDTD simulations suggest ridge-to-slot butt couplers result in about 3 dB of insertion loss and ridge-to-slot curve couplers result in about 0.5 dB of insertion loss. There is both an outgoing and incoming slot waveguide section for each device, connected by another short ridge waveguide section. A Y-junction is seen on each device used for an unrelated experiment. FDTD simulations suggest each junction has around 1 dB excess loss, leading to 4 dB loss for the configuration we use in our experiment. All couplers, bends, ridge waveguide sections, and y-junctions on each set of five slot waveguide devices are identical.

Measurements were taken with an Agilent 81980A fiber-coupled laser and 81636B detector. The laser emitted 1470 – 1570 nm light at power levels varying for tests between −3 and 12 dBm. A polarization rotator was used in order to ensure TE polarized light was coupled into the waveguides. A fiber array was used to couple light into input and output grating couplers. The noise floor of the measurement was typically near −70 dB for 12 dBm input power, with signal to noise ratios of more than 35 dB typically encountered for the highest loss devices measured.

Output power was measured from the collection of these devices on each chip. Because all components of each device except for the length of the slot waveguide section were identical, it was possible to characterize the slot waveguide propagation loss independent of the other sources of loss, including losses from grating couplers, y-junctions, or the ridge waveguide to slot waveguide mode couplers. Devices with slot sections between 860 and 7900 µm in length were placed in close proximity as seen in Fig. 4 . This layout minimized the possibility of fluctuations in coupling efficiency caused by grating coupler location on the chip. For each device tested, a wavelength sweep was taken across the peak grating coupler performance. The resolution of wavelength sweeps was finer than 0.01 nm in all cases. Sharp Fabry-Perot fringes can be seen in the spectrum. These are likely due to backreflections from the grating coupler. For a photonic circuit with minimal optical loss, even a backreflection of −10 dB can cause fringes on the order of 2 dB peak to peak, as are seen here. The fringe periodicity is quite short, under 0.1 nm, as should be expected for a very long path length. To more accurately determine a consistent optimal transmission for each device, a quadratic curve was fit to the 16-20 nm sections surrounding the maximum transmission value of each device. The maximum value of this quadratic fit was used to determine the optimal transmission from each device. A linear regression was calculated between these optimal transmissions and device length in order to determine slot waveguide loss per cm.

 

Fig. 4 Scanning electron micrograph of cleaved end-facet of a typical 130 nm slot waveguide device (top left). Optical micrograph of grating couplers and slot runout sections for three 130 nm slot waveguide devices (bottom left). Layout for a typical set of slot waveguide runouts devices (right). Optical micrograph includes PMMA, which is stripped for electron micrograph.

Download Full Size | PDF

Losses were calculated for devices on a number of chips, the results of which are shown in Table 1. One significant source of uncertainty was due to variation in coupling loss getting on and off the chip. As a result, we estimated the coupling uncertainty for each data point based upon the uncertainty of grating coupler input and output insertion losses. This is characterized by the standard deviation in coupling losses for 9 short grating coupler loops in close proximity. As shown in Fig. 5 , for example, this likely overstates the level of uncertainty actually encountered on some tests, since it would appear that the linear regression falls well within 1 sigma or less for each of the five data points. For each result shown in Table 1, we report either the coupling uncertainty, or the uncertainty due to the least squares regression [24]. In order to be maximally conservative, we used the higher uncertainty in each case.

 

Fig. 5 (a) Normalized wavelength sweeps of devices of different lengths of design A on chip 1. A quadratic fit is seen with each device used to determine peak optical transmission. The signal-to-noise ratio for the best performing device is 44 dB. (b) Normalized optical power vs. waveguide length for these devices. Error bars show uncertainty of loss due to grating couplers. A linear regression shows 1.7 ± 1.1 dB/cm propagation loss as seen in Table 1. The linear fit falls well within one standard deviation of all of the data points, suggesting our uncertainty estimation may overstate the true level of statistical variation encountered in each measurement. (c) Normalized optical power vs. waveguide length for a single test of design A, chip 2. A linear regression shows 2.9 ± 0.4 dB/cm propagation loss, within one standard deviation of the mean propagation loss of 2.4 ± 0.9 dB/cm shown in Table 1.

Download Full Size | PDF

Repeated measurements were used on some chips to confirm the reliability of the measurement technique. 3 measurements were taken on chip 2, 7 measurements were taken on chip 5, and 4 measurements were taken on chip 6. For chips in which multiple tests were taken, an average loss is shown, with an error statistically propagated from individual tests. In order to confirm that losses were not due to optical nonlinear effects, two tests on different chips were taken with a power level 6 dB different than the other tests. The propagation loss for these tests was consistent with other tests and is included in average loss values reported.

The primary source of optical propagation loss in our asymmetric slot waveguides is likely surface roughness and sidewall roughness [25]. Although we were not able to experimentally characterize roughness, several methods to predict scattering loss due to roughness have been theoretically investigated [26,27]. PMMA offers a bulk absorption loss of 0.9 dB/cm for 1550 nm wavelengths, and we therefore calculate [28] that PMMA should contribute near 0.5-0.6 dB/cm to the optical propagation loss. Both the silicon itself (with a resistivity of 14-22 Ω-cm) and buried SiO₂ layer are expected to offer negligible optical propagation loss. Loss due to substrate leakage should also be negligible for a 3 µm buried oxide layer.

5. Conclusion

In conclusion, we have shown that optical losses for narrow slot waveguides can approach those of ridge waveguides, making slot waveguides a practical alternative for certain applications. We have shown 130 nm asymmetric slot waveguide designs with low losses of 1.7 dB/cm. We demonstrate low losses for two other 180 nm slot waveguide designs. Further improvements in the lithography and processing will hopefully enable the ultimate slot size to decrease, while maintaining the current losses, which should increase the utility of these waveguides even further.