1. Introduction

Plasmonics has been at the forefront of research aimed at developing the next generation of integrated devices capable of delivering high bandwidth information processing at the nanoscale. Plasmonic devices offer the combined advantages of ultrafast optical signal processing capabilities of photonics and the potential for subwavelength modal confinement, potentially leading to device integration at a scale comparable to electronics. To achieve the goal of realizing plasmonic integrated circuits, many waveguiding schemes have been explored such as Long-Range Surface Plasmon Polaritons (LRSPP) [1], Dielectric-Loaded Surface Plasmon Polaritons (DLSPP) [2], Metal-Insulator-Metal (MIM) [3–5] and Channel Plasmon Polaritons (CPP) waveguides [6]. A typical challenge in these structures is the tradeoff between strong optical field confinement and propagation length. For example, MIM waveguides can provide modal confinement below the diffraction limit but their large propagation losses prevent the surface plasmon polaritons (SPP) from going further than a few wavelengths [4,5]. Structures based on LRSPPs, on the other hand, can support SPP with centimeter-range propagation lengths but their modes are loosely confined and diffuse over a large area [1]. Nanoscale confinement and low losses are both essential for achieving very dense integration of practical plasmonic circuits.

Recently, a new type of plasmonic waveguides referred to as hybrid plasmonic waveguides or conductor-gap-dielectric waveguides has generated considerable interest due to their ability to provide both subwavelength confinement and long propagation lengths [7–11]. These waveguides resemble the Insulator-Metal (IM) waveguide structure, except that a very thin gap of low-index material separates the metal layer and a higher-index dielectric layer. Theoretical analyses show that the gap can support a low-loss compact mode whose propagation length is a strong function of the gap size [9]. The high-index dielectric layer is typically patterned to form a rectangular or cylindrical core, which supports a photonic-like mode. By adjusting the gap size, the composite waveguide mode can be varied from plasmonic to photonic, allowing a wide range of modal characteristics such as strong confinement and long propagation length to be accessible.

Recently, a laser based on the conductor-gap-dielectric waveguide structure has been demonstrated using MgF₂ as the gap material and a CdS cylindrical rod as the high-index medium [12]. With the emergence of silicon as an important photonic material, it is of particular interest to demonstrate plasmonic devices and functionalities in silicon. In addition to the potential for seamless integration with CMOS electronics as well as conventional silicon photonics on the same chip, silicon plasmonic devices offer the possibility of achieving ultrafast all-optical switching using the nonlinear properties of silicon [13], as well as the possibility of introducing gain via Raman amplification or optical parametric amplification. A major challenge with silicon plasmonics, however, is that due to the high index of silicon, conventional subwavelength plasmonic waveguides such as MIM are extremely lossy, having propagation lengths of only a few microns [4,5]. In this respect, the conductor-gap-dielectric waveguide structure, with its low loss and strong confinement characteristics, provides a particularly promising platform for realizing practical silicon plasmonic devices with advanced functionalities.

In this paper, we present the first experimental realization, to the authors’ knowledge, of low-loss subwavelength conductor-gap-silicon (CGS) plasmonic waveguides, achieving a long propagation length of 40µm. We also experimentally explore the use of CGS plasmonic waveguides to demonstrate the operation of building blocks for integrated components such as S-bends and Y-splitters with low loss. In addition, a simple taper coupler is developed to provide highly efficient coupling between plasmonic waveguides and conventional silicon photonic waveguides on the same silicon-on-insulator (SOI) chip. The monolithic integration of plasmonic and photonic devices, combined with a CMOS-compatible fabrication process, can pave the way to highly functional plasmonic integrated circuits [14,15].

2. Conductor-gap-silicon plasmonic waveguide design and analysis

The conductor-gap-silicon plasmonic waveguide studied in this paper has a similar structure to that proposed in [9], with the silicon layer completely etched through as depicted in Fig. 1(a) . The waveguide core consists of a thin SiO₂ layer of thickness h _SiO2 and index n = 1.44, sandwiched between a gold layer of thickness h _Au and a Si layer of thickness h _Si and index n = 3.48. Lateral confinement is achieved in the structure by patterning through the Au-SiO₂-Si layers to form a rectangular waveguide core of width w. Surface plasmon at the Au-SiO₂ interface and the discontinuity in the E _y field component at the Si-SiO₂ interface give rise to a strongly enhanced electric field distribution in the SiO₂ gap, which is referred to as a gap mode [11]. Some residual power is also guided in the rectangular silicon core, forming what is referred to as the photonic component of the mode, a designation which lends itself to the interpretation of the guided mode as hybrid in nature. Since the photonic mode is associated with low loss propagation while the gap mode provides strong confinement, by varying the SiO₂ thickness, various degrees of hybridization can be achieved which corresponds to a wide range of modal characteristics in terms of propagation length and mode confinement. The degree of hybridization may be quantified by the ratio of the powers confined in the SiO₂ gap and the Si core, which is plotted as a function of the gap size in Fig. 1(b) for a waveguide structure with dimensions h _Au = 50nm, h _Si = 340nm, w = 200nm at 1550nm wavelength. In the numerical simulations, we assumed the dielectric constant of Au to be ε_r = −132 − 12.65i [16]. A maximum can be clearly seen in the plot which is indicative of a major plasmonic component for gap sizes in the 20-60nm range. For gap sizes below 20nm, the power in the gap drops precipitously as the gap area shrinks to zero. As the gap size increases above 60nm, the power in the gap begins to leak out into the Si core, causing the power ratio to slowly decrease.

 

Fig. 1 (color online) (a) Conductor-gap-silicon plasmonic waveguide structure showing the E _y field distribution of the quasi-TM mode. (b) Ratio of the powers inside the SiO₂ gap and the Si core at varying gap thickness. (c) Propagation length at varying gap thickness. In the above cases, the device parameters are h _Au = 50nm, h _Si = 340nm and w = 200nm at 1550nm wavelength. (d) Propagation length at varying waveguide widths for different values of gap and gold thickness.

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Figure 1(c) shows the dependence of the propagation length L_p of the CGS waveguide on the thickness of the SiO₂ gap. It is seen that the propagation length increases monotonically with the gap size as the mode becomes increasingly more photonic. Figure 1(d) plots the propagation length of the waveguide at different widths for some representative values of the SiO₂ gap and the metal thickness. Along with the gap size, the width of the waveguide plays a significant role in the propagation length and, to a lesser extent, so does the metal layer thickness. For our fabricated waveguides, the Si core dimensions were set to be h _Si = 340nm and w = 200nm ~250nm. The thicknesses of the gold layer and SiO₂ gap were targeted to be in the range h _Au = 50 ~60nm, h _SiO2 = 50 ~60nm. These parameters were chosen to achieve maximum power confinement in the gap while still yielding a relatively long propagation length in the range of 23µm ~45µm at the 1550nm wavelength. By contrast, we note that without the SiO₂ gap, the waveguide structure is simply a metal-dielectric plasmonic waveguide with a short theoretical propagation length of only 4µm.

Figure 2(a) gives a plot of the simulated E _y-field distribution of the fundamental quasi-TM mode, showing that the mode is predominantly confined inside the subwavelength SiO₂ gap. Figure 2(b) shows the field distribution along the x-axis at the metal-SiO₂ interface. Confinement in the x-direction is primarily due to the index contrast between the SiO₂ and the surrounding air, yielding a lateral mode size that is roughly equal to the width w of the metal strip. Figure 2(c) gives the field distribution along the y-axis through the center of the waveguide, showing a large electric field enhancement in the gap and some residual field in the Si core. It will be shown that the residual photonic mode in the Si core plays an important role in allowing efficient coupling from the CGS waveguide to a SOI dielectric waveguide to be achieved.

 

Fig. 2 (color online) (a) Simulated |E _y| field distribution of the fundamental quasi-TM mode in the CGS plasmonic waveguide. (b) Cross section of the |E _y| field distribution in the x-direction at the metal-SiO₂ interface. (c) Cross section of the |E _y| field in the y-direction through the center of the waveguide.

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We also note that it was recently suggested that the two dimensional conductor-gap-dielectric waveguide structure can support a low-loss and tightly-confined gap mode if the SiO₂ gap thickness is reduced below a certain critical thickness, which for the Au-SiO₂-Si system was determined to be 3.5nm [11]. However, the simulation results for our three dimensional structure in Fig. 1(c) show no presence of such a critical thickness near that gap size nor at any other value over a wide range. Also, from the fabrication point of view, achieving such a thin gap layer would also be very challenging. Because of fabrication issues and other considerations such as efficient coupling into the plasmonic modes, we found that it is more practical to design our CGS waveguides to operate in the “large-gap” regime as identified in [11].

3. Fabrication and measurement of conductor-gap-silicon plasmonic waveguides

The conductor-gap-silicon waveguides were fabricated on a SOI substrate consisting of a 340nm thick crystalline silicon layer on a 1µm buried oxide layer. The chip was first deposited with a 50nm layer of SiO₂ using plasma-enhanced chemical vapor deposition. Next, an electron beam lithography (EBL) step was used to define the plasmonic waveguides with a nominal width of 200nm. A 50nm-thick gold layer was sputtered onto the chip followed by a lift-off process to lay down the metallic strips of the waveguides. Due to variation in the deposition process, the final SiO₂ and gold thickness can vary up to 60nm. A second EBL step was used to define the underlying Si core of the plasmonic waveguides, as well as the input/output (I/O) silicon waveguides and taper couplers for direct light coupling between the plasmonic and silicon waveguides. Due to alignment error, the width of the underlying Si core of the plasmonic waveguide can be as much as 50nm wider than the Au strip which was accounted for in the simulations. The EBL resist pattern was transferred into the chip by reactive ion etching through the SiO₂ gap and silicon layer. Figures 3(a) and 3(b) are scanning electron microscope (SEM) images of the cross section and top view of a typical fabricated plasmonic waveguide. Also visible in the top-view SEM image are the plasmonic taper couplers and I/O silicon waveguides connected to each end of the plasmonic waveguide. The width of the I/O silicon waveguides is 1µm. The dimensions and performance of the taper couplers are described in the next section.

 

Fig. 3 (color online) (a) SEM image showing the cross section of a 250nm-wide CGS plasmonic waveguide (left) beside a 600nm-wide Si waveguide for comparison. The Si layer is 340nm high with a 50nm-thick layer of SiO₂ on top. The plasmonic waveguide is capped with an extra 50nm-thick gold layer. (b) Top-view SEM image showing the CGS waveguide, the taper couplers and I/O silicon waveguides. (c) Measured values (dots) and fitted curve (blue line) of the transmitted powers of CGS waveguides of different lengths.

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The devices were measured by coupling TM-polarized light from a tunable laser to the input silicon waveguide and measuring the transmitted power in the output silicon waveguide. Figure 3(c) plots the measured transmitted powers through straight plasmonic waveguides of lengths 10, 30, 50 and 70µm at the 1550nm wavelength. By fitting the measurement data with the curve P(z) = P(0)exp(−z/L_p), we obtained a propagation length L_p of 40µm for the plasmonic waveguides. This value falls within the range of the calculated values for CGS waveguides with h _SiO2 and h _Au between 50nm and 60nm as discussed in the previous section. We note that the propagation length can be extended even further by increasing the SiO₂ gap size.

4. Taper coupler

A simple taper coupler was devised to facilitate direct and efficient coupling between the I/O silicon waveguides and the plasmonic waveguides. Our coupler design exploits the fact that the degree of hybridization of the conductor-gap-dielectric waveguide can be continuously tuned by varying the conductor width w, thus allowing for efficient transition from a purely photonic mode in the Si waveguide to a predominantly plasmonic mode of the CGS waveguide. Figure 4(a) shows a schematic of the coupling structure, which consists of a taper from the silicon waveguide width of 1µm down to the plasmonic waveguide width of 200nm over a short taper length of 1µm. A smaller metal strip width of 700nm at the beginning of the taper is used to compensate for alignment issues. At the wide end of the taper, most of the power resides in the photonic mode, enabling near perfect mode matching with the silicon waveguide so the coupling efficiency is very high. As the width is tapered down to 200nm, the mode becomes increasingly more plasmonic and the power in the Si core is gradually transferred into the SiO₂ gap. This power transfer process is visualized by the three-dimensional finite-difference time-domain (3D FDTD) simulations of the structure at 1550nm wavelength in Figs. 4(c) and 4(d). Figure 4(c) plots the side-view E _y-field distribution along the center plane of the taper, showing power launched in the silicon waveguide from the left is gradually transferred and concentrated in the thin SiO₂ layer of the CGS waveguide. Figure 4(d) gives the top-view field distribution in a horizontal plane through the center of the SiO₂ gap, showing light being focused into the CGS waveguide by the taper. From the FDTD simulations we computed the theoretical coupling efficiency of the taper coupler to be 88%.

 

Fig. 4 (color online) (a) Schematic of the plasmonic taper coupler. (b) SEM image of a fabricated plasmonic taper. (c) Side view of the E _y-field distribution in a vertical plane through the center of the coupler obtained from 3D FDTD simulation. Power is input from the Si waveguide at the left. (d) Top view of the simulated E _y-field distribution in a horizontal plane through the center of the SiO₂ gap of the coupler.

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In our fabricated devices, the tapers were used to connect each end of the plasmonic waveguides to the I/O silicon waveguides, as shown by the SEM image in Fig. 4(b). To experimentally determine the coupling efficiency of the fabricated couplers, we note that the value P(0) = 33.55µW in the exponential curve fit in Fig. 3(c) is equal to α² P _in, where α is the coupling efficiency per taper and P _in is the power in the input Si waveguide. Separate measurements of the transmitted power through straight silicon waveguides without the plasmonic waveguides gave the reference power P _in = 52.5µW, from which we obtained a coupling efficiency α = 80% for each taper. This value is in excellent agreement with our FDTD simulation results, confirming that very high coupling efficiency can be obtained between the silicon and CGS waveguides using the simple taper structures.

5. Plasmonic S-bends and Y-splitters

The density of integration of plasmonic components depends on how tightly plasmonic waveguides can be bent without incurring large bending loss. It is thus of practical importance to assess the bending loss of our CGS waveguides. Notably, we found that although most of the field is confined in the SiO₂ gap, which does not have a large lateral index contrast with respect to the air cladding, very tight CGS bends with low loss can still be achieved.

We first investigated the theoretical loss in tightly-bent CGS waveguides by numerically computing the complex eigenvalues of waveguide bends in cylindrical coordinates [17]. The theoretical loss extracted from the imaginary part of the eigenvalues includes both the bending loss and conductor loss. This is plotted as a function of the bending radius in Fig. 5(a) (blue solid line). It is seen that the loss increases exponentially as the bending radius is reduced below about 1μm, indicating that bending loss is the dominant source of loss in very tight CGS bends. For bending radii above 1μm, the loss is independent of the bending radius, indicating that loss in these bends is mainly due to attenuation in the conductor. For comparison, we also plotted in Fig. 5(a) (red dashed line) the loss of bent Si dielectric waveguides having identical dimensions to the CGS waveguides but without the conductor layer. It is seen that bending loss in the Si waveguide increases much more rapidly with decreasing radius than the CGS bends, implying that surface plasmon polaritons play an important role in reducing the bending loss in CGS waveguides as a result of the strongly bound field at the metal-dielectric interface. For bending radii below about 0.8μm, the CGS bends are actually less lossy than the Si bends. This result suggests that it is possible to realize very compact CGS ring resonators with intrinsic quality factors higher than achievable in silicon microrings.

 

Fig. 5 (color online) (a) Theoretical loss in CGS plasmonic bends (solid blue line) and Si dielectric photonic bends (dashed red line) as functions of bending radius. The dimensions of the waveguides are h _Au = h _SiO2 = 50nm, h _Si = 340nm, w = 200nm at the 1550nm wavelength. (b) 3D FDTD simulation result of the E _y-field distribution in a 2µm-radius CGS S-bend at 1550nm. The cross section is through the SiO₂ gap. (c) Same simulation with cross section through the center of the Si layer where the field is much weaker in the Si than in the SiO₂ gap. (d) SEM image of the fabricated CGS S-bend with 2μm radius. (e) Wavelength scan of the normalized transmitted power of the fabricated CGS S-bend.

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We next performed 3D FDTD simulations of plasmonic S-bends comprised of two 90-degree turns to determine the total losses of these structures. The results for the E _y-field in a 2μm-radius S-bend are shown in Fig. 5(b) and 5(c). Figure 5(b) shows the field distribution on a horizontal plane through the center of the SiO₂ gap while Fig. 5(c) shows the distribution through the center of the Si layer. The losses are more visible in the latter since the field in the Si layer is weaker. The total transmission loss through the bend obtained from the simulation was 2.3dB. Since the theoretical loss for two 90-degree turns with 2μm radius is less than 1dB, we attribute the extra loss in the S-bend to scattering from the junctions between the two 90-degree arcs as well as between the arcs and the connecting I/O straight waveguides.

Conductor-gap-silicon S-bend structures consisting of two 90-degree arcs with radius of 1µm and 2µm were fabricated and measured to assess the experimental transmission loss of these structures. Figure 5(d) shows an SEM image of the fabricated S-bend with a 2µm radius. Figure 5(e) shows the measured transmitted power of the S-bend as a function of wavelength. The S-bend power was normalized to the power transmitted through a straight plasmonic waveguide of the same length as the S-bend, so that the plotted power represents the excess loss in the S-bend caused by bending loss and junction scattering. Over the scanned wavelength range, the average excess loss is about 1.4dB for this structure, which we attribute mostly to junction scattering loss since the bending loss is negligible at this radius. Adding conductor loss, the total S-bend loss amounts to 2.05dB, which is comparable to the value of 2.3dB obtained from FDTD simulation. By comparison, we note that S-bends using metallic V-grooves with 2.25µm radius were reported to have a total transmission loss of about 2.3dB [6].

For the smaller plasmonic S-bend with a 1μm radius, the theoretical transmission loss obtained from FDTD simulation was 3.14dB. Measurement of the fabricated structure gave an excess loss around 3dB, out of which 0.4dB can be attributed to bending loss and the rest due to junction scattering. Adding the conductor loss, the total experimental transmission loss through the S-bend was 3.34dB, which is in good agreement with the value from FDTD simulation. The results for the 1μm and 2μm-radius S-bends show that in both structures, junction scattering loss is a significant source of loss. By introducing a junction offset to reduce the mode mismatch between the two arc waveguides, the junction scattering loss can be minimized, yielding plasmonic S-bends with much lower loss.

We also designed and fabricated plasmonic Y-splitters by interposing two plasmonic S-bends. An SEM image of a Y-splitter with a 2µm bending radius is shown in Fig. 6(a) . Three-dimensional FDTD simulations of the structure showed the transmitted power is evenly split between the two waveguide arms, as shown by the E _y-field distribution in Fig. 6(b). The graph in Fig. 6(c) presents the transmitted powers measured at the outputs of the two branches of the Y-splitter with a 2µm bending radius. The powers were normalized to the average total power at the two outputs. A relatively constant power splitting ratio of 50% ( ± 7%) over the scanned wavelength range is achieved, indicating the equal power splitting and broadband response of the Y-splitter. The device has a measured transmission loss of 3.57dB. We also fabricated Y-splitters with 1μm and 3µm bending radius, both showing even power splitting ratios within a standard deviation of ± 10%. We expect these broadband power splitters to be useful for constructing more advanced CGS devices such as Mach-Zehnder interferometers.

 

Fig. 6 (color online) (a) SEM image of a fabricated CGS Y-splitter with 2μm bending radius. (b) 3D FDTD simulation result of the E _y-field distribution in the Y-splitter at 1550nm wavelength. (c) Wavelength scan of the transmitted powers in the two output branches of the plasmonic Y-splitter.

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6. Conclusion

In conclusion, we have demonstrated the operation of conductor-gap-silicon plasmonic waveguides, S-bends and Y-splitters. A long propagation length of 40μm and efficient coupling to conventional silicon waveguides characterize these devices. The strong mode confinement in the SiO₂ gap and the small footprint of these structures can be exploited for building very compact and low-loss plasmonic devices on an SOI platform. More advanced devices such as ring resonators and interferometers based on the CGS waveguide structure could lead the way to active devices that will enable modulating and all-optical switching functions based on nonlinear effects in the silicon core. Also, the strong electric field enhancement in the SiO₂ gap can be explored to provide gain, e.g., by doping the gap layer with Erbium or other suitable materials. We anticipate the conductor-gap-silicon waveguide to provide a versatile platform for realizing highly-functional plasmonic integrated circuits at subwavelength scale.