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Abstract
We design, fabricate, and demonstrate a low-loss and broadband optical interposer with high misalignment tolerance for large-scale integration of many chips using thermal compression flip-chip bonding. The optical interposer achieves flip-chip integration with photonic integrated circuit die containing evanescent couplers with inter-chip coupling loss of 0.54dB and ±3.53μm 3-dB misalignment tolerance. The loss measurement spectrum indicated wavelength-insensitive loss across O-band and C-band with negligible spectral dependence. Further, we demonstrate 1 to 100 wafer-scale equal power splitting using equal power splitters (EPS) and a path length matching design fabricated using a wafer-scale fabrication technique.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
The explosive growing demands for sensing [1], optical computing [2], and data communication [3] require large-scale and energy-efficient electro-optics integrated photonics systems [4], while the integration difficulty, cost, and yield limit the size and function of a single chip. Therefore, co-packaged multi-chip integration is investigated to improve performance and capabilities [5,6]. Optical interposer supporting many function blocks with electrical and optical connection brings solutions for complex electro-optics integrated systems, such as large-scale light detection and ranging (LIDAR) with wide emitting apertures [7], and high-performance computing (HPC) systems assisted by optical interconnects [8,9]. Such systems demand the optical interposer to realize large-scale, high integration density, high throughput, high energy efficiency, and simplicity in packaging [10,11].
A critical component in the optical interposer is the inter-chip coupler, which couples light between the interposer and photonic chips to support a high-efficiency signal transfer between the photonic chips under achievable packaging quality, with enough bandwidth to support the desired applications. Inter-chip couplers based on gratings typically suffer from a high coupling loss and/or narrow bandwidth [12]. Polymer waveguides offer a low-loss and broadband inter-chip coupler solution at the cost of relatively low reliability and temperature tolerance [13–15]. The silicon nitride(${\rm Si_3N_4}$) platform [16–18] serves as an excellent candidate for the optical interposer because it enables low-loss and broadband transition for compact inter-chip coupling [19] thanks to the low index contrasts between the core and cladding material. In this work, photonic integrated circuits(PICs) are flip-chip bonded onto the optical interposer using a thermal compression bonding process during packaging with an optical connection enabled by the inter-chip couplers. Meanwhile, the two bonded pads maintain the electric connection.
Another challenge of the interposer is to extend the interposer to a large scale, considering the single die size for deep-ultraviolet(UV) lithography steppers or scanners is typically below 3cm on one exposure [20] for multi-chip packaging. The low propagation loss and high fabrication tolerance of the ${\rm Si_3N_4}$ waveguides are beneficial for wafer-scale routing. This work presents a wafer-scale equal power distribution to split the input power evenly into a 10$\times$10 array across a 6-inch wafer realized by a fabrication technique utilizing a combination of projection and contact lithography to extend the optical interposer to a wafer scale. We achieve equal power splitting using EPSs and a path length-matching design to support wavelength and temperature-insensitive operation to first order.
This work presents a low-loss broadband inter-chip coupler with high packaging tolerance to support applications from 1200nm to 1600nm wavelength. At 1550nm wavelength, the inter-chip coupler has a 0.54dB coupling loss and a 3.53$\mu$m 3-dB misalignment tolerance. We present a wafer-scale equal power distribution for future large-scale photonic integrated systems.
2. Low-loss broadband inter-chip coupler design
A conventional flip-chip bonding process can achieve a $\pm 0.5 \mu$m misalignment after placement [21,22], which could significantly increase after the bonding. The optical coupling efficiency could be impaired under such misalignment. Thus, our design aim is to minimize the inter-chip coupling loss under an achievable post-bonding misalignment.
We use the wavelength-insensitive evanescent coupling on the ${\rm Si_3N_4}$ platform to efficiently couple between chips. We utilize its low propagation loss, large transparency window, and large mode size, brought by the low refractive index contrast on ${\rm Si_3N_4}$/${\rm SiO_2}$ waveguides. We design a low-loss broadband inter-chip coupler using a pair of ${\rm Si_3N_4}$ inversed tapers embedded in ${\rm SiO_2}$ cladding for optical transmission. We use metals at the surface of the chips for bonding, alignment, and electrical connection, as presented in Fig. 1(a). During transmission, the optical beam transmitted in one ${\rm Si_3N_4}$ waveguide is expanded by the inversed taper and coupled to the other taper evanescently. Figure 5 shows the evolution of the mode profile during transmission. The simulation uses a pair of inversed tapers with 500nm cladding on both sides and a 200nm air gap in between. The optical signal incident from the bottom left in Fig. 5(a) transmits across the airgap and is coupled into the upper inversed taper. We performed Au-to-Au flip-chip thermal compression bonding to package the silicon photonics chips [23] to the interposer guided by the alignment marks on the Au layers.
Fig. 1. (a) Schematic of the inter-chip coupler. Alignment marks and bonding pads are on the surface of the two chips. The orange arrows denote the beam propagation direction. The black arrow denotes the chip movement direction during flip-chip bonding. (b) Diagram of the flip-chip and Interposer packaging. The numbers denote (1) scattering loss at the edge of the air trench, (2) scattering loss at the edge of the flip-chip, and (3) coupling loss. (c) Top view and (d) side view diagram of the inter-chip coupler.
We design a test structure with straight waveguides to measure the coupling loss of the inter-chip coupler, as shown in Fig. 1(b). The inter-chip coupler has a $> 50\mu$m longitudinal misalignment (presented in Fig. 1(c)) tolerance, so only lateral misalignment is considered in this work. The test structure includes an array of the inter-chip coupler with a variable lateral offset to measure the coupling loss and the misalignment tolerance. The top cladding thickness was reduced to around 500nm at the coupling region to enhance the coupling efficiency. The flip-chip is plugged into the trench on the interposer during packaging. We adopt a 100nm silicon nitride thickness and a 1000$\mu$m taper length as a trade-off between the misalignment tolerance and device footprint. The total optical loss between the interposer and the flip-chip comes from the optical scattering and optical coupling. Optical mode discontinuity causes scattering loss during optical transmission. There are two discontinuities when the optical signal transmits on the waveguides on the interposer: (1) the edge of the air trench on the interposer, and (2) the edge of the flip-chip, and hence introduce the air trench scattering loss and the flip-chip scattering loss, as shown in Fig. 2(d) with blue and red dashed line box, respectively. Figure 2(a) and (b) show reference waveguides for measuring the scattering loss and the coupling loss, which are both straight waveguides, while the waveguide in (b) goes through two times of scattering. Scattering loss induced by mode discontinuity (as shown in Fig. 4(a-c)) decreases while increasing the interposer exposed cladding thickness and the air gap thickness (shown in Fig. 1(d)). The simulated scattering loss in Fig. 3(a) indicates that the scattering loss at the edge of the air trench dominates the total scattering loss. Figure 3(b) indicates the misalignment tolerance increase with the increase of the taper length. We design a 500nm interposer exposed cladding thickness and a less than 100nm flip-chip cladding thickness as a trade-off between the total inter-chip loss and lateral misalignment tolerance. The waveguide width is 3$\mu$m, and the tip width of all the inversed tapers is 250nm, limited by the minimum feature size of our ASML$^{\rm {TM}}$ PAS 5500 300 deep-UV lithography stepper. The air gap thickness is mainly determined by the sum of the two metal thicknesses on the chips. During bonding and annealing, the two metal pads will be squeezed together, making the gap thickness lower than the sum of the metal thicknesses. The two bonded metal pads enable electrical connections between the bonded chips and the interposer.
Fig. 2. (a) Reference waveguide, (b) reference waveguide with scattering loss, (c)waveguide with scattering loss and coupling loss, and (d) zoom-in view of the black dashed line box in (c). The blue and red dashed line contains the interface that induces the air-trench scattering loss and the flip-scattering loss.
Fig. 3. (a) Simulated scattering loss at the edge of the air trench and flip-chip as a function of bottom cladding thickness. The air gap thickness is 200nm. (b) Simulated coupling loss as a function of lateral misalignment. The gap thickness is 800nm, and the air gap thickness is 200nm,
Fig. 4. (a), (b), and (c) are simulated mode profiles with complete cladding, with 500nm silicon dioxide cladding, and with a 200nm air gap, respectively.
Fig. 5. Simulated beam profile of (a) inverse-taper coupling, (b), (c), and (d) cross-section view of the beam at the beginning, middle, and end of the propagation, with location denoted by the three white lines in (a), respectively.
3. Device fabrication
Figure 6(a-m) shows the fabrication flow chart of our interposer and the flip-chip. The interposer and the fabrication start with an initial wafer cleaning on a 150mm silicon wafer using a ${120}^{\circ}\textrm{C}$ piranha solution. We perform wet oxidation under ${1050}^{\circ}\textrm{C}$ to get a 6$\mu$m ${\rm SiO_2}$ bottom cladding. We then deposited stoichiometric ${\rm Si_3N_4}$ using low-pressure chemical vapor deposition (LPCVD). The interposer and flip-chip waveguide design is patterned onto the ${\rm Si_3N_4}$ layer using deep-UV lithography and etching, as presented in Fig. 6(r). We deposited a 4$\mu$m low-temperature oxide (LTO) on the interposer wafer using LPCVD as the top cladding, followed by a chemical mechanical polishing (CMP) [24]. The polished surface has an average surface roughness of 0.2nm, measured by atomic force microscopy (AFM), as shown in Fig. 6(q). We etch the trench on the interposer using inductively coupled plasma (ICP) etching with low surface damage since the roughness on the trench surface will induce scattering loss because of local discontinuity. After etching, the surface roughness is 0.5nm, as shown in Fig. 6(p). The surface roughness on the two surfaces will induce scattering and increase the coupling loss. On the flip-chip, we deposit a 350nm LTO on top of the patterned ${\rm Si_3N_4}$ layer, and we remove 250nm LTO by CMP to ensure the flip-chip cladding thickness is around 100nm. Using lift-off, we patterned 20nm Ti and 80nm Au on top of the interposer and the flip-chip wafers. Figure 6(n) and (o) present the alignment mark microscope photos on the interposer and the flip-chip, respectively. We perform a ${\rm SiO_2}$/Si deep etching process to make the flip-chip accommodated by the trench on the interposer during packaging and expose the edge of the waveguides on the interposer chip. Figure 6(s) shows the microscope photo of the tapers on the interposer chip after fabrication.
Fig. 6. Fabrication flow chart of (a) initial wafer cleaning; (b) thermal oxidation; (c) ${\rm Si_3N_4}$ deposition; (d) interposer ${\rm Si_3N_4}$ lithography and etching; (e) interposer LTO deposition; (f) interposer CMP; (g) interposer LTO lithography and etching; (h) interposer Ti/Au lift-off; (i) flip-chip ${\rm Si_3N_4}$ lithography and etching; (j) flip-chip LTO deposition; (k) flip-chip CMP; (l) flip-chip Ti/Au lift-off; (m) deep LTO/Silicon etching,(n) and (o) microscope photo of the alignment marks on the interposer and the flip-chip, respectively, (p)AFM measurement of the ${\rm SiO_2}$ surface inside the LTO trench after step (g), (q) AFM measurement of the ${\rm SiO_2}$ surface after CMP, (r) SEM photo of a patterned ${\rm Si_3N_4}$ taper, at the tip, and (s) microscope photo of the tapers.
The diced chips are then cleaned and flip-chip bonded together using a thermal compression bonding with a ${400}^{\circ}\textrm{C}$ temperature, 3N force for 10min. After bonding, we anneal the bonded chips under ${350}^{\circ}\textrm{C}$ and 67N for an hour.
4. Device characterization
We measure the scattering and coupling loss on the fabricated devices using single-mode lensed fibers as input and output in TE polarization around 1550nm wavelength. The measured result shows a total scattering loss of 0.77dB, as indicated in Fig. 7(a), by averaging the two scatterings on a reference waveguide. The minimum inter-chip coupling loss of 0.54dB in Fig. 7(a) occurs when the offset on an inter-chip coupler compensates for the flip-chip bonding misalignment. The inter-chip coupling loss at variable offsets in Fig. 7(b) shows a $\pm$3.53$\mu$m 3-dB tolerance. The post-flip-chip bonding misalignment is estimated to be 5$\mu$m.
Fig. 7. (a) Measured transmission of the reference waveguides and the inter-chip coupler with the highest transmission around 1550nm wavelength and (b) measured inter-chip coupling loss as a function of the offset at 1550nm wavelength.
Figure 8 shows the scattering and coupling loss from 1200nm to 1600nm wavelength. We use a broadband light source, followed by a polarization beam splitter (PBS), and a lensed polarization maintaining (PM) fiber with a calibrated rotation angle to couple light into the devices in TE polarization. The output light from the devices is then coupled into a lensed PM fiber and measured by an optical spectrum analyzer (OSA). The coupling loss is measured at the −5$\mu$m offset, which shows that the inter-chip coupling loss is wavelength insensitive in the designed bandwidth when the misalignment is near zero. The mode size at the C-band is larger than that of the O-band with the same waveguide configuration, which induces a higher scattering loss. The measured scattering loss and coupling loss show our optical interposer can support applications in both C-band and O-band.
5. Wafer-scale optical power distribution
Complex electrical-optical systems require integrating many components, raising the requirement for large-scale integration. We develop a wafer-scale equal power splitting on the ${\rm Si_3N_4}$ platform to split the input optical power into a 2D 10$\times$10 array with a 1cm period in both directions using the layout shown in Fig. 9(a) at 1550nm wavelength and fundamental TE mode. The round contour shows a 6-inch silicon wafer. The light from an external laser is split and distributed into a 10$\times$10 array using cascaded 1$\times$10 EPSs, with the layout shown in Fig. 9(b). The ten outputs from a single EPS are routed as indicated by the port numbers in Fig. 9(a) and (d). We design a wafer-scale optical interposer by placing inversed tapers in Fig. 9(c) at the end of the distribution to support up to 100 dies. As a proof of concept demonstration, we design and fabricate a wafer-scale grating array by replacing the inversed taper with the grating in Fig. 9(c) to observe the light emission from the top.
Fig. 9. (a) Layout of a wafer-scale optical interposer using a path length matching and stitching design, blue boxes contain EPSs, and Orange boxes contain gratings or inversed tapers. (b) the layout of the EPS, and (c) the layout of gratings and an inversed taper. (d) Zoom-in view of the centered blue box in (a).
The EPS, with a 3D diagram shown in Fig. 10(a), split the input optical power evenly into ten output ports by varying the output aperture width on every port to control the proportion of the power captured by the output waveguide. We fabricate the EPS as shown in Fig. 10(b) and measure the insertion loss on every output port presented in Fig. 10(c). The measured results show a 0.46dB loss variation in the ten ports with a 1.56dB total excess loss. Besides, we use a path length matching design to ensure the propagation loss on every path is the same and also the coherency on every terminal.
Fig. 10. (a) 3D diagram of a 1$\times$10 EPS, (b) SEM picture of the EPS, and (c) simulated and measured EPS insertion loss at ten output ports.
We develop a wafer-scale fabrication technique by combining projection lithography and contact lithography. The contact lithography can expose an entire 6-inch wafer at one time of exposure but can only achieve a down to 1${\mu}$m minimum feature size. Our projection lithography gives a 250nm minimum feature size, but the exposure area is limited to 22mm$\times$22mm, using the ASML 5500/300 DUV stepper. In our fabrication process, we first pattern the routing waveguides and six alignment marks using contact lithography and etching while preserving the area for the devices with small (<1$\mu$m) feature sizes, such as EPS, inversed tapers, and gratings. Then, we use projection lithography to expose devices with small features guided by the alignment marks and butt connect the devices to the routing waveguides. The waveguide mismatch presented in Fig. 11(a) induces a waveguide mismatch loss with a simulated result shown in Fig. 11(c). We placed vernier rulers in the stitching area to check the mismatch, as shown in Fig. 9(d). Figure 11(b) shows an SEM picture of a vernier ruler, in which the projection lithography creates a pattern on the left side while the contact lithography creates another on the right side. The misalignment between the two times of lithography is mainly decided by the quality of the alignment marks, which can be less than 60nm if the alignment marks are ideal. We achieved 100nm misalignment by optimizing the contact lithography process, which induced around 0.075dB insertion loss at all the connections, guided by the simulated data.
Fig. 11. (a) Diagram of the waveguide stitching mismatch, (b) SEM picture of the stitched vernier ruler, and (c) simulated waveguide mismatch loss.
The gratings at the terminals have a 1.2$\mu$m period and a 50${\% }$ duty cycle using a fully etched process with almost 50${\% }$ of the optical power coming to the top. We use an IR camera on the top of the wafer to capture the emitting light from the gratings. Our gratings have an around ${9}^{\circ}$ emitting angle at 1550nm wavelength. Therefore, our camera cannot focus on all of the gratings simultaneously. Figure 12(a) shows the photo of all the gratings from an IR camera. We used a metal ruler to cover the scattering light from the fiber input since the scattering light is strong enough to damage the camera. It must be noted that all the outputs from gratings are out of focus and are not measured at the optimized angle, so the brightness of every grating depends on its output power and location. We can also observe a strong scattering light from the entire wafer. We measured every column of the gratings, as shown in Fig. 12(b). During measurement, gratings at the center are better focused and measured at a more optimized angle, so the gratings at the center are brighter than those at the edge. The measured results qualitatively show that our device distributes the optical signal to all the gratings on a wafer scale.
Fig. 12. (a) Measured wafer-scale grating array using an IR camera, we use a metal ruler to cover the reflection from the fiber input, and (b) measured ten columns of the grating array.
Figure 13(a) shows the SEM photo of the grating with clear structures patterned using projection lithography and etching. The 100nm thickness of the ${\rm Si_3N_4}$ platform maintains a weak emission, as shown in Fig. 13(b). We individually measured a 3$\times$4 array in the wafer-scale grating array using an infrared (IR) camera to further explore the performance of the power distribution. Figure 13(c) shows the photos of the 12 gratings. Both simulated and measured output beams of the gratings are long, so they cannot couple well to a single-mode fiber or a lensed fiber. We measured the output energy of the 12 gratings by integrating the intensity in a small region around the gratings, with measured normalized output energy shown in Fig. 14. We use the same color to show the output energy from one raw, where all the outputs are from the same EPSs. The calculated output energy shows a 0.85dB variation range, higher than our measured results from EPS. The integration method will also count the scattering light from the entire wafer. Therefore, the actual output energy variation will be higher than our measured results. The output variation comes from the following aspects: (1) imperfect EPS design and fabrication, (2) wafer-scale nonuniformity from deposition, lithography, and etching, (3) contamination during fabrication, (4) misalignment variance across the entire wafer, and (5) dust contamination during measurement.
Fig. 13. (a) SEM picture of the ${\rm Si_3N_4}$ grating, (b) simulated intensity profile of the grating, and (c) measured intensity profile of 12 gratings.
Fig. 14. Measured normalized output energy of the 12 gratings. The outputs from the same raw are shown with the same color. The measured output energy shows a 0.85dB variation.
6. Conclusion
We have experimentally demonstrated an optical interposer for multi-chip integration using thermal-compression flip-chip bonding. The interposer uses inter-chip couplers with a 0.77dB scattering loss, 0.54dB coupling loss, and $\pm$3.53$\mu$m 3-dB misalignment tolerance, so the total insertion loss is 1.31dB. The inter-chip coupler can achieve less than 1.75dB total insertion loss from 1200nm to 1600nm wavelength. We have designed and fabricated a wafer-scale equal optical power distribution for large-scale integration realized by a wafer-scale fabrication technique. The wafer-scale optical power distribution uses EPSs, a path length matching design, to achieve equal power splitting. We put gratings at the terminal of the distributions to observe the optical power from the top.
Funding
National Aeronautics and Space Administration (80NSSC20K0321, 80NSSC21K0617).
Acknowledgments
We acknowledge technical support from the staff members of UC Davis Center for Nano/Micro Manufacturing and UC Berkeley Marvell Nanofabrication Laboratory.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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