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Abstract
We report on LinoSPAD2, a single-photon camera system, comprising a 512×1 single-photon avalanche diode (SPAD) front-end and one or two FPGA-based back-ends. Digital signals generated by the SPADs are processed by the FPGA in real time, whereas the FPGA offers full reconfigurability at a very high level of granularity both in time and space domains. The LinoSPAD2 camera system can process 512 SPADs simultaneously through 256 channels, duplicated on each FPGA-based back-end, with a bank of 64 time-to-digital converters (TDCs) operating at 133 MSa/s, whereas each TDC has a time resolution of 20 ps (LSB). To the best of our knowledge, LinoSPAD2 is the first fully reconfigurable SPAD camera system of large format. The SPAD front-end features a pitch of 26.2 μm, a native fill factor of 25.1%, and a microlens array achieving 2.3× concentration factor. At room temperature, the median dark count rate (DCR) is 80 cps at 7 V excess bias, the peak photon detection probability (PDP) is 53% at 520 nm wavelength, and the single-photon timing resolution (SPTR) is 50 ps FWHM. The instrument response function (IRF) is around 100 ps FWHM at system level. The LinoSPAD2 camera system is suitable for numerous applications, including LiDAR imaging, heralded spectroscopy, compressive Raman sensing, and other computational imaging techniques.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
Single-photon avalanche diodes (SPADs), or Geiger-mode avalanche photodiodes (GM-APDs), are single-photon detectors capable of detecting single photon events and to generate a digital pulse with a certain probability, known as photon detection probability (PDP). Detected photons can be counted individually or associated with a time stamp characterizing their time-of-arrival with picosecond precision [1]. SPADs are suitable for fast gating, which is implemented as an electronic shutter with less than 100 ps raise and fall time and a width as low as a few hundred picoseconds [2].
Thanks to their CMOS compatibility [3], SPADs can be used in a variety of applications requiring time-resolved imaging [1,4], whereas a wide range of architectures has been explored, from single high-performance pixels to Megapixel imagers with gating and/or timing electronics at pixel or column level [5–13]. In SPADs, a p-n or n-p junction biased above breakdown, i.e. in Geiger mode, must be coupled to a quenching and recharge circuitry to avoid distruction of the junction upon triggering of an avalanche. The same circuitry is also used to detect avalanches triggered by photon detection and thermal events and to convert them onto a digital signal, which can then be routed to a logic function. One-dimensional or linear arrays of SPADs, such as the one presented in this paper, allow to optimize fill factor by pushing pixel circuitry to the periphery of the chip.
Both time-correlated and uncorrelated applications have been explored over the years. In time-uncorrelated applications, large-format SPAD arrays operating at over 100 kfps, with time-gating have been proposed, where the natively digital nature of SPAD-based pixels enables one to manipulate their digital output directly without going through and A/D converter. This, combined with a virtually noiseless read-out, is useful when applied to computational imaging, as it enables high-speed movement correction at a single-photon level in large scenes for image quality optimization [14]. In time-correlated applications, one exploits high intrinsic timing precision of SPADs, which is generally characterized as single-photon timing resolution (SPTR), for instance, to ascertain the time-of-flight on a pixel basis. Other important time-correlated applications exist based on individual SPADs and SPAD arrays, such as fluorescence lifetime imaging microscopy (FLIM), near-infrared optical tomography, non-line-of-sight imaging, ghost imaging, and quantum random number generation, just to name a few.
All these applications share a common need of fast data acquisition and high-performance processing. Some of the commonly used techniques are photon counting, histogramming, single-photon synchronous detection [15–17], which are generally integrated on chip along with the SPADs. Thus, only limited or partial programmability is possible. Examples include different histogram binning and on-chip data compression levels, often obtained by employing some degree of circuit sharing to minimize silicon real estate [8,10,11,16,18–22]. Programmability by means of digital processing units combined to a backside-illuminated SPAD array has been reported in [12], in-pixel reconfigurable logic in [23], and modular photon processors in [9,24], allowing to switch between intensity and time-resolved operating modes.
This paper details the architecture and performance of the LinoSPAD2 single-photon camera system. To the best of our knowledge, LinoSPAD2 is the first fully-reconfigurable photon-counting camera system, where the SPAD array is directly coupled to massively parallelized processing logic implemented in two field-programmable gate-arrays (FPGAs). Thanks to direct access to light information with the granularity of a single photon and picosecond timing resolution, LinoSPAD2 enables one to implement unprecedented functionality on a very large number of pixels in a fashion that is effectively free of read-out noise. As an example of the fully reconfigurable FPGA architecture, the end-user might need a coarser time resolution for the target application with a better non-linearity: in this case the TDC binning is performed directly on the FPGA while the timestamp histogram is building up, without burdening the end user with this task. This has been achieved without degradation of the native SPAD performance and mitigating the typical issues of high performance, fully integrated designs, such as additional design costs, extended fabrication cycles and operating complexity. The LinoSPAD concept originally launched in [25,26] has been totally redesigned and in this paper we outline the result taking advantage of a state-of-the-art SPAD technology and enhanced firmware to allow the exploration of new applications [27].
2. Image sensor architecture
LinoSPAD2 features a linear array of 512${\times }$1 SPAD pixels implemented in a 0.18 $\mu$m CMOS process. A micrograph of the IC is shown in Fig. 1. Each pixel includes a SPAD based on the p-i-n configuration described in [28], a dedicated passive quenching and recharge circuitry, and an inverter for digital signal forming and impedance adaptation. Quenching and recharge are performed by a 600-k$\Omega$ resistor, while AC-coupling through an n-well capacitor to a diode is done to limit the voltage on the digital logic when large excess bias voltages are used. A transistor controlled by $V_{ctrl}$ is used to leak a very small current from the limiting diode, so as to avoid capacitor potential buildup at the input of the inverter. Thanks to this solution, high excess bias voltage can be achieved to optimize PDP and SPTR. The pixel schematic is shown in Fig. 2, where $V_{op}$, $V_{diode}$, and $V_{ctrl}$ are used to bias and control the pixels and $V_{dd}$ to power the logic circuits. $V_{op} = V_{BD} + V_{EX}$ has to be adjusted, so as to achieve the intended excess bias voltage $V_{EX}$ for a given breakdown voltage $V_{BD}$, which varies as a function of temperature. The novel aspect of this front-end design is to enable high photon count rates at the SPAD output, since the AC coupling circuit makes the anode signal derivative, leading to spiking outputs detected by the inverter. Even if the SPAD anode RC constant is low, the detected photons can thus be recorded even in presence of high illumination levels. This scheme is described in Section 2.1.
Fig. 1. LinoSPAD2 IC micrograph detail. Microlenses are imprinted on top of the SPADs, with the alignment crosses drawn with the final metal layer on the array side (one cross is visible on the left).
Fig. 2. LinoSPAD2 pixel circuit with voltage waveforms highlighted, enabling individual SPAD readout and 1:1 coupling to external FPGAs. This configuration enables high excess bias voltages thanks to AC coupling to logic circuits and higher photon count rates. $V_{a}$ indicates the peak voltage of the inverter input, for which the maximum is set by $V_{diode}$.
The output of each pixel is connected to a dedicated digital I/O pad, thus enabling fully parallel readout of the SPADs. Control and power supply pads are placed every 20 signal I/O blocks to minimize IR drop, especially when high photon fluxes may induce a localized reduction of $V_{op}$ and thus of excess bias. A daughterboard PCB hosts the sensor, which is mounted in a chip-on-board configuration. A motherboard is connected to the daughterboard via high-density multipole connectors. The motherboard hosts a Spartan 6 XC6SLX150 Xilinx FPGA capable of supporting up to 150k logic elements packed in 20k slices and other discrete components for power management. FPGA programming and data transmission to a host PCB are enabled by a Cypress FX3 USB3.0 transceiver chip. Since a Spartan 6 has 498 available I/Os, a single motherboard is not sufficient to read out the whole SPAD array. Two motherboards are therefore connected in parallel to a single daughterboard. Each motherboard, capable of processing 256 pixels, is based on [29], whereas the firmware and software are new. The USB connection enables continuous streaming of 200 Mbps and up to 3 Gbps to the host PC.
2.1 High-voltage compact monostable front-end
The pixel front-end design has been redesigned with the purpose of allowing a high excess bias voltage to be applied on the SPAD device while achieving a high maximum photon count rate. Several solutions to sustain a high excess bias on the SPAD device have been presented in the literature, such as introducing cascode transistors between the SPAD anode and the quenching device [30–32]. However, the SPAD excess bias allowed on-chip is still limited due to the breakdown of the front-end MOS devices. The novel front-end design is shown in Fig. 2 together with the important waveforms occurring for two close photon events. With the proposed pixel scheme, the SPAD can reach higher excess biases, for which the authors tested values up to 8 V. The diode placed after the capacitor plate protects the inverter and M0 transistors from the anode voltage swing (0 to $V_{ex}$). Since the polysilicon resistor and the metal-on-metal (MoM) capacitor can sustain high voltages (up to tens of V) the pixel is able to reach a high excess bias. This is a key factor for applications in which the SPAD must have a high sensitivity. In addition to this feature, the MoM capacitor together with M0 are acting as a high-pass filter on the SPAD anode, which attenuates the low-frequency components of the voltage while reaching the inverter input. This transforms de facto the SPAD anode voltage into a high-frequency only spiking signal, modulated by the $V_{ctrl}$ voltage. With this scheme, even if the SPAD anode is recharging, as long as the SPAD is in breakdown regime it is able to detect another photon and the event is transmitted to the output.
We call this architecture a compact monostable circuit. The authors in [33,34] implemented an AC coupling in the SPAD front-end, but in a reversed pixel configuration and for another aim, i.e. to ensure DC compatibility of the capacitor output voltage with the digital CMOS logic implemented. In addition to that, the maximum applicable excess bias voltage was still limited by the anode swing, while in our scheme the diode limits this voltage, allowing a greater and configurable maximum anode voltage swing. Simulated values for this pixel reach up to 100 Mcps while the maximum measured countrate of the system is around 24 Mcps per SPAD, limited mainly by the FPGA readout, the PCB parasitic capacitance and the pixel direct readout to pad without further digital counting on-chip.
With these two novel features, i.e. very high SPAD excess bias voltages and high photon count rate detection, the LinoSPAD2 chip excels in applications where high sensitivity and/or high photon count rates are necessary.
2.2 System architecture
The LinoSPAD2 system is shown in Fig. 3. It features one or two custom-made motherboards and a daughterboard, which hosts the 512$\times$1 line sensor. Several read-out and processing topologies can be implemented in the FPGA and also modified in quasi real-time. They range from pixel-based digital counters to shared TDC arrays capable of on-the-fly histogram generation and calibration. Four representative examples are shown in Fig. 4, based on [26]. Fig. 4(a) illustrates the implementation of 256 parallel 32 bit counters, one for each SPAD output of a sensor half. Since not all applications do require picosecond timing resolution but rather high throughput, the TDC LSB can be increased or, in other words, bins can be merged to achieve nanosecond LSB. This operation, known as binning, has been achieved by operating the counters at 100 MHz, coupled to a double buffering memory scheme to avoid missing events, with integration times down to a few microseconds. If counting on a shorter timescale is required, gates can be implemented, as shown in Fig. 4(b), potentially employing multiple counters. The use of programmable delay elements within FPGAs makes it possible to instantiate gates with 100-ps precision.
Fig. 3. LinoSPAD2 system. One of the two custom-made motherboards, each of them hosting the FPGA, power management and host communication units dealing with one sensor half, is shown on the left, while the right part is the daughterboard on which the LinoSPAD2 integrated circuit itself is mounted.
Fig. 4. Representative architectures for the reconfigurable imaging sensor concept as demonstrated with the LinoSPAD2 system: (a) basic photon counting with per-pixel counters, (b) time-gated photon counting, implemented with several counters and a time gate that is shifted with 18-ps resolution, (c) time-correlated single-photon counting with a TDC shared among four pixels and raw TDC data read-out, and (d) TDC array as in (c) with additional on-the-fly histogram generation for reduced bandwidth and increased photon efficiency.
2.3 TDC architecture with smart multiplexing
Time-correlated single-photon counting (TCSPC) applications rely on TDCs built with the FPGA’s carry chains [35–39]. Other recent TDC techniques on FPGA involve the use of gray code oscillators with the aim of decreasing the amount of FPGA resources utilized, with the drawback of worsening the time resolution. The authors in [40] overcame the low resolution problem with a new matrix scheme achieving 20.97 ps TDC bin in a 16 nm Ultrascale+ FPGA device. The carry chain-based TDC or tapped-delay-line (TDL) has become common in fields sharing the need for high timing precision [36,41,42]. It relies on delay lines constructed from dedicated carry logic available in programmable logic elements, providing the fastest paths from one register input to the next, and thus the best timing resolution possible, at the same time minimizing non-linearities. The LinoSPAD2 delay line is sampled at the highest possible frequency in Spartan 6 FPGAs, 400 MHz, thereby minimizing its length and reducing timing degradation. We employ 35 carry elements with four outputs each, resulting in a total of 140 bit samples. This is sufficient to cover 2.5 ns of the clock period for all operating conditions, i.e. taking into account timing differences due to different locations in the FPGA, as well as variations due to operating temperature or voltage. A schematic of the TDC architecture is shown in Fig. 7 for clarity.
TDC arrays are available within the LinoSPAD2 system in several variants. Given that TDC blocks are relatively large, a single TDC per pixel is not feasible in a Spartan 6 FPGA. This leds to three main time-resolved implementations, with the basic one coupling 64 TDCs to 64 SPADs in a fixed topology. This is already sufficient for a number of use cases. In a second implementation (Fig. 4(c)), a single TDC is shared amongst four pixels and the raw timestamps are made directly available to the user. In this case the 64 TDCs can be dedicated to groups of 64 SPADs at any time, moving to the next group of 64 pixels in a round-robin fashion (sequential access), or serving all pixels simultaneously by means of smart 4:1 multiplexers (shared access). The latter is obviously more efficient but harder to implement, given that conflicts need to be avoided. The underlying principle and approach are shown in Fig. 5. The novel smart multiplexers are implemented in the LinoSPAD2 FPGA architecture as shown in Fig. 6. They have been placed-and-routed in close proximity with the FPGA TDLs with ad-hoc constraints. The pulses coming from 4 SPAD pixels are processed in parallel by a modified OR tree to retain the address of the SPAD which fired, and by an LUT programmed with the SPAD combinations for which the timestamp is valid. All the SPAD pulse processing is implemented in the same configurable logic block (CLB), together with the synchronizing flip flops, which are sampled by the fast 400 MHz clock. The output of these provides the SPAD codes together with the TDC valid bit which determines if the TDC code, sampled at the same clock edge, is recorded or discarded. Up to now we implemented only the condition for which we validate the timestamp if just a single SPAD fired during the clock period and we leave for future implementations the possibility of reprogramming this block to implement smart processing of the SPAD logic pulses, such as enabling different levels of coincidence. The overall final maximum TDC rate is 133 MHz, with a maximum range of 4.5 ms (28 bits) and an average LSB of 20 ps. In a typical configuration, the FPGA utilization levels of the logic, register and memory resources are of 71%, 43% and 94%, respectively.
Fig. 5. (Left) Pulse shrinking circuit schematic for a single pixel, tailored for implementation in an FPGA. Input pulses are shortened to 2.5-5.0 ns. (Right) Pulse shrinking circuit timing diagram. The shrunk pulses of four pixels are combined using an OR-gate to share the same delay line. This leads to higher event rates and lower pulse losses due to temporal overlap of the input signals.
Fig. 6. Smart multiplexing scheme implemented in a single FPGA CLB to allow concurrent operation of four different input SPADs while detecting possible timing conflicts. The delayline is triggered when one of the four inputs has a rising edge. The address of the input pulse is determined by the Address high/low signals and the timestamp is validated if TDC valid is asserted.
Fig. 7. Time-to-digital converter FPGA architecture illustrating one of the smart multiplexing-enabled TDCs. Only seven Carry4 configurable logic blocks (CLBs) are shown on the left side for simplicity, while in the real FPGA architecture the delayline is composed of 35 elements. The delayline input comes from the input CLB, shown at the bottom of the image, which hosts the smart multiplexing scheme detailed in Fig. 5 and Fig. 6. The carry chain outputs are converted to binary by means of a fast thermometer encoder in a pipelined fashion. The final timestamps are then resynchronized to a 133 MHz clock domain by means of a rate reducing block.
When individual timestamps are not needed, system efficiency can be further enhanced by adding an on-FPGA on-the-fly histogram generation engine as in Fig. 4(d), with a corresponding substantial read-out bandwidth reduction. Typical configurations are 1024 bins of 16 bits each or equivalent, limited by the available memory blocks.
3. System characterization
The sensor has been characterized over 256 pixels in terms of breakdown voltage, system SPTR, PDP, crosstalk and afterpulsing, and over 512 pixels in terms of dark count rate (DCR). The DCR measurements were performed by means of counters implemented on FPGA, while for the SPTR measurements the TDC array was employed.
3.1 Breakdown voltage
The SPAD breakdown voltage levels have been measured in the dark, counting the first DCR digital pulses produced by the pixels. To characterize the breakdown voltage in temperature, the IC was inserted in a temperature chamber with temperatures ranging from -65$^{\circ }$ to +60$^{\circ }$. For each temperature the SPAD voltage has been swept with a 0.05 V granularity from the expected breakdown voltage -0.5 V to +0.5 V and 10 measurements have been acquired for each voltage point. A linear fit has then been employed to determine the intercept with the voltage axis in the counts over SPAD voltage graph. The results of this characterization are shown in Fig. 8. A correction of 0.6 V has been applied, to take into account the inverter threshold voltage in the pixel.
Fig. 8. Mean SPAD breakdown voltage characterization over temperature; the error bars correspond to the standard deviation. Inset: breakdown voltage distribution over the array at 20$^{\circ }$C. For other temperatures the distribution was found to be similar around the mean breakdown voltage.
3.2 Dark count rate
After having determined the breakdown voltages across the array the DCR was measured. The system was enclosed in a black box during the measurements to remove all spurious light sources and to avoid that the sensor warms up during the integration time. An exposure time of 1 s was set and 10 acquisitions were performed per excess bias voltage, and then averaged. The resulting cumulative DCR distribution over the full array is shown in Fig. 9 at room temperature and for different excess bias voltages, for a representative sensor. In Fig. 9 the median DCR of the same pixel array is plotted from 1 to 7 V of excess bias voltage at 20$^o$C. Results for these SPADs are in agreement with previously reported SPADs in this technology [28,30].
Fig. 9. (Left) Cumulative DCR distribution over the full array for different excess bias voltages, measured at 20$^o$C. A number of pixels, corresponding to the missing parts of the plots on the left, were inactive due to electrical contact issues. (Right) Median DCR over the full array as a function of the excess bias voltage, measured at room temperature.
3.3 Sensitivity
The PDP has been characterized between 320 nm and 960 nm at different excess bias voltages with the optical set-up detailed in [31,43]. A wide spectrum Xenon lamp was employed as a light source and fed to a monochromator and then to an integrating sphere. A reference photodiode (Hamamatsu S2281) was used for the intensity calibration. After calibration, the LinoSPAD2 chip was placed in the setup, at distance of about 14 cm from the output port, and characterized. Sufficiently low light levels over the sensor were employed to avoid pile-up effects, which could potentially alter the SPAD photo-sensitivity curve. Before scanning the wavelengths, a DCR measurement was performed at a specific excess bias and then subtracted. In Fig. 10 the PDP as a function of wavelength is shown for different excess bias voltages. To improve the sensor light detection efficiency, microlenses have been designed and imprinted on the sensor [44]. Fig. 11 shows a comparison between the PDE with and without microlenses and a plot of the concentration factor (CF) with respect to wavelength. This parameter is measured as the ratio of the count rates with microlenses and without and it determines the ability of the lenses to focus light onto the SPAD photosensitive area.
Fig. 10. Detector PDP as a function of the excess bias voltage and wavelength (mean values over the pixel array). The peak PDP is at 520 nm with a value of 53 % @ $V_{ex}$ = 5 V.
Fig. 11. (Left) Mean photon detection efficiency at $V_{EX}$ = 5 V and $V_{diode}$ = 1.4 V with and without microlenses (left) and corresponding concentration factors (right). Error bars correspond to the standard deviation of the measurements. The transmission reduction in the NUV, below 400 nm, is caused by the microlens material. Reprinted with permission from [45] © The Optical Society. (Right) Photo-response non uniformity (PRNU) over the SPAD array at 520 nm and $V_{EX}$ = 5 V. Left: PDE, right: corresponding CF. The linear fit coefficients are indicated in the plot, together with the $R^2$ parameter to indicate fit quality. The upper red plot was measured for a sensor with microlenses, while the lower one for a sensor without. Reprinted with permission from [45] © The Optical Society.
Fig. 11 shows the average CF over all pixels, computed for every wavelength. Applying different excess bias voltages does not influence the mean CF value of 2.3, which is slightly below the simulated value of 2.9 for NA $\approx$ 0.177 [45]. This is likely due to manufacturing imperfections in the microlens shape and/or microlens-to-pixel misalignment errors. The pixel-to-pixel variation shown in Fig. 11, measured at a fixed wavelength close to the PDP peak, features a small gradient and a relative PDE change of 4.0% peak-to-peak between the two sides of the array, according to a linear fit. This applies to both arrays shown, i.e. one with microlenses (top) and one without (bottom). Finally in Fig. 12 the full uniformity data over the array at 5 V excess bias is reported at a fixed excess bias voltage.
Fig. 12. PDP as a function of wavelength and pixel number, at $V_{EX}$ = 5 V and $V_{diode}$ = 1.4 V.
3.4 Afterpulsing
Afterpulsing has been characterized for different pixels in the array, soldering short wires directly onto the daughterboard PCB and analyzing the pixel traces by means of a fast oscilloscope (LeCroy WaveMaster 813 Zi-B) using active probes. The histogram of the inter-arrival times for a reference pixel is shown in Fig. 13. A dead time of 18 ns was observed in the trace, which is in agreement with the value of the $\mathrm {RC}$ constant of the pixel passive quenching/recharge circuit of 12.6 ns according to our design, see Fig. 2. However no double exponential behavior has been observed, and therefore no afterpulsing value is reported. This is due to the passive recharge mechanism employed for this pixel. As observed in [46], afterpulsing in this type of SPAD is not zero, however it cannot be observed with an experimental setup characterized by relatively large parasitic capacitance in parallel to the SPAD.
3.5 TDC characterization
The TDC non-linearity characterization was performed by exposing the sensor to uncorrelated light distributed uniformly over the 400 MHz sampling clock period in the so-called code density test. Fig. 14 shows the results of the test; a point of measure indicates the recorded bin size in ps for each of the 1024 bins in the TDC. A mean LSB of 18 ps with a standard deviation of 13 ps was measured in any given delay line with respect to a reference. An on-FPGA calibration step is used to compensate for the variability of all the bin sizes, thereby reducing differential and integral non-linearity. The non-linearity correction scheme consists in a histogram count redistribution (bottom part of Fig. 14) by means of a matrix multiplication. The uncalibrated histogram is multiplied by a matrix of weights computed from the code density test results. The counts are redistributed in such a way that the equivalent size of the new calibrated TDC bins after correction is:
where $\mathrm {B}_{cal}$ is the width of the new TDC bins (22.9 ps in our case), $\mathrm {T}_{TDC}$ is the TDC period (20 ns) and $N_{bin,cal}$ is the new total number of bins (800). In our case $\mathrm {N}_{bin,cal}$, i.e. after calibration, is smaller than its counterpart before calibration due to the elimination of empty bins while maintaining the same TDC range. The timing skew is then compensated in the firmware by using a correlated light source, whereby the FPGA is programmed with a peak-finding algorithm to determine the fixed time difference between each channel. This allows to time-align all channels, as will also be apparent in the IRF curves shown in Section G. The overall skew magnitude range is of $\pm$8 ns.Fig. 14. Time-to-digital converter bin sizes over a reference TDC delay line on the FPGA, obtained by means of a code density test. The top figure shows the raw uncalibrated TDC bins, while the bottom graph shows the bin sizes after non-linearity correction implemented directly on the FPGA.
3.6 Crosstalk
The overall system crosstalk was characterized using the TDCs on the FPGA, following the methodology detailed in [47]. After the non-linearity calibration and an offline skew correction, the sensor was illuminated with light from a halogen lamp, attenuated by means of ND filters and a diffuser, in order to achieve a uniform illumination over the SPAD array, with an excess bias voltage of 6 V. We then analyzed the raw timestamps for pixel pairs, one "aggressor" and one "victim", by counting the number of events detected by the victim inside a 500 ps time window after the aggressor event. We then subtracted from this value the mean number of crosstalk events at larger timescales (multiple victim events are compared and histogrammed in a time window $\approx 100$ ns, taken after $5$ ns wrt the aggressor event), which are uniformly distributed. The result was divided by the total number of events recorded by the two selected pixels over the 48.4 seconds acquisition time. Fig. 15 reports the crosstalk probability map for 16 adjacent pixels (corresponding to 16 TDC channels in the FPGA). The highest pixel crosstalk level which we observed was $\approx 0.19 {\% }$, which is consistent with other measurements in the same technology and for similar SPAD sizes.
Fig. 15. Crosstalk probability matrix at 6 V excess bias over a section of the LinoSPAD2 array. Inset: example of crosstalk probability for five pixels adjacent to pixel 3.
3.7 System Instrument response function
The system SPTR has been characterized employing a femtosecond pulsed laser (NKT photonics ORIGAMI O-08LP) with a typical pulse duration $\leq$160 fs and a center-wavelength of 780 nm. The laser has been synchronized with the LinoSPAD2 board using a high bandwidth RF cable and the laser light power has been attenuated using neutral density filters before illuminating the SPAD array using a diffuser. Neutral density filters ensure that the array is operating in photon-starved mode, so as to avoid pile-up. The TDCs on the FPGA were used for these measurements, and their raw timestamps calibrated as previously described. A Gaussian fit around the peak (+-$\sigma _e$ bins) was applied to the data to extract the FWHM values of all the pixels. A value of $\sigma _e = 10$ was chosen to take into account only the laser peak for the calculation. In Fig. 16 three histograms of the jitter FWHM values are shown over the array for three different excess bias voltages. As expected, the timing performance improves with increased excess bias, in accordance with standard SPAD theory and practice. In addition to the FWHM distribution over the array, the normalized, calibrated IRFs of selected pixels (251 out of 256) are also shown in Fig. 16.
Fig. 16. Normalized IRF curves for multiple SPAD pixels as acquired by the TDCs on FPGA, after correction for non-linearities and skews between the pixels. Inset: FWHM distribution over the array.
3.8 System power consumption
The overall system power consumption has been characterized for different modes of operation, corresponding to representative light levels. The results are shown in Table 1 for some key voltage supplies (see also Fig. 2 and Fig. 3). The main power consumption source is the 5V plug powering the FPGA, the voltage regulators, the flash memory and the USB communication interface. When the light power onto the SPAD active area increases, the higher activity impacts the I/O blocks of the chip as well as the FPGA inputs, which draw more current.
Table 1. System power consumption for different illumination scenarios without optics on the sensor.
4. LinoSPAD2 time-resolved applications
The versatility of the LinoSPAD2 camera system is illustrated in several time-resolved applications, whether operated in a synchronous or asynchronous manner. Table 2 lists all those applications for which the LinoSPAD concept was used, to date, along with core firmware requirements. The first five are specific to LinoSPAD2 and rely in one way or another on its hardware and/or firmware key features (high sensitivity combined with parallel, virtually noiseless read-out), to improve the acquisition speed and/or the signal quality. The applications are diverse in complexity, from compressive Raman, where high-speed counting over all pixels and low DCR are needed, to heralded spectroscopy, where a selected pixel range can be addressed and a fixed TDC topology is acceptable. In other applications, such as quantum random number generators, pixels must be truly independent and as many as possible are needed to increase throughput. Conversely, in quantum astrometry/spectroscopy, there is a need to detect correlations between distant pixels, and shared TDC access is necessary. In this case the smart multiplexing scheme is a key feature enabling the direct measurement of time and energy (i.e., wavelength or frequency) over the full sensor, in a spectrometer set-up, for simultaneous single photons, thereby combining excellent temporal and spectral resolution. Indeed, without smart multiplexing only a portion of the array would be usable for this application. Initial results have already been reported at only a factor of ten above the Heisenberg Uncertainty Principle limit of $\hbar$/2 for energy and time [48]. In addition, having a $\approx$30% peak PDE, which is also one of the highest reported for linear SPAD arrays, decreases by almost five times the integration time (compared to the original LinoSPAD) given that the probability of coincidence events is proportional to the square of the PDE.
Table 2. LinoSPAD2 (*) or LinoSPAD (**) reconfigurable cameras reference applications, together with specific firmware requirements. Reference columns: further information on the application and (when available) specific results obtained so far. N/A: not yet available or work in progress. NLOS: non-line-of-sight imaging, QRNG: Quantum Random Number Generation.
The last argument applies as well to other applications where detection in coincidence plays a prominent role, such as room temperature single-particle heralded spectroscopy of quantum dots and lead halide perovskite nanocrystals [49,50]. In this case, LinoSPAD2 made it possible to extend the temporal resolution limit of standard spectrometers by several orders of magnitude. Furthermore, the combination of low DCR and high PDE enabled compressive Raman sensing [51,52] at a very short effective pixel dwell time of 800 ns, which would be hardly feasible in presence of high DCR as the weak spontaneous Raman signal would be buried by noise. This achievement enabled an effective parallelization of single-pixel compressive Raman and represented an important step towards high-speed chemical imaging. Finally, in all cases low crosstalk is appreciated to reduce spurious events and coincidences, in heralded spectroscopy in particular, and in quantum imaging in general.
Up to now we did focus on fixed firmware functionality, designed for the target application; however, FPGAs can be reconfigured dynamically at run-time if need be. For instance, an increase of processing power for selected tasks may be needed and several firmware IP blocks could be added for further enhancements, typically implementing real-time post-processing steps. Examples include time-of-arrival estimation, peak intensity extraction, lifetime estimation in FLIM, or autocorrelator arrays for diffusion estimation [53] or $g_2$ calculations [54]. Additional performance achievements are expected by moving to more advanced FPGA platforms, although the existing platform has proven to be sufficient for most applications. Two main boards are in principle needed to address the full sensor. However, user feedback has shown that in a number of cases a restricted amount of pixels is perfectly sufficient. If so, they can selected amongst those featuring the least high-DCR pixels.
5. Conclusions
LinoSPAD2 is a time-resolved camera featuring 512 SPADs arranged in a linear configuration and connected directly, in a fully parallel manner, to an FPGA. This solution enables a reconfigurable and highly customizable camera for a variety of very diverse applications. The pixel pitch is 26.2 $\mu$m, while the SPADs have a median DCR of 80 cps, a peak PDP of 53%, an intrinsic SPTR of 50 ps FWHM, and an average IRF at system level of 106.3 ps at 5 V excess bias. The LinoSPAD concept has been totally redesigned: the sensor itself is twice as long as the original one, the PDP has improved by more than 60%, also thanks to the novel high-voltage compact monostable front-end, the PDE has been multiplied by $\approx$ 2.3 times by means of custom imprinted microlenses, and the median DCR reduced by at least 50 times. This has been coupled to enhanced firmware and software, in particular the smart multiplexing option, to allow the exploration of new applications. Serving all pixels simultaneously was for example simply not possible before. Key results are reported in Table 3 and compared with literature.
Table 3. State-of-the-art comparison of large line format CMOS SPAD sensors with either on-chip or FPGA-based data acquisition and processing.
LinoSPAD2 is a hardware-reconfigurable imager featuring high-sensitivity and natively digital single-photon detection in standard CMOS. This allows to process photons a few nanoseconds after detection with possibly complex processing done practically in situ. This firmware- and software-defined camera system is a new paradigm in image sensors, enabled by the speed and digital nature of SPADs. It will support future single-photon-aware and quantum imaging and new emerging applications.
Funding
Schweizerischer Nationalfonds zur Förderung der Wissenschaftlichen Forschung (20QT21-187716; 200021-166289).
Acknowledgments
The authors would like to acknowledge Francesco Gramuglia for the fruitful technical discussions about the PDP setup and the femtosecond laser setup, Mathieu Moulin (EPFL) for system testing, Gur Lubin, Ron Tenne and Dan Oron (Weizmann Institute of Science), Sergei Kulkov and Jakub Jirsa (Czech Technical University, Prague), as well as Andrei Nomerotski (Brookhaven National Laboratory), for characterization assistance.
Disclosures
CB: PI Imaging Technology SA (I,S), EC: Fastree3D SA (I,S) and PI Imaging Technology SA (I,S).
Data availability
Data may be obtained from the authors upon reasonable request.
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