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Abstract
The escalating need for expansive data bandwidth, and the resulting capacity constraints of the single mode fiber (SMF) have positioned the 2-μm waveband as a prospective window for emerging applications in optical communication. This has initiated an ecosystem of silicon photonic components in the region driven by CMOS compatibility, low cost, high efficiency and potential for large-scale integration. In this study, we demonstrate a plasma dispersive 4 × 4 photonic switch operating at the 2-μm waveband with the highest switching speed. The demonstrated switch operates across a 45-nm bandwidth, with 10-90% rise and 90-10% fall time of 1.78 ns and 3.02 ns respectively. In a 4 × 4 implementation, crosstalk below -15 dB and power consumption lower than 19.15 mW across all 16 optical paths are indicated. This result brings high-speed optical switching to the portfolio of devices at the promising waveband.
© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
With the spread of big data and 5 G networks, optical communication systems are evolving to accommodate the expanding volume of information that needs to be transmitted over point-to-point or meshed networks [1–4]. Currently, the most commonly used wavelength for optical communication is at the C-band [5,6]. However, there exists a theoretical maximum transmission capacity due to the Shannon limit [7,8]. To address the anticipated increase in capacity requirements, one promising approach is to initiate the development of a new waveband infrastructure. Regarding the abovementioned topics, the 2 μm waveband shows significant promise with the development of the low-loss hollow core photonic bandgap fiber (HC-PBGF) [9,10] and the thulium-doped fiber amplifier (TDFA) [11,12], which are critical components of a communication system [13,14]. HC-PBGF is an interesting media for optical transmission at 2 μm, indicating low optical nonlinearity, latency, transmission loss and high-power handling capabilities. TDFA, on the other hand, enables high small-signal gain and low noise figures. Due to the CMOS-compatibility of silicon photonics, the platform is commensurate with large-scale and low-cost manufacturing [15–18]. Over the years, substantial efforts have been dedicated to the development of integrated silicon photonic circuits operating at the 2 μm waveband. As a result, a comprehensive array of essential building blocks has been demonstrated, including both passive components like waveguides [19,20], grating couplers [21,22], micro-ring resonators [23,24], and multimode interferometers [25,26], as well as active components like lasers [27,28], photodetectors [29,30], and modulators [31,32]. These advancements underscore the potential of silicon photonics at the 2 μm waveband as a new and prospective window for future development and applications, including optical communications [33], and while not limiting, biomedical monitoring [34], and sensing [35,36].
Among these key silicon photonics components, high-speed optical switches routing with low power consumption are crucial in optical communication [37], optical interconnection [38], and high-performance optical computing [39]. Current integrated photonic switches are based on microelectromechanical (MEMs) actuation [40], microring resonators (MRRs) [41] and Mach-Zehnder interferometers (MZIs) [42,43]. MZI-based photonic switches enable broader operating wavelength range compared to MRR-based switches, while indicating lower operating voltages and simpler fabrication process flows than MEMs-based photonic switches [44]. Photonic switching is enabled by the phase modulation of lightwaves, through effective refractive index manipulation in the waveguide arms. This modulation can be induced by the thermo-optic (TO) effect, where the phase shifter area is heated, or by the plasma dispersive effect, where free-carrier injection from PN/PIN junctions occurs upon the application of forward bias voltage to the device. Generally, TO switches offer simpler fabricating process [45,46], while plasma dispersive switches utilizing carrier injection, can achieve switching speeds in the nanosecond-scale: ∼1000 times faster than TO switches [44]. Furthermore, the thermal crosstalk inherent in TO switches precludes high integration densities.
In the era of cloud computing, the Internet of Things (IoT), and artificial intelligence (AI), high-speed plasma dispersive switches are critical for efficiently managing a substantial volume of random data and responding to exploratory requests in real time, thereby enabling the ultra-fast switching of frequent short messages. Therefore, plasma dispersive switches become particularly crucial, and are applicable to vast amounts of applications, including packet-switched multi-plane/multi-path wavelength division multiplexing (WDM) networks [47], low-latency interconnect between microprocessors [44,48], and high-throughput data center network (DCN) [49], where ultrafast switching speed on the order of nanoseconds or less is favored. We note that the development of optical switches, specifically high-speed switch, at 2 μm have been lacking [50–55], while our group have reported a 1 × 8 optical switch [52]. Given the escalating demand for higher capacity and progressive trend towards photonics circuits at 2 μm [56], the development of high-speed switches becomes increasingly necessary and crucial.
In this work, we report a 4 × 4 silicon photonic plasma dispersive switch operating at the 2-μm waveband based on the Mach-Zehnder interferometer (MZI) structure. Firstly, a 2 × 2 elementary cell is characterized. The power consumption for π-phase-shift (Pπ) is measured to be 6.12 mW, extinction ratio (ER) higher than 16 dB and crosstalk (CT) lower than -16 dB are demonstrated across the 45-nm wavelength range (1968 - 2013nm), considering both input ports. Subsequently, the elementary cell is scaled to a 4 × 4 optical switch by a waveguide crossing. Crosstalk of lower than -15 dB, with a minimum of -23 dB is characterized. Furthermore, dynamic characteristics of the 2 × 2 elementary photonic switch are investigated, with 10-90% rise and fall time of 1.78 ns and 3.02 ns respectively. To the best of our knowledge, this is the highest switching speed in this waveband.
2. Device design
2.1 Design and fabrication process overview
The schematic diagrams and micrograph images of the photonic switches discussed in this work are shown in Fig. 1. As indicated in Fig. 1(a), the 2 × 2 elementary photonic switch comprises of two 270 μm-long PIN-junction phase shifters, connected on both ends by two 3-dB 2 × 2 MMI couplers. MMIs are utilized in view of its tolerance to fabrication errors, low-loss and compact size [57]. PIN-junction phase shifters are implemented on both arms of the elementary cell for switching (switching arm), as well as optical phase compensation due to errors in fabrication (phase compensation arm). Phase compensation is particularly necessary since silicon photonics is a high index contrast platform that is prone to fabrication-induced phase errors from nanometer-scale dimensional variations [58–61]. This part will be discussed later in section 2.3. We define VP and VS as the applied voltages on the phase compensation arm and switching arm, respectively. The micrograph image of the 2 × 2 elementary cell is shown in Fig. 1(b), with labels of all components shown in the schematic diagram, as well as the metal pads for VS, VP and ground connection (GND). Through the application of the appropriate forward bias on the PIN-junction, an optical phase difference is implemented between the Mach-Zehnder arms, resulting in the photonic switching between the two output ports (O1, O2), in regard to one of the two input ports (I1, I2). For the 2 × 2 elementary photonic switch (Fig. 1(a)), the terms “bar” and “cross” refer to the status where the lightwave is transmitted from I1 (I2) to O1 (O2), and from I1 (I2) to O2 (O1), respectively.
Fig. 1. (a) Schematic illustration of the 2 × 2 elementary photonic switch; the definition of “bar” and “cross” status is illustrated for I1 input with the switching and phase compensation arm. (b) Micrograph image of the 2 × 2 elementary photonic switch, with scale bar indicated. The switching arm and phase compensation arm are indicated, with VS and VP representing the applied voltages on them. Metal pads for applying VS, VP, and ground (GND) are labeled. The inset shows the enlarged image of MMIs. (c) Schematic illustration of the 4 × 4 photonic switch. M1, M2, M3, and M4 represent each elementary switch cell. C1, C2, C3, and C4 represent four ports of the waveguide crossing. (d) Micrograph image of the 4 × 4 photonic switch, with scale bar indicated. Numbers 1 - 9 represent the metal pads used in the 4 × 4 photonic switch, and their functions are summarized in Table 1. The inset shows the enlarged image of the waveguide crossing.
Table 1. Metal pads for different voltages applied to the 4 × 4 photonic switch
Subsequently, a 4 × 4 photonic switch is demonstrated, enabling routing of any input port (I1, I2, I3, I4) to any output port (O1, O2, O3, O4). This necessities four 2 × 2 elementary switches (M1, M2, M3, M4) and a waveguide crossing interconnected in the architecture illustrated in Fig. 1(c); the micrograph image of the 4 × 4 photonic switch is shown in Fig. 1(d), with labels of the crossing, individual elementary switches, and I/O ports. The metal pads applied in the 4 × 4 photonic switch are numbered 1 - 9 in Fig. 1(d), with their functions detailed in Table 1. Based on the prior illustration, it is evident that 2 × 2 MMIs, high-speed PIN-junction phase shifters, and waveguide crossings, all optimized at 2 μm with good performance, are the key building blocks for scaling photonic switches at the novel waveband. In the following sections, the design of the 2 × 2 MMI, PIN-junction phase shifter and waveguide crossing will be presented.
The device presented in this work is fabricated by the wafer-level platform developed by Sia et al. [62], where detailed fabrication process flow is elucidated. The process starts with a 200 mm SOITEC 220 nm silicon-on-insulator wafer. Waveguide patterning for 130 and 220 nm etch are enabled via the 193 nm Argon Fluoride (ArF) immersion lithography and optical proximity correction. The lithography technology has a minimum single-exposure size of 40 nm, but is limited by the resolution of the hardmask. All the waveguide layers of the device are fabricated on the single crystal, 220 nm-thick silicon. The buried oxide below the 220 nm-thick silicon is 3 μm-thick to prevent leakage of the optical mode into the silicon substrate. The 130 nm partial etch and 220 nm full etch are implemented for the formation of the PIN junction phase shifters and strip waveguides respectively. The waveguide layers are defined via inductively coupled plasma reactive ion etching (ICP-RIE) process. Ion implantation steps are implemented prior to and after the definition of the waveguides, where the metal contact areas are heavily doped (ohmic) to reduce contact resistance. Rapid thermal annealing is utilized for carrier activation. Upon the silicidation of the silicon, a back-end-of-line process is used to contact the silicide, one via layer between two metal layers. Lastly, passivation is carried out and the contact pads are formed.
2.2 2 × 2 MMI design
The 2 × 2 MMI illustrated in Fig. 2(a), operates via the self-imaging theory [63], with device dimensions and input/output ports labeled, is designed using the 3-D Eigenmode expansion (EME) method with metal simulation boundaries to prevent unphysical modes. The selected MMI width is 6 μm, sufficiently wide for self-imaging to be facilitated within the multi-mode MMI region. The width of MMI input and output waveguides are tapered from 1.1 µm (WT) to 0.6 µm (W) over a length of 10 µm (LT) for low-loss adiabatic transition to a fundamental TE waveguide. The output spacing of the MMI is determined through the imaged output from the input, via the top-down electric field distribution of the designed MMI coupler. Due to device symmetry of the designed MMI, the operating characteristics remains the same when the input is at port 1 or 2. In order to obtain the optimal MMI core length, light was input into port 1, and the fundamental TE transmission using mode expansion monitors at port 3 (T13) and 4 (T14) as a function of MMI core length is indicated in Fig. 2(b); the ripples seen in Fig. 2(b) can be attributed to residual reflections at the simulation boundaries. When the length of the MMI coupler is 30.65 μm, T13 = T14, and the insertion loss of the MMI (T13 + T14) reaches a minimum. The insertion loss of the MMI is shown in Fig. 2(c) with legend “Total”, with a minimum insertion loss of 0.57 dB across the simulated wavelength region; the wavelength dependance from T13 and T14 also indicated. The top-down electric field distribution of the MMI is shown in Fig. 2(d), where efficient 3-dB splitting is indicated.
Fig. 2. (a) Schematic diagram of the 2 × 2 MMI, with device dimension and ports labeled. (b) Transmission from port 1 to port 3 (T13) and port 4 (T14), and the total transmission (T13 + T14) as a function of 2 × 2 MMI core length. (c) Insertion loss and the wavelength dependance for T13 and T14 of the designed 2 × 2 MMI with core length of 30.65 μm. (d) Top-down electric field distribution of the optimized 2 × 2 MMI with core length of 30.65 μm.
2.3 PIN junction phase shifter design
Rib waveguides with 130 nm etch, are implemented for this work [62]. Finite difference eigenmode (FDE) simulations are performed as a function of waveguide width to derive the single mode condition at 2 µm (Fig. 3(a)). Only the fundamental TE mode is supported when the width of the waveguide is smaller than 660 nm. As a result, the waveguide width was set to be 600 nm. The MZI structure includes two symmetric rib waveguide arms for the implementation of a phase shifter, with a PIN junction implemented on both arms via a 270-μm-long active PIN diode in consideration of switching (switching arm, Fig. 1(a)-(b)) and fabrication-induced phase error correction (phase compensation arm, Fig. 1(a)-(b)). The cross-section of the PIN junction is shown in Fig. 3(b). P++ (red) and N++ (green) regions are heavily doped to form ohmic contact with low contact resistance, positioned 1 μm away from the rib edge to minimize the free-carrier absorption loss. The electric field distribution of the optical mode is indicated at the inset of Fig. 3(b). Figure 3(c) shows the carrier distribution at varying driving voltages. As the voltage increases, the concentration of carriers across the PIN section increases, leading to a change in the silicon material refractive index change, expressed as [64]
Fig. 3. (a) Single-mode condition of the strip waveguide at 2 µm wavelength range, subject to rib width. (b) The schematic diagram of the cross-section of the slab waveguide; the red, green, and blue indicates the P++, N++ and intrinsic regions respectively. The inset shows the electric field distribution of the fundamental optical mode. (c) Hole concentration distribution at varying driving voltage in the PIN junction region. (d) Effective refractive index of the PIN rib waveguide as a function of the driving voltage.
With regards to the elementary cell (Fig. 1(a)), a lightwave propagates to one of the input 2 × 2 MMI coupler and is split equally into the two arms. Through the application of a bias voltage to the MZI arms, free carriers are injected and the silicon material refractive index Δn changes as indicated by Eq. (1), resulting in the effective refractive index changes of the propagating mode Δneff. A phase differential Δϕ will be implemented across the MZI arms as indicated by Eq. (2). Subsequently, the lightwave from the two arms interferes at the output MMI forming an interferometric spectrum. The lightwave can be output from either two of the output port, subject to the phase differential applied across both arms.
The abovementioned switching process is under an ideal scenario, which means there’s no phase differential between the two MZI arms. However, this hard to realize due to the sensitivity at the nanometre scale variations of silicon photonics platform [62]. To realize optical switching function and address potential phase differential induced by fabrication errors in the MZI arms, PIN-junction phase shifters are implemented on both arms, with one arm for optical switching and the other for phase compensation, as shown previously in Fig. 1(a)-(b). Voltage is applied to specific 80 × 80 μm2 metal pads on the photonic chip via a multi-contact DC probe. These pads are separated 20 μm away from one another, matching the spacing of the probe pins. The pads for phase compensation voltage (VP), switching voltage (VS), and ground (GND) are labeled in Fig. 1(b). In reference to the 2 × 2 elementary cell (Fig. 1(a)-(b)), the strategy for phase compensation involves the application of a voltage to one arm (phase compensation arm) such that the optical power at one of output ports is maximized, indicating an initial “bar” or “cross” state. The determination of which initial state to achieve is primarily considered upon the specific values of VP in each scenario, since a lower VP is favored to achieve better optical switching performance and avoid significant output power drop caused by free-carrier absorption (FCA) effect [65–67]. In our practical experiments, we found that a lower VP was required to achieve an initial “cross” state. Therefore, an initial “cross” state was achieved for the subsequent device characterizations. To be specific, when light is input from port I1 in Fig. 1(a)-(b), the output optical power at port O2 is maximized via the application of voltage VP on one arm (phase compensation arm). Similarly, when light is input from port I2, the output optical power at port O1 is maximized. Following the phase compensation process, a forward voltage VS is then applied to the other arm (switching arm). When this voltage induces a π-phase-shift on this arm, light will be redirected to the other output port and thus realize optical switching between the two output ports.
2.4 Waveguide crossing design
The 4 × 4 photonic switch design (shown in Fig. 1(c)-(d)) is derived from the elementary switch cell structure by connecting four 2 × 2 elementary photonic switch cells through a waveguide crossing. The waveguide crossing is designed with the inverse design toolkit by Lumerical [68] where the component comprises of two orthogonal multi-mode sections with L1 = 18.4 μm, taper length L2 = 5 μm and width W1 = 3 μm, contributing to a total footprint of 28.4 × 28.4 μm2, as shown in Fig. 4(a) with the four ports. Within the multi-mode section, along the direction of propagation of the input lightwave, multiple modes interfere constructively and destructively, creating an interference pattern. The multi-mode section is designed such that the input fundamental TE is recreated at the output of the output, as shown by the top-down electric field distribution in Fig. 4(b), computed via 3D FDTD [69]. In addition, the insets of Fig. 4(b) show the cross-sectional electric field distribution at the input and output waveguide respectively, indicating a fundamental TE mode which verifies the good waveguide crossing design.
Fig. 4. (a) Schematic diagram and (b) top-down electric-field distribution of the waveguide crossing, with X-Y coordinates and labels of the four ports. Insets show the electric field of the input and output mode at C2 and C4, respectively.
The performance of a waveguide crossing can be quantified by its insertion loss and crosstalk. First of all, optical power at the four indicated ports C1, C2, C3, and C4 in Fig. 4(a) is defined as PC1, PC2, PC3, and PC4, respectively. The insertion loss of a waveguide crossing (ILCrossing) can be specified as the optical power loss incurred at the output, relative to the input (i.e., insertion loss at C4 (C3) output port relative to C2 (C1) input port) [70]. For example, when the light is input from port C2, the insertion loss of output port C4 can be defined as ILCrossing = 10log10(PC4/ PC2). The crosstalk of a waveguide crossing (CTCrossing) is defined by the ratio of the optical power at the orthogonal port of the crossing waveguide relative to the output [71]. For instance, when the light is input from port C2, the light is supposed to be transmitted to the output port C4, and the crosstalk between C3 and C4 can be defined as CTCrossing = 10log10(PC3/ PC4). The simulated insertion loss and crosstalk is lower than 0.05 and -45 dB, respectively.
3. 2 × 2 elementary photonic switch characteristics
3.1 Static characteristics
The experiment setup for evaluating static characteristics of the 2 × 2 elementary photonic switch is illustrated in Fig. 5. A wavelength (λ = 1990nm) was input from a 2 μm tunable laser source (TLS) and subsequently amplified using a high-power TDFA, connected with a fiber polarization controller (FPC). Then the light was coupled in and out the switch device via edge coupling, facilitated by the lensed fiber and silicon inverse tapers (tip cross-section: 0.20 × 0.22 μm2, length = 200 μm). The fiber coupling loss of -6.7 dB/facet was measured from a reference waveguide on the same chip. The output was subsequently directed towards a photodetector (PD). The device was subjected to the voltage applied via DC probes.
Figure 6 presents the measured IV curve of the fabricated PIN junction, with the turn-on voltage approximating 0.8 V. Figure 7(a)-(f) present the static characteristics of the 2 × 2 elementary photonic switch cell, with input/output ports indicated in Fig. 1(a)-(b). In Fig. 7(a)-(d), a bias voltage (VP) of 0.92 V was applied to the phase compensation arm (Fig. 1(a)-(b)) to compensate for fabrication induced phase error. This VP corresponds to an electrical power of 0.71 mW based on the I-V curve of the phase shifter shown in Fig. 6. With regards to I1 and I2, the output optical power at O1 and O2 as a function of bias voltage/electrical power to the switching arm (Fig. 1(a)-(b)) is indicated in Fig. 7(a)-(d), respectively. The Vπ/Pπ in the figures refers to the amount of voltage/electrical power that is applied to the switching arm of the elementary cell to introduce a π-phase-shift and switch the output from O1 to O2, or O2 to O1 [72]. A Vπ/Pπ of 0.14 V/6.56 mW for I1-input mode, and 0.12 V/6.21 mW for I2-input mode are obtained, respectively. With an average Vπ of 0.13 V, a modulation efficiency (Vπ·L) of 0.035 V·mm is obtained, where L is the length of the switching arm. [73]. This low Vπ·L indicates high suitability of the demonstrated 2 × 2 elementary photonic switch cell for cascaded fabric and large-scale switch matrices applications, such as optical phased array (OPA) in chip-scale Light Detection and Ranging (LiDAR) [74,75]. In addition, the low average Pπ of 6.39 mW indicates low power consumption for changing switching states, which is advantageous for high power efficiency and large-scale multiplexing scheme [44,76]. At the same time, high extinction ratio (ER) of larger than 16 dB and 18 dB are measured for these optical paths.
Fig. 7. Normalized transmission (λ = 1990nm) as a function of voltage on the switching arm for (a) I1 and (b) I2. Normalized transmission (λ = 1990nm) as a function of power on the switching arm for (c) I1 and (d) I2. Normalized transmission spectrum for both “bar” and “cross” statuses at the two output ports for (e) I1 and (f) I2. The input and output ports of the 2 × 2 elementary photonic switch is illustrated in Fig. 1(a).
The wavelength dependance for both “bar” and “cross” statuses at the two output ports were measured and presented in Fig. 7(e)-(f). The insertion loss of 2.03 ± 0.84 dB and 2.57 ± 0.65 dB, as well as crosstalk lower than -16 dB and -18 dB, were recorded for I1-input mode and I2-input mode respectively, within a spectral bandwidth of 45 nm (1968 - 2013nm). The plasma dispersive switch phase shifter operates in carrier injection mode, which accounts for the higher insertion loss due to free-carrier absorption (FCA) effects [65–67].
3.2 Dynamic characteristics
The experimental setup for the dynamic characterization of the 2 × 2 elementary cell is shown in Fig. 8. A fixed laser source (λ = 1990nm) was amplified by a TDFA and connected with the FPC before coupled in and out of the chip via lensed fiber-silicon inverse tapers. An electrical square-wave was applied to the electrodes through a pattern generator (Anritsu MP1763C), which has a rise/fall time of lower than 0.1 ns (Fig. 9(a)). The clock output of the pattern generator was linked to the oscilloscope for triggering. The output temporal waveform was measured by a high-speed PD (EOT ET-5000F) with a responding speed of ∼28 ps and a bandwidth of larger than 12.5 GHz, connected via FC/APC fiber connector, and subsequently received by an oscilloscope (Agilent DSO93004L) via a SMA cable. The oscilloscope can operate up to 30 GHz frequency range, which is fast enough for our characterization.
Fig. 9. (a) Applied 50 kHz RF signal with VPP = 0.834 V and Vbias = 0.35 V. (b) The optical switch response with the zoomed-in plots on the (c) rising edge and (d) falling edge measured by the oscilloscope.
The dynamic switching characteristics of the elementary switch cell, subject to a 50 kHz square-wave signal (Fig. 9(a)), 0.834 V peak-to-peak voltage (VPP), biased (Vbias) at 0.35 V, is shown in Fig. 9(b). Figure 9(b), with reference to the applied square-wave in Fig. 9(a), presents the overall dynamic characteristics, while Fig. 9 (c) and (d) show the zoomed-in plots of Fig. 9(b). From the zoomed-in plots, the 10-90% rise (Fig. 9(c)) and fall time (Fig. 9(d)) can be extracted as 1.78 ns and 3.02 ns, respectively. To the best of our knowledge, this constitutes the fastest switching speed for silicon optical switches operating near 2 μm reported to date.
4. 4 × 4 photonic switch characteristics
To further substantiate the scalability of the 2 × 2 elementary photonic switch, we designed and fabricated the 4 × 4 silicon photonic plasma dispersive switch for the 2-μm waveband, which consists of four elementary photonic 2 × 2 switch elements (M1 - M4) through a waveguide crossing, as shown in Fig. 1(c)-(d).
With regards to the 2 × 2 elements, the applied voltage for phase compensation (VP), measured power consumptions for both bar (PBar) and cross (PCross) states, and the power (Pπ) and voltage (Vπ) consumptions to achieve a π-phase-shift for each switch element within the 4 × 4 photonic switch, are detailed in Table 2; Vπ/Pπ are obtained from the voltage/power differential between the cross and bar states. From Table 2, an average Vπ of 0.12 V and standard deviation of 0.01 are obtained. The corresponding average Vπ·L is as low as 0.032 V·mm. For Pπ, the average value and standard deviation are 6.64 mW and 0.24, respectively. The high consistency of Vπ/Pπ among all switch elements within the 4 × 4 photonic switch indicates a high degree of uniformity and scalability potential.
Table 2. Power consumption and applied voltage of each elementary cell in the 4 × 4 switcha
The measured transmission spectrum from 1968nm to 2013nm of the designed waveguide crossing (Fig. 4), with input from C2, is presented in Fig. 10, indicating an insertion loss of lower than 0.3 dB and a crosstalk of lower than -23 dB. The inset shows the crosstalk level with low variations across this wavelength range, which indicates a wide compatibility of the crossing. By implementing this waveguide crossing in the 4 × 4 configuration (Fig. 1(c)-(d)), 16 optical routing paths (P1 - P16) are realized and shown in Table 3. In the table, “1” represents “bar” state, “-1” represents “cross” state, and “0” represents the absence of input power in the ideal scenario. Table 3 also indicates the minimum power consumptions for each switching path. The values range from 5.31 mW to 19.15 mW, which are calculated with the power consumption (PBar and PCross) presented in Table 2.
Fig. 10. Transmission spectrum of the waveguide crossing from port C2 to port C4; the labelling of the ports is illustrated in Fig. 4(a). Inset: Crosstalk level over the testing wavelength range.
Table 3. Minimum power consumption for each optical path of the 4 × 4 switcha
The insertion loss across the demonstrated wavelength range for each 16 switching path listed in Table 3, is measured to be 5.47 ± 1.75 dB. As mentioned in section 3.1, such loss can be mainly attributed to the free-carrier absorption (FCA) effects. Crosstalk levels of the 16 optical paths from 1968 to 2013nm are summarized in Fig. 11(a)-(d) for P1 - P4, P5 - P8, P9 - P12, and P13 - P16, respectively. Figure 12(a) and (b) show the transmission spectra of two optical paths with minimum (-23 dB) and maximum (-15 dB) crosstalk levels respectively, corresponding to the best and worst optical spectral performance among all switching configurations of the demonstrated 4 × 4 photonic switch. Comparing to the 2 × 2 elementary switch cell, the insertion loss and crosstalk degradation is primarily due to the cascading of multiple elementary cells. Transmission spectra for all the 16 optical paths showing these insertion losses and crosstalk levels are presented in Supplement 1, Fig. S1.
Fig. 11. Crosstalk levels of each optical path (P1 - P16) in 4 × 4 photonic switch. Optical paths P1 - P16 are illustrated in Table 3.
Fig. 12. Transmission spectrum of the 4 × 4 switch for switching configurations: (a) I1 – O4; (b) I2 – O1. The labelling of input and output ports is illustrated in Fig. 1(c). The partial absence of some lines is due to the power level that falls below the measurement threshold.
Table 4 summarizes the key performance parameters of previously published silicon optical switches operating near 2 μm. Our designed 4 × 4 silicon photonic plasma dispersive switch in this work exhibits favorable performance, including fastest switching speed, minimal power consumption, and broad bandwidth.
Table 4. Key performance of reported silicon optical switches near 2 μma
5. Conclusion
In this work, we present high-speed silicon photonic plasma dispersive switches operating at the 2 μm waveband. The static and dynamic characteristics of the devices are comprehensively evaluated. The 2 × 2 elementary photonic switch exhibits the fastest switching speed to date among silicon optical switches operating near 2 μm with rise and fall time of 1.78 ns and 3.02 ns, respectively. The Pπ of 6.21 mW, with ER larger than 16 dB, and a crosstalk of lower than -16 dB across the 45-nm bandwidth are demonstrated with high uniformity at both input ports. The 4 × 4 plasma dispersive photonic switch indicates a minimum power consumption of 5.31 mW and a crosstalk of lower than -15 dB within the range of 1968nm to 2013nm for all 16 optical paths. Given its favorable performance and chip-scale size with good scalability, the designed optical switch presents substantial utility in promoting next-generation high-speed integrated applications at the 2 μm waveband.
Funding
Ministry of Education - Singapore (MOE-T2EP50121-0005).
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
Supplemental document
See Supplement 1 for supporting content.
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