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Abstract
Top-illuminated PIN photodetectors (PDs) are widely utilized in telecommunication systems, and more efforts have been focused on optimizing the optical responsibility and bandwidth for high-speed and capacity applications. In this work, we develop an integrated top-illuminated InP/InGaAs PIN PD with a back reflector by using a microtransfer printing (µ-TP) process. An improved µ-TP process, where the tether of silicon nitride instead of photoresist, is selected to support an underetched III-V device on an InP substrate before transfer. According to theoretical simulations and experimental measurements, the seamless integration of the PD with a back reflector through µ-TP process makes full use of the 2nd or even multiple reflecting light in the absorption layer to optimize the maximum responsibility. The integrated device with a 5 µm square p-mesa possesses a high optical responsibility of 0.78 A/W and 3 dB bandwidth of 54 GHz using a 500 nm i-InGaAs absorption layer. The present approach for top-illuminated PIN PDs demonstrates an advanced route in which a thin intrinsic layer is available for application in high-performance systems.
© 2022 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
With the growing demand for telecommunication systems, optical modules must continuously upgrade to cope with the high capacities needed for data transmission systems, such as short-link applications. In short-link applications, optoelectronic converters are a key part that transforms a modulated light signal to an electrical current at a high modulation frequency. High-speed photodiodes with superior quantum efficiency and power handling capability are critical in converters. InP/InGaAs-based PIN photodetectors (PDs) offer both excellent opto-electro conversion efficiency and a low dark current and have been widely utilized in these systems [1–3]. However, the trade-off between responsibility and bandwidth in PIN PDs restricts further high-performance applications. Structural improvements, such as bottom-illuminated and resonant cavity enhanced (RCE) structures, have been proposed to enhance the optical responsibility [4,5]. Compared with these two structures, top-illuminated PIN PDs, with the advantages of a simpler fabrication process and easier light coupling in modules, lack both high speed and capacity due to the absence of multi-absorptive structures. Thus, structural improvement for top-illuminated PIN PDs, similar to the top reflector in bottom-illuminated devices, is necessary. In this case, a back reflector is alternative that can be applied for responsibility optimization.
It is well-known that high-quality III-V epitaxial layer is unable to be grown on the metals. The difficulty of inserting a back reflector between the active region and substrate is addressed by transferring the PD from the native substrate to another substrate with a reflecting metal layer. Micro transfer printing (µ-TP) is an emerging technique that allows the transfer of epitaxial layers from a source substrate to a target substrate [6,7]. The µ-TP method enables parallel operation, and most of the device processes on the source substrate and pre-integrated processes on the target substrate are performed individually, which avoids processing conflicts between heterogeneous materials [8–11]. Additionally, µ-TP has been applied in III-V semiconductors [12–18], especially InP/InGaAs [19–23], based on state-of-the-art reports.
In this work, we demonstrate a new structural design with a back reflector in a top-illuminated InP/InGaAs PIN PD to optimize the responsibility and bandwidth. In the µ-TP process, the tether of silicon nitride (SiNx) instead of photoresist is selected to support an underetched III-V device on an InP substrate before transfer. To enhance the 2nd light absorption, a near-junction metal reflector evaporating on the substrate is constructed beneath the integrated PD. The integrated device with a 500 nm intrinsic InGaAs layer possesses an optical responsibility of 0.78 A/W and 3 dB bandwidth of 54 GHz. The present device exhibits the potential to enable a feasible route to integrate top-illumination PDs in high-performance optoelectronic integrated circuits (OEIC) and optical systems.
2. Design of device structure and fabrication
A schematic of the integrated top-illuminated InP/InGaAs PIN PD is shown in Fig. 1. The PD consists of a conventional top-illuminated PIN PD with a back reflector.
Fig. 1. (a) Layout of the integrated top-illuminated PIN PD with a back reflector; Schematic of mesa structure: (b) the conventional top-illuminated PIN PD; (c) the integrated top-illuminated PIN PD with a back reflector.
For comparison, two pairs of nonintegrated (Fig. 1(b)) and integrated (Fig. 1(c)) samples were fabricated. The process flow for the integrated device is shown in Fig. 2(a)-(k).
The stack of epitaxial layers (details shown in Table 1) was designed to be grown on a semi-insulated InP substrate by molecular beam epitaxial (MBE) (Fig. 2(a)): (i) Lattice-matched sacrificial layers of In0.53Ga0.47As (InGaAs) and the etch-stop layer of InP were grown alternately on an InP substrate. It should be noted that these two layers did not exist in the reference samples; (ii) Highly doped n-contact InGaAs and n-doped InP were subsequently grown; (iii) Intrinsic InGaAs (500 nm), which is considered to exceed 40 GHz of bandwidth [24], served as the absorption layer; and (iv) Layers of p-doped InP and p-contact InGaAs were finally grown on the top of the sample.
Table 1. Epitaxial Stack of Integrated InP/InGaAs PIN PD
A p-contact metal of Pt/Ti/Pt/Au was deposited on the top surface of p-contact InGaAs, and then an InGaAs wet etchant (mixture of H3PO4:H2O2:DI = 3:1:50) was used to etch the top InGaAs until p-InP was revealed (Fig. 2(b)). A thin layer of 50 nm SiNx was firstly grown by plasma-enhanced chemical vapor deposition (PECVD) and then partially etched away by inductively coupled plasma (ICP) to define the p&i-mesa of the PD. Next, InP wet chemical etchants (mixture of H3PO4:HCl = 4:1) and abovementioned InGaAs wet etchant were used to remove the p-InP, i-InGaAs and n-InP layers until n-InGaAs (Fig. 2(c)). An n-contact metal of Ti/Pt/Au was deposited to form ohmic contact to n-InGaAs (Fig. 2(d)). Another period of wet etching was implemented to form the PD mesa and sacrificial mesa (Fig. 2(e)).
To avoid post-processing O2 plasma etching of the photoresist tethers [18], an improved process was explored. A layer of passivation SiNx, with the thickness of 200 nm, was deposited by using PECVD and was etched by SF6 to form tethers. The tethers served as anchors to enable device linking to the substrate after the sacrificial layer was underetched (Fig. 2(f) and Fig. 3(a)).
Fig. 3. SEM image of PD (a) with sacrificial layer; (b) supported by SiNx tethers. (c) Optical image of PD after integration and metallization; (d) Cross-section detail of red dash area in (c).
Wet etching, soaking in a mixture of FeCl3:DI = 1 g:2 ml for 35 mins, was used to remove the sacrificial InGaAs layer [25]. After the sacrificial layer was etched, the prefabricated PD was anchored to the InP substrate by SiNx tethers forming a state of suspension (shown in Fig. 2(g) & Fig. 3(b)). A thin Ti/Au film, defining the integrated area and serving as the back reflector (Back Refl.), was pre-deposited on the Si substrate. Afterward, an interlayer of methylbenzene-diluted divinyl siloxane bis-benzocyclobutene (DVS-BCB), which offers excellent insulation, was coated onto the substrate.
In the µ-TP process, a polydimethylsiloxane (PDMS) stamp with micropillars was aligned to attach PDs and quickly laminated to pick up the devices from InP substrate by a contact lithographic machine (Süss MJB3). Then the stamp was moved onto the pre-determined places on Si substrate to place the devices by lifting up slowly (Fig. 2(h)). After printing, the Si substrate was baked to obtain full curing of the interlayer (Fig. 2(i)). A planar BCB layer was spin-coated on the hard cured substrate, and another curing treatment was applied (Fig. 2(j)). Dry etching by a mixture of SF6 and O2 was used to open the inter-via. Finally, electroplating were applied to form the testing electrode pads (Fig. 2(k)).
In order to compare the properties of device with and without a back reflector, two pairs of 5 and 10 µm square p-mesa, aiming to high-speed application, were fabricated. The details of prepared samples were shown in Table 2.
Table 2. Details of Integrated and Reference Samples
The photography details, depicted in Fig. 2(f) and Fig. 2(g), was shown in Fig. 3(a)-(c). The cross section of an integrated PD with a back reflector is given by Fig. 3(d). Notably, the processes of Reference samples were nearly same to the Integrated samples, except for the absence of under-etching, transferring and printing shown in Fig. 2(g)-(i).
3. Device measurement and analysis
3.1 Device measurement
The scheme of the O-E measurement system is plotted in Fig. 4. This setup mainly has a vector network analyzer (VNA, ROHDE&SCHWARZ ZVA67), a DC source (Agilent E5263A), a Vector Signal Generator (VSG, ROHDE&SCHWARZ SMW200A), a signal spectrum analyzer (SSA, ROHDE&SCHWARZ FSW), a bias tee and a 1550 nm laser module including a laser source and a modulator. For electrical signal transmission, a 67 GHz GSG probe station was connected to the bias tee. A fiber with a tapered head (single-mode fiber with spot diameter of 2.5 ± 0.3 µm at 1/e2 level) rather than a flat head was used to couple the laser light into the devices. Due to the margin between the spot size of tapered fiber and the size of the active window (shown in Table 2) is at least 0.5 µm for all devices, the coupling efficiency was estimated to be at least 95% for 5 µm square p-mesa PD and nearly 100% for 10µm square p-mesa PD.
Fig. 4. Scheme of O-E measurement system (black solid & dash line for electrical link; red dash line for optical link).
The measured I-V curves of dark currents for the prepared samples are shown in Fig. 5, and the detailed data are listed in Table 3. Notably, the dark currents of S.iii and S.iv show no obvious deterioration compared with R.i and R.ii. At a reverse bias voltage, the dark current of integrated PDs is numerically lower than the values of nonintegrated devices. The lower dark current is attributed to the leaking behavior of the substrates, where DVS-BCB has better insulation than the semi-insulated InP substrate.
Table 3. Dark Currents of Integrated and Reference Samples
The tapered fiber is used to couple the light into the PDs and the corresponding responsibility value, shown in Fig. 6(a)-(c), of the smaller p-mesa (0.43 A/W of R.ii and 0.78 A/W of S.iv) is smaller than that of the larger p-mesa (0.45 A/W of R.ii and 0.83 A/W of S.iii). Here, the lower responsibility of smaller device is attributed to the slight misalignment between the spot and the active window.
Fig. 6. O-E responsibility measurement: (a) under -2 V bias; (b) under -3 V bias; (c) under -4 V bias (navy and orange dash line indicate saturation point for 5 and 10 µm square p-mesa samples, respectively).
Thereafter, frequency-dependent S21 curves of the four samples were recorded and are shown in Fig. 7(a)-(e), and the values of the 3 dB bandwidth, f3dB, under specific conditions are summarized in Table 4.
Fig. 7. O-E bandwidth measurements of (a) R.i and R.ii at -4 V bias voltage; (b) S.iii under 0.5 mW light; (c) S.iii under 2 mW light; (d) S.iv under 0.5 mW light; (e) S.iv under 2 mW light.
Table 4. Detailed 3 dB Bandwidths of Samples
In the S.iii and S.iv samples under a low light power of 0.5 mW, the bandwidth shows no obvious variation since the applied low voltage can afford a sufficiently high electrical field to support carriers drifting through the intrinsic layer with saturated velocity. However, as the light power increases to 2 mW, the photocurrent begins to saturate at a low bias, where a large amount of photogenerated carriers weakens the applied electrical field. A larger p-mesa area is associated with a higher saturated current value so that the bandwidth of S.iii under 2 mW illumination exhibits a slight drop, while the bandwidth of S.iv shows a more obvious drop. Although a high bias voltage accommodates a high bandwidth, it cannot balance the influence of current saturation.
The radio frequency (RF) output powers versus the incident light power of the samples are presented in Fig. 8. The handling capacity of RF output power is usually represented by the large signal 1 dB compression current I1dB. It is defined as the average photocurrent at which the RF output power decreases by 1 dB from the expected linear response. As shown in Fig. 8(a) and (b), an initial increase with a linear slope is observed when the input light power remains at a low level. To obtain the same output power, integrated PDs require 2.1 dB lower light power than nonintegrated PDs. This value is correlated to a 1.8 times higher responsibility, which is converted to 2.5 dB. The I1dB of our devices are 4.15, 4.22 mA for R.i, S.iii at 20 GHz and 1.60, 1.67 mA for for R.ii, S.iv at 40 GHz. Corresponding maximum RF output powers are -18.7, -19.1, -35 and -35.4 dBm. The RF saturated properties remains the same for PDs with the identical size.
Fig. 8. RF output power measurement (a) output of R.i and S.iii at f = 20 GHz; (b) output of R.ii and S.iv at f = 40 GHz.
3.2 Results analysis
As shown in Fig. 6(a)-(c), by applying the back reflector, compared with R.i and R.ii, S.iii and S.iv demonstrate obvious improved behavior because photocurrents have larger values at every bias voltage. Particularly at -4 V bias, the responsibility has increased by 84% and 77% for S.iii and S.iv compared to the values for R.i and R.ii, respectively.
The improved responsibility results from structural improvement, where the back reflector leads to a double light absorption in the 500 nm i-InGaAs absorbent layer.
To analyze the improvement, the theoretical curves of responsibility with and without a back reflector were calculated, respectively.
The responsibility of the top-illuminated PD without a back reflector, Ract, can be expressed as Eq. (1), where Rideal is the ideal responsibility for a specific wavelength, R0 is the reflectance at the top–semiconductor interface, α is the absorption coefficient, which approximately equals 1×104 cm-1 at 1550 nm [26], and di is the thickness of the absorbent layer. For InGaAs absorbing at 1550 nm, the first item of Eq. (1), Rideal, is approximated to be 1.25 A/W so that the expression can be written as Eq. (2). The top SiNx layer, with a total thickness of 250 nm, is served as an anti-reflection (AR) layer. The R0 is estimated to be 0.1 by the contrast of the measured responsibilities before and after the dielectrics, including planar-BCB and the AR layer, above the active window is etched away in our private experiment. Here, the responsibility of the nonintegrated PD, Rref, versus thickness of absorbent InGaAs is plotted as a black line in Fig. 9(a).
The back reflector is designed for S.iii and S.iv; thus, the light absorption includes the light reflected by the bottom metal. The responsibility of the integrated PD, RInte, can be written as Eq. (3). Compared to Eq. (2), Eq. (3) has two additive items: the 2nd absorption by InGaAs layer and the waste absorption by the bottom InGaAs. Rmetal is considered to be 1 due to ultra-smooth surface of evaporated metal and db-InGaAs is the total thickness of the bottom InGaAs under active PD layers. To assign these parameters into Eq. (3), the relationship among the integrated PD, RInte, and the thickness of the absorbent layer can be given by the black dashed line in Fig. 9(a).
The responsibilities of the fabricated samples are also noted in Fig. 9(a). The data well match the theoretical prediction. Notably, the measured RInte is slightly larger than the theoretical value due to multiple absorptions resulting from the light reflection back and forth between p-metal and bottom metal except for the 2nd light reflection.
In addition, by tuning the bias voltage from -2 to -4 V, the applied electrical field between pin junctions was accordingly increased in the prepared devices. The increased field enables more generated electron-hole pairs to be separated to neutralize this field, which leads to a higher saturation point of the photocurrent. Therefore, it can be found in Fig. 6(a) to (c) that the starting point of current saturation (the navy dotted line for a small device and the orange dotted line for a large device) increases along with the reverse bias from the dotted line indication. That is, saturation occurs at nearly the approximately same photocurrent for identically sized devices.
To investigate the bandwidth limit of the samples, equivalent modeling of the resistance-capacitance (RC) time and the carrier transit time was applied.
In principle, the total bandwidth f3dB can be given as Eq. (4), where v is the average drift velocity in the intrinsic layer, di is the thickness of the intrinsic InGaAs layer, Sp is the active area of p-mesa and Rt is the total resistance of the PD device [28]. According to the PIN PD modeling reported by W. Yih-Guei [29], Rt in Eq. (4) can be written as Eq. (5), where τp is the p-contact resistivity, Wcp is the coverage area of the p-contact metal, L is the active length of p-mesa, Rps is the p-contact sheet resistance, T is the thickness of all p-layers, Rns is the n-contact sheet resistance, G is the gap between p-mesa and n-metal, τn is the n-contact resistivity and Wcn is the coverage area of the n-contact metal. By assigning all the parameters listed in Table 5, corresponding Rt for 5 µm and 10 µm square p-mesa are 6300 Ω and 2800 Ω, respectively.
Table 5. Parameters for Bandwidth Calculation
Based on this modeling, the theoretical bandwidth versus the length of p-mesa, by taking 500 nm i-InGaAs into account, is presented in Fig. 9(b). Particularly, from the theoretical prediction for the bandwidths, the PD with a 5 µm square p-mesa exceeds 50 GHz, and the PD with 10 µm square p-mesa is nearly 29 GHz. These values clearly match the measured values.
4. Conclusions
Integrated top-illuminated InP/InGaAs PIN PDs on silicon substrates with a back reflector based on the µ-TP process were investigated. To improve the µ-TP process, tethers of high-strength SiNx instead of regular photoresist were applied to anchor underetched PD to native substrates. A layer of evaporating metal, several hundred nanometers beneath the device, served as a near-junction reflector to enhance full absorption of the illuminated light and multiple reflection. Through optimizations, the PD with a 500 nm i-InGaAs absorption layer demonstrates both a high optical responsibility of 0.78 A/W, which is nearly 80% higher than 0.44 A/W corresponding to the device without improvement, and 3 dB bandwidth of 54 GHz. The 2nd absorption of light through the back reflector is taken into account to target the O-E performance. The optimized PD promises an improved structure for both capacity demand and fast data transmission in high-performance OEIC and optical systems.
Funding
National Natural Science Foundation of China (No. 61991431); National Key Research and Development Program of China (2018YFA0209100).
Disclosures
The authors declare no conflicts of interest.
Data Availability
Data underlying the results presented in this paper are available in Ref. [26], Ref. [27].
Supplemental document
See Supplement 1 for supporting content.
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