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Abstract
In this paper, we present the design, fabrication and characterization of a carrier depletion silicon-photonic switch based on a highly doped vertical pn junction. The vertical nature of the pn junction enables the device to exhibit a modulation efficiency as high as 0.23 V.cm. Fast switching times of 60ps are achieved in a lumped configuration. Moreover, the process flow is highly tolerant to fabrication deviations allowing a seamless transfer to the 350 nm process node of a commercial complementary-metal-oxide semiconductor (CMOS) foundry. Overall, this work showcases the possibility of fabricating highly efficient carrier depletion-based silicon photonic switches using medium resolution lithography.
© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
Addressing the ever-growing increase in global internet traffic produced by a nearly exponential growth in cloud-based applications, social media and big data analytics is constantly challenging data center (DC) infrastructures. By the end of 2021, global IP DC traffic will reach an astounding number of 20.6 Zettabytes (ZB) [1](versus 6.8 Zettabytes in 2016) per year putting ever more pressure on data center infrastructures. As a result, there is a strong need for low cost, high speed, low power interconnect and switching technologies. This is precisely what silicon photonics is expected to address in a timely manner. Indeed, silicon photonics technology scalability/cost ratio makes it naturally suited to become the technology of choice for current and beyond single mode 100G intra-DC interconnects required for warehouse-sized [2] data center infrastructures. On the other hand, the commercial emergence of single mode silicon photonic transmission modules interconnecting servers is leveraging the implementation of the same technology ever closer to the server core. Indeed, silicon photonics is a single mode technology that has the potential to boost the I/O bandwidth offered by the most advanced switching application-specific integrated circuits (ASIC) [3] (128x 100GbE, 12.8Tb/s) in a seamless fashion [4], replacing lossy and power hungry serializer/deserializer (SerDes) metal traces with optical ones to break the distance bandwidth product. The latter determines how far an electrical or optical signal transporting information at a given data rate can be pushed across a communication medium. On the other hand, adding chip-scale routing functionalities [5] in the optical domain for low power on- chip, chip-to-chip and board-to-board interconnects would consolidate silicon photonics as the main enabling technology for future exascale data centers.
In this paper, we present a 2 × 2 electro-optic (E/O) silicon photonics switch based on a vertical pn junction that is versatile enough to be used also as an electro-optic modulator in a lumped configuration. In addition to its versatility, the switch vertical pn junction has been intentionally designed in a way that it is much less sensitive to fabrication variations than conventional lateral/horizontal pn junction-based silicon photonic modulators.
Up to date, switching mechanisms based either on thermo-optical [6–12], opto-mechanical [13] or electro-optical carrier injection effects [14–22] have been reported. The key for electronic switching matrices to be gradually replaced by photonic switching matrices is to reduce the power consumption. Although producing thermo-optical based devices is relatively straightforward, the use of on-chip resistive electrodes may lead to high power consumption, complex thermal management across large matrices and relatively slow switching times (in the microsecond range) [23], which may limit their applicability. Opto-mechanical switches are the technology of choice for large capacity optical networks [24] but integration requires the use of MEMS with relatively high latency. By contrast, electro-optical effects in silicon induced by changing the free carrier densities are gradually taking over as the most effective way to achieve high performance switching due to its low latency and high level of integration. This effect, related to the variation in concentration of free carriers in silicon, which changes the real and imaginary parts [25] of the refractive index, enables switching times on the order of a few ns when the pn junction (or p-i-n diode) is operated in injection, and down to 10 to a few tens of picoseconds when operated in the depletion regime with a suitable radio-frequency (RF) design.
Whereas carrier depletion is mostly used for high speed (up to 70Gb/s) [26–30] modulation purpose due to the fast dynamics of majority carriers, carrier injection is rather used for switching applications where switching time (in the ns range) is not as critical. Here, we investigate the possibility of using the carrier depletion mechanism as a means to achieve efficient and fast switching using an alignment tolerant fabrication process.
2. Device design
The active region has been designed relying on a shallow etched waveguide configuration. The chosen semiconductor structure is a vertical pn junction (see Fig. 1) which, on the one hand, allows us to achieve a larger effective index change than horizontal pn junctions [31] and on the other hand, is more tolerant to potential mask alignment errors since its formation is dictated by the implantation energy rather than the resolution of the optical lithography. Early vertical pn junctions relied on doped polysilicon deposition [32] However, although the use of polysilicon is standard in CMOS processes, it is usually much lossier than its crystalline counterpart. More recently, a highly efficient “u-shaped” pn junction was demonstrated [33] showing values ranging between 4.6 V.mm and 2.6 V.mm at a low voltage (−0.5 V on different devices). However, this high efficiency comes to a price. First, its formation requires the use of several low and medium energy implants that makes it more difficult to align the different implantation layers, which implies an increase in process costs. In addition, 0° tilt implantation (rather than the usual 7° standard) strongly increases boron channeling, reducing the control on the vertical pn junction positioning. Finally, the small waveguide height (220 nm) limits the expansion of the reverse-biased pn junctions resulting in a strong decrease of the modulation efficiency as the reverse voltage increases.
The active (doped) region has been modeled with Athena and Atlas, which are process and device simulation software from Silvaco [34], respectively. The charge carrier densities are numerically calculated and converted into real and imaginary refractive indices via Soref’s empirical equations [25]. The fractional change in effective index may also be optimized when considering the holes/electrons density ratio. According to Soref’s equations, holes are more efficient than electrons in changing the refractive index for carrier concentrations up to 1019 cm−3, and absorb less photons than electrons.
It was shown that based on rather simple analytical approximations, one may calculate the optimum holes/electrons density ratio that allows the effective refractive index change to be maximized on the p-type side [35]. Briefly, assuming homogeneous donor/acceptor densities and an abrupt junction, the effective index change on the p-type side is maximized when Na = 1.5Nd where Na, Nd are respectively the acceptor (holes) and donor (electrons) concentrations.
However, this optimized acceptor/donor ratio becomes challenging to apply to real implantation processes which commonly produce profiles that are far from idealized homogeneous densities of impurities separated by abrupt boundaries [36]. Achieving virtually homogeneous implantation profiles would require multiple implantation steps and well controlled rapid thermal annealing processes which would in turn increase the wafer processing time and overall cost of the fabrication process. Before designing any silicon electro-optical device, it is paramount importance to ensure that the actual implantation profiles are well known and accurately fitted to the simulated ones. This is especially true in the case of vertical pn junctions, where the pn junction boundary depends mostly upon the energy, dose and resulting implantation profiles and not on the mask window edges above the waveguide, just as for horizontal/lateral pn junctions. As a first approximation, one may analytically approximate the implantation profile by a one-dimensional Gaussian curve. However, although the fit is almost always good near the implantation peak, there is a pronounced skewness in the actual distributions. To account for the skewness as well as any tailing character, we included built-in Pearson distributions in Silvaco. To ensure the accuracy of the simulations, a series of implantations were performed “in-house” with an upgraded Varian 350D ion implanter. The vertical pn junction was designed following these guidelines and the implantation energies and doses were chosen accordingly.
3. Fabrication process
Early prototypes of the 2 × 2 carrier depletion switches were fabricated in NTC-UPV 6-inch clean room facilities [37]. The silicon-on-insulator (SOI) wafers feature a 220 nm thick layer of crystalline 100 silicon with a 2 µm buried oxide (BOX) underneath to achieve the required index contrast for efficient modal confinement. The fabrication of the switches requires 5 chromium masks for 365 nm “i-line” optical lithography, with the minimum feature size being 1 µm. Two additional high-resolution e-beam lithography steps are required to form the sub-µm optical waveguides and oxide spacers although industrial 248 nm deep-UV or 365 nm “i-line” steppers with higher alignment accuracy could seamlessly substitute these in large volume CMOS foundries. The process starts with the definition of the pn junction area via 365 nm i-line lithography (EVG-620) on a 1 µm-thick soft backed (100°C) AZMIR (All-resist AR-P 679.04) photoresist. Then follows the formation of the vertical pn junction, where the implantation energies define the implant depth and therefore the relative positions of the p-type and the n-type impurity profiles. It is worth noting that only one photomask is required to form our vertical pn junction (instead of two for lateral pn junctions) resulting in a potentially significant cost reduction. Phosphorus (P31) is implanted with an energy of 150 keV and a dose reaching 8e13 cm−2. BF2 is then implanted with an energy of 100 keV and a dose reaching 6e13 cm−2 (see Fig. 2(a)). Owing to its higher mass, BF2 has been preferred over boron, in order to achieve a narrower doping and shallower implant profile. Shallow-etched (70 nm etch-depth leaving a 150 nm thick slab) waveguides and grating couplers are defined with e-beam lithography (RAITH 150) with FOX-12 photoresist and reactive ion etching with inductive coupling plasma source (STS ICP-RIE) as shown in Fig. 2(b). Then, a 100 nm-thick silicon oxide (SiO2) “implant blocker” is deposited using PECVD (Centura P5200) on top of the active waveguide region and etched by means of a selective etch recipe to avoid undesired silicon over-etching during the process (see Figs. 2(c) and 2(d)). The oxide spacer plays an important role as it helps relax the alignment tolerances of the subsequent p++ and n++ implantation steps. It is worth noting that the oxide spacer is required here due to the low alignment accuracy (± 1 µm) of our 365 nm “i-line” mask aligner but it would no longer be needed in large volume foundries where alignment accuracy is far better. The p++ and n++ shallow-heavily doped regions are then defined using i-line 365 nm optical lithography with respective energies and doses of 50 keV and 1e15 cm−2 (see Figs. 2(e) and 2(f)). A subsequent annealing step at 1000°C for 15s (with 20°C/s ramp up and down) was initially found to be a good trade-off between dopant redistribution, activation and ion damage recovery. 700 nm thick oxide (PECVD, Centura P5200) is then deposited and trenches are etched down to the highly doped regions (see Fig. 2(g)) to prepare the samples for the metallization step. To achieve good ohmic metal-semiconductor contacts (not to limit the switching speed) a good metallization process is required. A 3 µm thick resist layer is first deposited on top of the SiO2 cladding and exposed followed by the physical vapor deposition (PVD, PFEIFFER vacuum classic 500) of a 50/700 nm thick Ti/AlCu layer, and annealed for 30 min at 350°C (see Fig. 2(h)). The unexposed resist is then removed via a lift-off process in order to pattern the electrodes (see Fig. 2(i)).
Fig. 2. Silicon switch process flow, (a) P (150 keV, 8e13 cm−3), and BF2 (100 keV, 6e13 cm−3) implantations, (b) e-beam lithography and RIE etching of waveguides/grating couplers, shallow-etch step (70 nm), (c) 100 nm thick SiO2 spacer deposition (PECVD) and (d) subsequent etching, (e) BF2 (50 keV, 1e15 cm−3) and (f) P (50 keV, 1e15 cm−3), (g) 700 nm SiO2 oxide windows RIE etching, (h) metal evaporation (PVD), (i) lift-off.
Additional in-situ information to monitor the process quality (lithography, alignment, cleaning) was acquired via microscope inspection of backup wafers. The key steps are illustrated in Fig. 3.
Fig. 3. In-situ process monitoring via optical microscope inspection of key process stages: (a) pn junction formation and SiO2 spacer formation, (b) heavily doped region before RTA (ion damage visible), (c) oxide windows on top of the n++ and p++ region after RTA (ion damage partially recovered), (d) final 1.25mm-long 2 × 2 switch metal pads. (e) GDS layout of the 2 × 2 switch.
4. Rapid prototyping: 1st generation of E/O switches
4.1 DC characterization
The DC characterization results of an asymmetric 1.25 mm-long Mach-Zehnder interferometer (MZI) for varying drive voltage (from + 0.75 V to −6 V) is shown in Fig. 4. The pn junction is 6 µm-wide to ensure relaxed process tolerances and to rule out any undesired effects produced by potential mask misalignment. For high-speed operation (see section “high speed characterization” further in the text), the pn junction width is significantly reduced at the expense of tighter fabrication tolerances.
Fig. 4. Transfer function of the asymmetric MZI with 100 GHz channel spacing for varying DC voltages, obtained at (a) in1-out1 (T11), (b) in1-out2 (T12), (c) in 2-out 2 (T122) and (d) in2-out1 (T21).
The 2 × 2 switch is driven just below the pn junction threshold voltage to benefit from a high modulation efficiency while preventing slower AC operation caused by slow minority carrier recombination time. The device exhibits a clear symmetric behavior in terms of phase shift for any input/output (T11, 12, 21 and 22) ports combinations as illustrated in Figs. 4(a)–4(d). Figures 5(a) and 5(b) show that the switch is highly efficient between + 0.7 V and −0.8 V, reaching a state-of-the-art efficiency of 0.23 V.cm to 0.5 V.cm between │ΔV│=0.2 V and │ΔV│=1.5 V (starting just below the threshold voltage at + 0.75 V) for a pn junction-based silicon modulator. Beyond −1.5 V, the switching device reaches a “plateau” and is no longer performing efficient switching. The reason for this saturation is the probably excessive duration of the annealing step (15s) that has likely caused uncontrolled impurity diffusion and degraded the pn junction integrity. A deeper analysis is needed to clarify the root cause and will be described further in the text.
Fig. 5. (a) Effective index change vs varying voltage and (b) figure of merit VπLπ in the four possible I/O configurations (T11, T12, T21, T22).
As mentioned previously, the pn junction of the device is 6 µm-wide, which acts as a large capacitor exhibiting ns-range charging and discharging RC time constants. This makes the device unsuited for Gb/s switching operation. The device was designed on purpose for precise DC assessment. To achieve high speed operation, we designed a 2 µm wide pn junction, which is the smallest achievable pn junction based on our lithography resolution (i-line 365 nm) and alignment constraints (±1 µm). It is worth mentioning that the final pn junction width is highly dependent on the equipment performance as far as alignment tolerance and lithography resolution are concerned. State-of-the-art performance and high yield could flawlessly be achievable in more advanced CMOS-foundry while maintaining the straightforwardness of the fabrication process. In our process flow, the lithography resolution and process flow limit the minimum width of the pn junction to around 2 µm. Our simulations show that this is sufficient to achieve switching speed in the GHz-range in a lumped configuration which is enough for short packet switching/routing applications to speed up data flow within the network. The fiber-to-fiber total loss of the 2 × 2 switch with a 6 µm-wide pn junction are 30 dB of which, 1.6 dB account for the MMI losses, 2.4 dB come from the 100 µm rib bend loss (see [38] for more details on the subject), 9 dB from the I/O grating couplers, 0.5 dB from the 12 µm to 400 nm tapers, 5.5 dB from the standard passive rib waveguides, and finally 11 dB (1.25mm*8.8 dB/mm) come from the phase shifter. On the other hand, the losses of the 2 × 2 switch with a 2 µm-wide pn junction was 41.5 dB due the phase shifter loss reaching 22.5 dB (1.25mm*18 dB/mm). A possible explanation for this degradation may simply be an alignment accuracy problem since working close to the intrinsic resolution and alignment limits. Indeed, our “i-line” lithography tool may have caused some irregular exposed resist patterns and some regions close to the waveguide may have kept unprotected. As a result, heavy ion implantation may have “leaked” very close to the waveguide in these regions. On the other hand, impurities coming from the heavy implanted regions may likely have diffused very close to the waveguide during the rapid thermal annealing step (1000°C for 15s) which we suspect had an excessive duration based on a cross-check analysis of the saturation at low voltage and losses. This has had a direct impact on the losses and extinction ratio of the device by lowering the MZI maximum extinction ratio to 7 dB. It is worth mentioning that the overall losses can be notably reduced by optimizing the fabrication of passive and active components.
4.2 High speed characterization
High speed electro-optical characterization of the lumped device was performed to assess the maximum modulation speed. Data transmission measurements were carried out driving the 2 × 2 switch with a “1−0” or “on-off” pattern delivered by a bit pattern generator (SHF BPG 44E). The electrical signal was amplified through a 40 GHz driver (SHF-810) to achieve the required voltage swing and coupled to a DC bias voltage. The output modulated optical signal is photodetected by a 40 GHz digital communication analyzer (Infiniium DCA-J 86100C).
In order to compensate for the low extinction ratio of the device, a 5Vpp voltage swing plus a −2.2 V DC voltage was applied to the switch (T12) through a bias tee to ensure that the switch is always driven below the pn junction threshold voltage and in the carrier depletion regime (see Fig. 6). Time measurements show that the switch rise and fall times are as low as 60 ps allowing for fast switching operation. Data transmission measurements were carried out using a non-return-to-zero (NRZ) PRBS of length 27−1 and the extinction ratios and bit rate transmission of the 1.25 mm-long, lumped 2 × 2 switch was measured to be 4.7 dB and 4.1 dB at 2.5 Gb/s and 5 Gb/s, respectively. The fast rise and fall times (60 ps) indicate that the pn junction is two times faster than anticipated by our transient simulations from which we obtained a value of 120 ps for a lumped configuration and a 1.25 mm-long phase shifter with a 2µm-wide pn junction. This confirms the fact that the pn junction is actually narrower than expected and features therefore a smaller capacitance. This narrowing of the pn junction due to the closer proximity of the heavily doped p++ and n++ regions to the optical mode is beneficial in terms of device speed but clearly detrimental in terms of insertion loss. Based on Silvaco transient simulations enabling 60 ps rise and fall times (instead of 120 ps) and 11.5 dB excess insertion losses, the actual width of the pn junction is estimated to be between 1 µm and 1.2 µm, instead of 2 µm. For this particular geometry, a trade-off between speed and insertion loss is found to be 1.4 µm for switching applications. However, this value can be reduced slightly to increase the device speed (at the expense of increasing the insertion losses) as may be required for 1 × 1 E/O modulators, where modulation speed is a key metric and a slight increase in losses may be tolerated depending on the application.
Fig. 6. (a) Rise and fall time measurements (60ps) at 5Vpp. Bias voltage is −2.2 V, (b) 2.5 Gb/s and (c) 5Gb/s eye diagram acquisition through input port 1/output port 2.
5. Transfer to commercial CMOS foundry: 2nd generation of E/O switches
To show the full potential of the device in terms of tolerance to alignment error, scalability and cost effectiveness, the design and process flow was seamlessly transferred to Austria Microsystem (ams AG) CMOS foundry. The fabrication steps were performed entirely on a 365 nm i-line stepper routinely used for large volume 350 nm node microelectronics production. The purpose of this transfer was to show that a given design may seamlessly be prototyped in a flexible small-scale pilot foundry (NTC-UPV), tested and transferred in a large-scale foundry (ams AG) thereby minimizing the development cost. Pictures of the fabricated 2 × 2 switch are shown in Figs. 7(a) and 7(b). Although the process flow remains mostly unchanged, some steps were slightly altered according to ams AG’s specific design rules and back-end-of-line (BEOL) fabrication stages.
Fig. 7. (a) and (b) Optical microscope picture of the 2 × 2 switch fabricated in ams AG foundry with a 3 Metal layer stack. On the one hand, the oxide spacer is no longer needed (see Fig. 2(d)) since the alignment tolerance of ams AG’s i-line stepper is good enough to position the p++ and n++ region with sufficient accuracy and on the other hand, the metallization follows (c) ams AG’s BEOL standards with the use of three metal levels instead of just one as available in NTC-UPV 6‘‘ wafer-processing line.
5.1 DC characterization
To assess the performance of the 2 × 2 switch, standard DC testing was performed. As shown in Figs. 8(a)-(d), all four possible switching states (T11, T12, T22, and T21) were achieved by applying the optimum bias values for push-pull operation. The pn junction is indeed efficient enough to allow DC biases to compensate for the slight phase differences in each MZI arm. This removes the need for power hungry thermo-optical bias adjustment mechanisms. Multi-mode interference (MMI) couplers are also highly symmetric enabling fully symmetrical switch operation. In order to set the switch around the quadrature point, the optimum DC voltages for the range 1535-1540 nm wavelength were −2 V (resp. −0.3 V) in the upper (resp. lower) arm to set the E/O switch to the “on-state” for T11 (see Fig. 8(a)) and T22 (see Fig. 8(c)), (resp. “off-state” for T12 and T21), and −0.8 V (resp. −1.5 V) in the upper (resp. lower) arm to set the E/O switch to the “off-state” for T11 (see Fig. 8(b)), and T22 (see Fig. 8(d)), (resp. “on-state” for T12 and T21). Optimum biases can be found for any wavelength from 1510 to 1560 nm within the grating coupler transmission range. The switch exhibits an “on-off-ratio” >10 dB for all port combinations across an approximately 40 nm-wide wavelength range. Extending further the optical would require an alternative 2 × 2 directional coupler design [19] at the expense of reduced fabrication tolerances.
Fig. 8. Transfer function of the symmetric MZI DC voltages, obtained at (a) input port 1-output port 1, (b) input port 1- output port 2, (c) input port 2-output port 2, (d) input port 2-output port 1.
To fully assess the modulation efficiency, VπLπ, of the silicon E/O switch, an asymmetric version has been characterized. The DC E/O characterization results shown in Figs. 9(a)-(d) and Figs. 10(a) and 10(b) demonstrate the state-of-the-art modulation efficiency of the optical switch based on a vertical pn junction. Namely, starting from + 0.5 V, the VπLπ is 0.26 V.cm at │ΔV│=0.5 V, 0.33 V.cm at │ΔV│=1.5 V and rising up to 0.39 V.cm at│ΔV│=4 V, where the effective index change becomes less pronounced and gradually degrades the modulation efficiency up to │ΔV│=6.5 V just below the breakdown voltage at −7 V. This corresponds to a pn junction saturation effect, i.e. when the charge carriers reach the Si/SiO2 interface as the pn junction is gradually depleted.
Fig. 9. Transfer function of the asymmetric MZI with 100 GHz channel spacing for varying DC voltages at (a) input port 1-output port 1, (b) input port 1-output port 2, (c) input port 2-output port 2, (d) input port 2-output port 1.
Fig. 10. (a) Effective index change vs applied voltage variations and (b) figure of merit (VπLπ) for varying applied voltages for the four I/O ports combinations.
To provide evidence of this saturation effect, we have performed secondary ion mass spectroscopy (SIMS) measurements after the rapid thermal annealing process (see Fig. 11). In the case of the vertical pn junction (compared to the lateral pn junction), SIMS measurement are very informative since they provide its exact location, which is critical to predict the modulation efficiency by fitting the results with those obtained from Athena (Silvaco).
Fig. 11. Secondary ion mass spectroscopy (SIMS) measurements of the vertical pn junction after RTA 1000 °C for 10s vs theoretical modelling using Pearson distribution and fully coupled diffusion model including interstitial damage caused by the implanted impurities.
The implantation simulations were performed using the Pearson distribution models for each species (P and BF3). The rapid thermal annealing (RTA) consisting of a 20 °C/s ramp up from 750 °C to 1000 °C, sustained for 10s and ramp down to 750 °C at 20 °C/s, was simulated using a fully coupled model including enhanced diffusion via interstitial damage produced by the implantation processes. Although ion implantation models can accurately be fitted to the actual ones with few iterations, diffusion processes are much more sensitive. A good fit of the implantation profiles after RTA allows the pn junction behavior to be accurately predicted. So as to prove the accuracy of the modeling, we intend to provide an explanation for the pn junction saturation observed in Figs. 5 and 10.
Figures 12(a)-(f) show the contour plots of the DC simulations based on the experimental implant profile curve fittings (see Fig. 11) whereas Figs. 13(a)-(c) translate the contour plots in quantitative data.
Fig. 12. Simulation results of real refractive index change (Δn(x,y)) for varying DC voltage variations │ΔV│= (a) 0.5 V, (b) 1.5 V, (c) 2.5 V, (d) 3.5 V, (e) 4.5 V and (f) 6.5 V. The effective index change saturation can be observed qualitatively comparing the contour plots (e) and (b).
Figure 13(a) demonstrates the very good agreement between the calculated effective index change versus experimental data. The saturation effect occurring at │ΔV│=4.5 V is caused to the Si/SiO2 interface which prevents the depletion region from expending further on the positive charge side (holes). Since thermal equilibrium (DC) implies overall charge neutrality within the depletion region [39], if it cannot expands further on the p-side, neither can it on the n-side and consequently saturation occurs. It is worth noting that the doping concentration chosen here are close to the minimum values that allowed us to minimize the saturation effect. The use of lower doping concentrations would have caused the depletion width to expand more for increasing voltage and the saturation point to be reached more quickly. For this reason, the use of a longer-lower doped (versus a shorter-higher doped) device was discarded due to the height restrictions inherent to the thin 220 nm silicon epilayer. Figures 13(b) and 13(c) show the phase shifter loss and modulation efficiency versus applied varying voltage. Again here, theoretical and experimental data are in good agreement, although theoretical losses are slightly higher than experimental ones which were extracted from cut-back measurements of four straight phase shifters under varying applied voltages from + 0.5 to 6 V. The slight differences might come from sidewall roughness and small variations in doping concentrations, although the theoretical loss values lie well within the interval of confidence. Looking back at Fig. 8, the fiber-to-fiber total loss lies around 20.5 dB. Based on the experimental measurements we may determine the different source of losses. Namely, 0.6 dB account for the MMI losses, 1.2 dB and 0.8 dB come again from the 100 um rib 90° bend and 60° bend losses, respectively [28], 9 dB from the I/O grating couplers, 0.2 dB from the 12 µm to 400 nm tapers, 0.45 dB from the standard passive rib waveguides (2 dB/cm), and finally 8.25 dB (1.25mm*6.6 dB/mm at −2 V DC) come from the upper and lower phase shifters when reverse biased to switch on the device by achieving maximum transmission (“1”).
Fig. 13. Theoretical vs experimental data of (a) effective index change vs applied voltage variations, (b) phase shifter losses vs applied voltage and (c) VπLπ (modulation efficiency) vs applied voltage variations.
5.2 High speed characterization
Following the same procedure as in section 4.2, the silicon switches were E/O characterized with high speed, low voltage RF electrical signals at 1540 nm wavelength. First, to assess the maximum speed at which the switches can operate, 231−1 PRBS (pseudo-random bit sequence) signals at 0.5 Gb/s and 1.25Gb/s, were directly applied to the switch in a push-pull configuration under 0.6 Vpp and 1.2 Vpp drive voltages with applied biased of Vbias,low=−1.4 V and Vbias,up=−0.9 V in the lower and upper arms, respectively. The resulting extrema AC voltage combinations [Vmax,up,Vmin,down] and [Vmin,up,Vmax,down] with 1.2Vpp swing applied on each arm in a push-pull fashion are [−2 V,−0.3 V] (“bar-state”) and [−0.8 V, −1.5 V] (“cross-state”), which correspond to the DC voltage combinations used to achieve all four static states of the 2 × 2 switch. For 0.6Vpp AC voltage, the voltage swing combinations are [−1.7 V,−0.6 V] and [−1.1 V,−1.2 V] for the “cross”- and “bar”-states, respectively.
The eye diagrams shown in Fig. 14 illustrate the very good performance of the switch in terms of extinction ratio versus drive voltage. Indeed, in a push-pull configuration (±1.2Vpp applied in each arm) at 0.5 Gb/s and 1.25 Gb/s the extinction ratios reach 14.8 dB to 17.5 dB, and 8.6 to 9.5 dB, respectively. Moreover, with even lower drive voltages (±1.2 Vpp applied to each arm), the extinction ratios reach 10.7 dB to 14.5 dB, and 6.6 to 8.9 dB, respectively. The significant decrease of the extinction ratios at 1.25Gbps arise from the limited E/O bandwidth of the switch as shown by the small signal characterization results (see Fig. 15). According to Fig. 15(a), the 3 dB E/O roll-off bandwidth is 0.54 GHz, corresponding to a rise/fall time of trise,fall=0.35/BW = 0.35/0.54 = 648 ps [40] which is consistent with the average measured value on the oscilloscope of ≈700-750ps on average (see Figs. 14(a)-(d)). At lower voltages (0.6 Vpp) (see Figs. 14(i)-(l)), the rise and fall times increase significantly (≈1055 ps) due to the increased capacitance of the pn junction at lower voltages.
Fig. 14. Eye diagrams at λ=1540nm in all four possible states (T11, T12, T22, T21) of the silicon E/O switch driven in a push pull configuration under 1.2Vpp at 0.5Gb/s (a) T11, (b) T12 (c) T22, (d) T21 and 1.25Gb/s (e) T11, (f) T12 (g) T22, (h) T21 and 0.6Vpp at 0.5Gb/s (i) T11, (j) T12, (k) T22, (l) T21 and 1.25Gb/s (m) T11, (n) T12, (o) T22 and (p) T21.
Fig. 15. (a) S21 (transmission) and (b) S11 (reflection) E/O scattering parameters of the silicon switch measured with RF push-pull voltages of 1.2Vpp in each arm. The 3dB cut-off E/O bandwidth is 0.54GHz. S11 measurements show low RF signal reflections beyond 0.5GHz. This justifies the use of low power drive signals to minimize the amplitude of the reflected signal below 0.5GHz.
The measured transient parameters (sub-ns) of our devices are still better than what carrier injection devices can achieve (usually a few ns), but do not reflect the full potential of the pn junction in terms of speed. Forward biased p-i-n diode-based devices are indeed more efficient, easier to fabricate and more compact than their reversed-biased pn junction-based counterparts, however, it is worth noting that this E/O bandwidth limitation is not intrinsic to the pn junction itself but rather due three factors: firstly, in a lumped electrode configuration, the phase shifter acts as a large capacitor, secondly additional RC parasitics are likely caused by the three metal layers and thirdly, the use of resistive TiN as a diffusion barrier and as metal 1 is also likely to induce additional resistance and RF loss. The respective contribution of each of these effects is out of the scope of this paper and could straightforwardly be tackled using more “RF-friendly” electrodes by removing TiN and using less metal layers among others. These hypotheses are strengthened by the results obtained in the rapid prototyping phase where sub 60 ps rise and fall time were obtained with only one Ti/AlCu metal layer. Reducing further the pn junction width down to around 1.2 µm and embedding it in a travelling wave electrode configuration would enable rise and fall times to be as fast as 15 ps, making the device readily compatible with >25 Gb/s transmission speed.
Additionally, the silicon E/O switch was characterized in a system-like scenario, where a 40 Gb/s optical signal modulated by an external lithium niobate amplitude modulator (Coedon) is sent into the device, which routes the signal from one port the complementary one in a static fashion. The 40Gbps E/O modulated signal is provided by the bit pattern generator (SHF BPG 44E). As can be seen in Figs. 16(a)-(d) the 40 Gb/s eye diagrams exhibit no degradation compared to the back-to-back measurement (see Fig. 16(e)). Bit error rate (SHF EA 44) measurements confirm that the E/O switch readily maintains the signal integrity with negligible power penalties varying from 0.1 dB to 0.4 dB at a BER = 10−12 (defined here as error-free operation) and 10−9, respectively.
Fig. 16. 40Gbps eye diagrams after transmission through all four I/O combinations (a) T11 (b) T12 (c) T22 (d) T21 of the E/O switch and (e) back-to-back (w/o DUT), (f) experimental bit error rate vs received power.
To assess the switch performance in dynamic conditions, we used an arbitrary waveform generator (Keysight-N6030A, 1.25 GS/s) to generate square waves with 50% duty cycle, driving the switch in a push-pull configuration with 1.2 Vpp and 0.6 Vpp. The E/O switch is fed with a 40 Gb/s optical signal to produce short optical data packets of 4 ns (f = 125 MHz) and 1.85 ns (f = 300 MHz) duration alternately egressing from each one of the output ports. Figure 17 illustrates the very good symmetry between the complementary output ports as well as the high extinction or “on-off” ratio even at very low drive voltages. With a 1.2Vpp push-pull drive voltage, the extinction ratio values readily exceed 20 dB (resp. >15 dB) at f = 125 MHz (resp. f = 300 MHz) or optical packet duration of 4 ns (1.85 ns). Interestingly no noticeable degradation of the switching performance is observed when driving the E/O switch in a push-pull configuration with a 0.6 Vpp swing voltage. It is worth noting that the oscilloscope was calibrated before performing the experiment. Even so, performing an accurate measurement of the extinction ratio beyond 20 dB is challenging due to noise produced by the spontaneous emission of the erbium-doped fiber amplifier (EDFA). Anyhow, measuring such high extinction ratio values at very low drive voltages is an achievement and is sufficient for most switching applications. The rising and falling edges at f = 300 MHz (pulses of 1.85 ns duration) seem to degrade slightly despite the sufficient E/O bandwidth of the switch. This is actually due to the limited resolution of the AWG itself which struggled to provide square-shaped waveforms above 250 MHz.
Fig. 17. Output optical packets of 4ns and 1.85ns durations, respectively encoded with 40 Gb/s data in all four possible switching states (T11, T12, T22, T21) in a push-pull configuration with 1.2 Vpp (a), (b), (c), (d), (f), (j), (h) and 0.6Vpp (i), (j), (k), (l), (m), (n), (o), (p) drive voltages.
Finally, the power consumption of the 2 × 2 silicon switch can be estimated for both voltage swings (1.2 Vpp and 0.6 Vpp). Here, it must be noted that the switch is consuming power in both “bar”-“cross” and “cross”-“bar” transitions due to the use of a push-pull driving scheme. The capacitance values, which were extracted from the fitting between experimental and simulated values from Atlas via small signal analysis are 4.94 pF (resp. 4.81 pF) in the “bar”-state,T11 and 4.8 pF (resp. 4.7 pF) in the “cross”-state,T12 for a swing voltage of 1.2 Vpp (resp. 0.6 Vpp). The same holds for the complementary “bar” and “cross”-states (T22) and (T12). The energy accumulated in the capacitance via the DC bias supply is in principle fully recoverable when switching it off [41]. Therefore, we do not account for the DC contribution in the overall power consumption.
In real-world applications, each individual device would not need to switch from one state to the other (among the four possible transitions “bar”- “bar”, “bar”- “cross”,” cross”- “cross” and “cross”- “bar”) at each clock cycle as actually occurs in Fig. 17 (which increases the overall power consumption) but rather randomly. Therefore, we can assume that there is a 25% probability of being in one of the four possible transitions at each clock cycle. Among the four possible transitions, two out of four, “bar”- “cross” and “cross”- “bar”, consume energy, and are denoted here Eb-c and Ec-b, respectively. The average consumed energy per switching event is therefore:
As opposed to thermo-optical switches, the total power consumption will depend on the switching rate or, in other words, the optical packet duration, Tpacket, as: The power consumption of thermo-optical devices is typically in the mW-range while the maximum operation speed is limited to the µs-range [7]. In our case, the power consumption would drastically be reduced down to the µW-range if optical packet duration were in the µs-range. For faster operation speed, the power consumption naturally increases, however, even in the worst-case scenario, where the device is forced to switch states as fast as enabled by its intrinsic rise/fall falling edges (see Fig. 14), the power consumption still remains in the mW or sub-mW-range.It is important to understand here that the function of switches differ from that of modulators. The energy per bit is the common figure of merit in modulators where the term bit accounts for the maximum data rate that can be modulated [29,41]. However, for switches, the energy per bit metric is calculated by considering the maximum date rate of the optical signal that can be routed through the device [42,43], which is actually not directly related to the switching time but rather to the optical bandwidth of the switch. In our experiment, we have demonstrated a bit rate of 40 Gb/s across the switch, hence, the energy per bit of switched data considering 1.2 Vpp and 0.6 Vpp swing voltages is:
It is worth noting that a faster switching time (which is achieved with a higher voltage swing) yield more energy per bit of switched data. Conversely, by halving the voltage, the energy per bit of switched data drops by a factor of 6.5. It is also important to remark that higher data rates could be supported by our device, which would also give rise to lower energy per bit values. Overall, the obtained values of our carrier depletion switch compares favorably with other stand-alone switches such as carrier injection [15,19] or thermo-optical devices [7,11]. Clearly, whereas ms to µs-range switches based on micro- microelectromechanical systems (MEMS) [13] or thermo-optical effects [7,11] may be more suitable for circuit switching applications in high capacity core networks (where switching energy targets are not very challenging), several-ns [15,19] and sub-ns (this work) range switches find applications in short packet routing [44] (with much more challenging switching energy targets), which is the natural evolution of high capacity data networks [45].
6. Conclusion
Overall, we have shown that carrier depletion switches featuring moderately to highly doped junctions with peak concentration reaching 4.5.1018 cm−2 (BF2) and 3.5.1018 cm−2 (P) are serious candidates to address low voltage and low power switching and modulation for low power data center communications. This is primarily due to the high efficiency (≈0.26 V.cm at │ΔV│=0.5 V) achieved in this doping concentration span. The pn junction saturation that occurred with the early-prototype devices arise from of our fabrication process limitations but has been shown to be readily overcome in a large volume CMOS foundry where mask-to-mask alignment accuracy of industrial “i-line” lithography steppers is one order of magnitude higher (±100 nm) than that routinely guaranteed in our academic foundry (±1 µm). Further process improvements for rapid prototyping include the use of high-speed 100 keV electron-beam lithography for the critical steps with high alignment accuracy (±100 nm) and ultra-high resolution (50-100 nm), better control of the impurity diffusion process during the rapid-thermal annealing step since it has been shown that decreasing the annealing duration from 15s down to 10s maintains the pn junction integrity and location and displaces the pn junction saturation problem at higher voltages. Despite the inherent loss-efficiency trade-off [46] of highly-doped carrier depletion devices, which limits their scalability for larger switching matrices, they could readily be used as a single or an array of 1 × 1 push-pull modulators for low power transceivers applications driven by advanced 16 nm (or lower) FinFeT ASICs with a maximum core voltage of 0.8 V.
Funding
European Commission (318240, 67155, 688544); Ministerio de Economía y Competitividad (TEC2016-76849); Generalitat Valenciana (PROMETEO/2019/123).
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