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Abstract
High-power and reliable GaN-based vertical light-emitting diodes (V-LEDs) on 4-inch silicon substrate were fabricated and characterized in this article. The metallization scheme reliability was improved by depositing the Pt/Ti films that surround the compressed Ag/TiW films to protect it from environmental humidity. We demonstrated that although current crowding in V-LEDs was not as severe as that in lateral light-emitting diodes (L-LEDs), high current density around the opaque metal n-electrode in V-LEDs remained a problem. A SiO2 current blocking layer (CBL) was incorporated in V-LEDs to modify the current distribution. Roughening the emitting surface of V-LEDs with KOH and H3PO4 etchant was compared and the influence of surface roughening on the emission property of V-LEDs was studied. The high-power V-LEDs showed low forward voltage with small series resistance and high light output power (LOP) without saturation up to 1300 mA. Under 350 mA injection current, V-LEDs achieved an excellent light output power (LOP) of 501 mW with the peak emission wavelength at 453 nm. The prominent output performance of V-LEDs demonstrated in this work confirmed that integrating the optimized metallization scheme, SiO2 CBL and surface texturing by KOH wet etching is an effective approach to higher performance V-LEDs.
© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
With the advantages of high efficiency, longevity, high color-rendering index and adjustable emission wavelength varying from deep ultraviolet to yellow, GaN-based light-emitting diodes (LEDs) have become an appealing candidate for next-generation solid-state lighting (SSL) [1,2]. It is widely accepted that GaN-based LEDs have great potentials in high-value illumination applications, such as full-color displays, high dynamic range liquid-crystal displays, visible-light communication, water purification and disinfection, and biomedical instrumentation [3,4]. However, although the efficiency of GaN-based LEDs has been largely promoted in past few decades, mainly through improving the quality of the active layer and boosting the light extraction efficiency (LEE) [5–9], further pursuing on high-power and high-efficiency GaN-based LEDs with low-cost is necessary to penetrate conventional lighting markets [10].
Vertical LEDs (V-LEDs) are considered much suitable for future high-power and high-efficiency lighting devices with a superior device architecture [11,12]. First, V-LEDs have larger emitting area without the shielding by top p-electrode and the loss of active layer for n-contact compared with conventional lateral LEDs (L-LEDs) [13,14]. Second, transferring the LED epilayers from sapphire substrate to a better heat conductive substrate in V-LEDs improves the heat dissipation ability [15]. Lastly, the emitting surface of V-LEDs can be easily roughened with N-polar GaN exposed by cost-effective wet chemical etching for high light-extraction efficiency (LEE) [16]. However, there are still a series of problems in V-LEDs that restrict the performance and reliability of V-LEDs, such as the metallization scheme, p-type metallic reflector, current crowding and surface roughening.
In this work, we demonstrated the fabrication process for high-power and reliable V-LEDs. Au-In bonding technique with the advantages of low temperature bonding and high working temperature was used to join the LED and 4-inch silicon (Si) wafer together. We investigated and evaluated the metallization scheme quality using transmission electron microscopy (TEM) combined with energy dispersive X-ray (EDX) spectroscopy and X-ray photoelectron spectroscopy (XPS). To obtain reliable metallization scheme for the long-term stability of V-LEDs, we proposed that depositing the Pt/Ti film around the compressed Ag/TiW film to protect it from environmentally assisted fracture. Current crowding around n-electrode in V-LEDs was numerically investigated and a SiO2 current blocking layer (CBL) was incorporated to mitigate the current crowding. Finally, the influence of surface roughening by wet chemical etching on the emission property of V-LEDs was studied by finite difference time domain (FDTD) method.
2. Experimental
Figure 1 shows the fabrication process of V-LEDs. The V-LED epilayers were grown on 4-inch c-plane hemispherical patterned sapphire substrate (PSS) using metal-organic chemical vapor deposition (MOCVD) method. LED epitaxial structures consisted of a 30-nm-thick low-temperature GaN nucleation layer, a 2.5-μm-thick undoped GaN buffer layer, a 3.0-μm-thick n-GaN layer, a 200-nm-thick InGaN/GaN superlattice as strain release layer, a 12-pair InGaN (3 nm)/GaN (10 nm) multiple quantum wells (MQWs) active region, a 48-nm-thick p-AlGaN/GaN superlattice electron blocking layer, and a 110-nm-thick Mg-doped p-GaN layer. After the MOCVD process, inductively coupled plasma (ICP) etching was used to create channels for electric isolation. A square mesa structure with size of 1 mm × 1 mm was defined after the ICP etching. A SiO2 CBL (80 nm) was deposited by plasma enhanced chemical vapor deposition (PECVD) on the entire p-GaN and then patterned with a width of 15 μm by a combination of photolithographic and BOE wet-etching processes. A 100-nm-thick Ag film was deposited on the p-GaN as metal reflector by ion beam sputtering system under a base pressure of 5 × 10−5 Torr. To enhance the thermal stability of Ag-based Ohmic contacts [17,18], TiW alloys as diffusion barrier were deposited onto Ag film by sputtering with an Ar pressure of 5 × 10−5 Torr. 5-pair Pt/Ti capping layers were subsequently deposited on the TiW alloys by electron beam deposition. Rapid thermal annealing at 600°C to promote the Ag/GaN Ohmic contact was performed after the deposition of Pt/Ti capping layers. Ti/Pt/Au multilayers were deposited on the p-Si wafer and Ti/Pt capping layers respectively to ensure good Ohmic contact with the p-Si wafer after bonding. This was followed by the thermal evaporation of bonding layer, a 2.5-μm-thick In layer, onto the p-Si wafer. After completing the above processes, the whole LED wafer was bonded to the p-Si wafer by thermal compression at 230°C. Laser lift-off (LLO) process using a 248 nm KrF excimer laser was performed to separate the sapphire substrate from the GaN epilayers and expose the undoped GaN layer, and the undoped GaN layer was removed to expose n-GaN surface through the following inductively coupled plasma (ICP) etching process. The LEDs were then dipped into KOH or H3PO4 solution to texture the n-GaN surface for improving light extraction efficiency (LEE). Finally, Cr/Pt/Au multilayers were deposited on the textured n-GaN surface and the backside of p-Si wafer respectively to form the p- and n- electrodes. The n-contact fingers were set to have a width of 12 μm. Figure 1(i) showed the photograph of fabricated V-LEDs on 4-inch Si wafer. The colorful patterns observed in the photograph was due to thin-film interference effect. L-LEDs with the same mesa size were fabricated and characterized for comparison. The detailed fabrication process of L-LEDs can be found in our previous work [9].
Fig. 1 Schematic illustration of the fabrication process of V-LEDs: (a) MOCVD growth of LED epitaxial layers; (b) Defining the SiO2 CBL; (c) Deposition of the metallization scheme and bonding to a Si wafer; (d) LLO to separate the sapphire substrate from the GaN epilayers; (e) ICP etching to expose the n-GaN layer; (f) Deposition of p- and n- electrodes. (g) SEM image of the exposed n-GaN surface with hemispherical dimples after LLO and ICP etching. (h) Cross-section SEM image of V-LEDs bonded on Si wafer. (i) Photograph of fabricated V-LEDs on 4-inch Si wafer.
3. Results and discussion
To investigated the quality of metallization scheme, TEM combined with EDX spectroscopy analysis was carried out. Figure 2(a) shows the cross-section TEM image of the V-LED. The vertical lines marked as L1 and L2 in the TEM image denoted the bonding interface and protective layers, respectively. EDX line scanning was performed along the vertical lines to obtain the elemental concentration profile. Figure 2(b) shows the EDX line scanning result along L1. Except for acting as an adhesion layer to the p-Si wafer, the Ti film also effectively functioned as barrier layer against Pt penetration and subsequent Au/Si interaction according to the elemental concentration profile. While there was O concentration peak at the Si/Ti interface, the passivating effect on Si/Ti Ohmic contact by interfacial oxides was negligible here. The proposed explanation is that the Ti can react with the oxide forming Ti oxides plus silicon and possibly Ti silicide [19], which permitted reasonably intimate contact between the Ti and Si as indicated in Fig. 2(b). The intermixing of Ti and Si removed the passivating effect of the Si-O bonding or the fixed oxide charge, resulting in a low Schottky barrier height. According to Fig. 2(c), the atomic ratio of Au/In in the bonding layer was about 1/1.87, suggesting that the bonding layer formed by the solid-liquid interdiffusion was a mixture of AuIn and AuIn2 [20]. Since the bonding was achieved at 230°C, far below the melting point of the final alloy (about 456°C), the residual stresses that form upon cooling of the bonding structure to room temperature will be smaller. The Ag concentration steadily kept at over 90% for about 80 nm along the scanning path and declined steeply at the Ag/TiW interface, demonstrating that a high-purity Ag reflective layer was preserved by the TiW barrier layer. To investigate the possible band bending at the Ag/GaN interface caused by interface states, XPS measurement was carried out and discussed below. Figure 3 shows the XPS Ga 3d core level spectra obtained from the interface region of Ag/p-GaN before and after thermal annealing at 600 °C. Thermal annealing treatment caused the Ga 3d core level shifts toward the lower binding-energy side by 0.15 eV, which revealed that the surface Fermi level moved toward the valence band edge after thermal annealing [21,22]. Following the reduced downward surface band bending, the Schottky barrier height between Ag and p-GaN decreased in the annealed sample, leading to a better p-type contact.
Fig. 2 (a) Cross-section TEM image of the fabricated V-LED. The red lines marked as L1 and L2 in the image denoted the EDX line scanning path. (b) The element concentration profile obtained from EDX line scanning along L1. (c) The element concentration profile obtained from EDX line scanning along L2.
Fig. 3 The XPS spectra of Ga 3d core level obtained from the interface region of Ag/p-GaN samples before and after thermal annealing.
Residual stress is generally involved in the sputter-deposited W film, which changes from compressive to tensile on increasing the working-gas pressure [23]. In our experiment, the TiW film sputter-deposited under low Ar pressure retained high compressive stress. The compressive stress was caused by the lattice expansion, which arose from incorporated energetic working gas particles (neutralized and reflected ions at the cathode) bombarding the growing films [23,24]. Such high residual compressive stress is detrimental to the reliability of TiW film. Following Griffith”s criterion, delamination occurs once the strain energy release rate exceeds the interfacial toughness [25]. However, the interfacial toughness would be deteriorated by the environmental humidity while the mechanical energy of the film remains the same, leading to the buckling and delamination of TiW film [26]. Figure 4(a) shows the optical microscope image of conventional multilayer metallization stacks without lateral protection suffering from moisture in the air. Telephone cord buckles were observed, which could be viewed as a form of environmentally assisted fracture [27]. Therefore, it is essential to protect the Ag/TiW interface from environmental humidity for the reliability of multilayer metallization scheme. In this work, we deposited the Pt/Ti capping layers surrounding the Ag/TiW films as the inset scheme illustrated in Fig. 4(b) to protect the interface from environmental humidity. After undergoing the same environment, no buckle was observed in the optical microscope image of multilayer metallization scheme with lateral protection as shown in Fig. 4(b).
Fig. 4 Optical microscope images of different metallization scheme designs suffering from moisture in the air: (a) Conventional multilayer metallization stacks without lateral protection; (b) Multilayer metallization stacks with Pt/Ti capping layers surrounding the Ag/TiW films.
Light absorption by the metal contacts is one of the optical loss sources in LEDs [28]. Photons generated around the electrodes suffer from a high risk of being shaded and absorbed by the electrodes. However, most of current is crowded in proximity of the electrodes due to the nonideal conductivity of the semiconductor layers, leading to a localization of emission around the electrode pads [29,30]. Furthermore, current crowding results in a stronger self-heating effect on the p-n junction, inducing the decrease in internal quantum efficiency (IQE) [31]. The current density distribution in the active layers of V-LEDs was theoretically studied using the commercial SimuLED software (STR, Inc.) as shown in Fig. 5(b). To illustrate the advantages of V-LEDs in current spreading, the simulation result of L-LED was also provided for comparison. For the L-LED under 350 mA injection current, the current was notably crowded around the p-contact electrode, presenting a much non-uniform current density distribution in the active region. V-LEDs under the same condition gave a relatively uniform current distribution compared to the L-LED, while current crowding around the opaque n-electrode in V-LEDs remained a problem. The current crowding around n-electrode is the result of small top n-contacts and large backside Ag-based p-contacts in V-LEDs [29], which can be mitigated through the use of a SiO2 CBL as shown in Figs. 5(b) and 5(c). V-LEDs with SiO2 CBL showed significantly reduced current density beneath the opaque n-electrode and improved current density away from the n-electrode.
Fig. 5 (a) Optical microscope images of the L-LED and V-LED. (b) Simulated current density distribution in the active layers of L-LED, V-LED and V-LED with SiO2 CBL. (c) Calculated current density profiles along the dotted line in Fig. 5(b).
Owing to the large difference between the refractive indices of GaN and air, the critical angle for light escaping from GaN into air is small, which results in a small chance for light propagating into the escape cone before being absorbed by active layers or electrodes in V-LEDs. Roughening the emitting surface of V-LEDs is an efficient method for improving LEE since the roughened surface can increase the probability of light propagating into the escape cone and scatters the light outward [28]. The advantage of V-LEDs in roughening the emitting surface lies on that their emitting surface with N-polar GaN exposed can be easily roughened in KOH or H3PO4 etchant. Figures 6(a) and 6(b) showed the roughened surface morphology of V-LEDs after wet etching using KOH or H3PO4 solution, respectively. Highly integrated surface textures consisted of periodic hemispherical dimples and hexagonal pyramids was observed after wet etching using KOH solution. The hemispherical dimples were formed after the removal of PSS by LLO process, which transfers the hemispherical dimples to the surface of LEDs [32]. KOH wet etching was then used to create irregularly distributed hexagonal pyramids structures across the whole surface, resulting in the highly integrated surface textures. For the sample with H3PO4 wet etching, the hemispherical dimples disappeared and only dodecagonal pyramid structures with a rather low density were left on the surface. To show the superior light extraction ability of V-LEDs with roughened surface, we numerically calculated and compared the far-field radiation patterns of a flat-surface L-LED and a V-LED with integrated surface textures created by KOH wet etching using FDTD method. The simulation models of L-LED and V-LED were set with the same scale and equal number of dipole sources were respectively placed in the middle of active layer. The far-field radiation pattern of flat-surface L-LED presented several discrete emission peaks with high symmetry as shown in Fig. 6(c), which arose from the interface effects within the vertical GaN cavity sandwiched between mirrors made of GaN/metal and GaN/air [33]. For the V-LED with integrated surface textures created by KOH wet etching, its far-field radiation pattern showed significantly improved radiation intensity and broader distribution. Moreover, the symmetry of far-field radiation pattern was destroyed owing to light scattering at the roughened GaN/air interface. Therefore, the simulated far-field radiation patterns clearly indicated that the roughened surface not only reduces the Fresnel reflection but also scatters the light outward with a broad distribution, which lead to improved LEE.
Fig. 6 (a) SEM image of the textured surface of V-LEDs after wet etching using KOH solution. (b) SEM image of the textured surface of V-LEDs after wet etching using H3PO4 solution. (c) Simulated far-field radiation patterns of L-LEDs. (d) Simulated far-field radiation patterns of V-LEDs with integrated surface textures created by KOH wet etching.
Figure 7(a) shows the I-V profiles of fabricated L-LEDs and V-LEDs. We can observe that the forward voltage was much smaller in the case of V-LEDs under the same injection current. For example, at an injection current of 350 mA, the forward voltages for L-LEDs and V-LEDs were 3.52 and 2.87 V, respectively. This was mainly due to that the vertical current injection path in V-LEDs has lower series resistance than that of the lateral current path. Figure 7(b) showed the measured L-I curves of L-LEDs and V-LEDs. In the low injection current region (<100 mA), the LOP of V-LEDs showed an almost linear increase tendency and was slightly higher than that of L-LEDs. At higher injection current, the LOP of L-LEDs was greatly surpassed by the LOP of V-LEDs. Moreover, the LOP of L-LEDs saturated at ~320 mA while the LOP of V-LEDs increased steadily with the increase of injection current and showed no saturation up to 1300 mA. The absence of premature LOP saturation in V-LEDs was attributed to reduced current crowding and enhanced heat dissipating compared to L-LEDs [34]. Under 350 mA injection current, V-LEDs achieved a LOP of 501 mW. In comparison, Zhang et al. reported an excellent LOP of ~450 mW at 350 mA for GaN-based blue V-LEDs on Si substrate [35]. The higher LOP demonstrated in this work confirmed that integrating the optimized metallization scheme, SiO2 CBL and surface texturing by KOH wet etching is an effective approach to higher performance V-LEDs.
Fig. 7 (a) I-V profiles of fabricated L-LEDs and V-LEDs. (b) L-I characteristics of the fabricated L-LEDs and V-LEDs.
We performed high temperature–humidity aging test to study the reliability of V-LEDs that integrate the optimized metallization scheme, SiO2 CBL and surface texturing by KOH wet etching. Two groups of V-LEDs, that adopted the metallization scheme design of Ag/TiW films with and without lateral protection as illustrated in Fig. 4, are investigated. During the aging test, V-LEDs were placed into a life-test humidity chamber and stressed under the constant condition of 85°C and 85% RH. The samples were taken out from the chamber at a series of predefined aging time for LOP measurements at 350 mA. Figure 8 shows the LOP maintenance of V-LEDs after prolonged high temperature–humidity aging test. V-LEDs adopting the metallization scheme design of Ag/TiW films with lateral protection exhibited negligible optical degradation even after an aging time of 1008 h, demonstrating a superior reliability. However, V-LEDs adopting the metallization scheme design of Ag/TiW films without lateral protection suffered a sustained degradation as aging time prolonged, which is likely the result of deteriorated Ohmic contact caused by the environmentally assisted facture of Ag/TiW films.
4. Conclusion
In conclusion, we presented our exploration for fabricating high-power and reliable V-LEDs. We demonstrated that our metallization scheme design is reasonable for application in high-power V-LEDs. Depositing the Pt/Ti protective layers surrounding the Ag/TiW films to protect the interface from environmental humidity was proposed and demonstrated an effective method. The advantages of V-LEDs in current spreading and surface roughening were demonstrated thorough a comparative study of V-LEDs and L-LEDs. High-power V-LEDs was achieved through the combination of well-designed metallization scheme, SiO2 CBL and highly integrated surface textures created by KOH wet etching.
Appendix
Figure 9 shows the typical I-V characteristics of indium-tin oxide (ITO) contact to p-GaN, Ag/TiW contact to p-GaN and Cr/Pt/Au contact to n-GaN. The linear I-V characteristics of all these contacts demonstrated the good Ohmic behaviors of p-contact and n-contact used in this work. Specific contact resistances measured using circular transfer length method (CTLM) are 1.03×10−4, 8.41×10−2 and 1.61×10−6 Ω cm2 for ITO contact to p-GaN, Ag/TiW contact to p-GaN and Cr/Pt/Au to n-GaN, respectively.
Funding
National Key R&D Program of China (2017YFB1104900); National Natural Science Foundation of China (51675386, 51775387); Hubei Province Science Fund for Distinguished Young Scholars (2018CFA091).
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