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Abstract
Total ionizing dose tolerances of current integrated circuits are limited to 3–10 kGy because semiconductor devices are fundamentally vulnerable to radiation. However, using programmable architecture, the total ionizing dose tolerances of integrated circuits can be increased if the integrated circuits can be repaired each time a permanent failure occurs. Nevertheless, current programmable devices cannot allow such repairable use because their serial programming functions fail immediately, even if only a few transistors on the devices are damaged. To increase the radiation tolerance of integrated circuits, this paper presents a proposal of a new optoelectronic programmable device with a parallel light configuration architecture instead of current field programmable gate arrays which have a serial configuration architecture. This demonstration confirms 1.9 MGy radiation tolerance on an optoelectronic programmable device using a non-radiation-hardened standard complementary metal oxide semiconductor process.
© 2017 Optical Society of America
1. Introduction
Total ionizing dose tolerances of current very large scale integrations (VLSIs) are limited to 3–10 kGy because such semiconductor devices are fundamentally vulnerable to radiation [1–5]. Actually, the latest VLSIs have over a billion transistors. The radiation tolerances of the VLSIs are estimated under the condition that even one transistor among a billion transistors is not allowed to be broken by radiation. Nevertheless, the total ionizing dose tolerances of current VLSIs can be increased if the VLSIs could accommodate radiation damage of fewer than 1 % of all transistors.
For their typical applications, programmable architectures such as field programmable gate arrays (FPGAs) and complex programmable logic devices should be used instead of custom non-programmable VLSIs [6–8]. If they were used, then each time a permanent failure occurred on VLSIs, the failure part could be detected by implementing error detection circuits. Subsequently, a new circuit having the same function that avoids failure of the programmable gate array region and which uses the rest non-failure programmable gate array region could be implemented.
Unfortunately, current programmable devices cannot accommodate such use after repair because their serial programming functions fail immediately, even if only a few transistors on the devices are damaged by radiation [9]. Since configuration circuits on programmable devices occupy 38 %–70 % of the device area and because the configuration circuit is connected serially, when a transistor is damaged, the probability that the damaged transistor is included in the configuration circuit is extremely high. Therefore, current programmable devices cannot be used as repairable VLSIs.
This paper therefore presents a proposal of a new optoelectronic programmable device with a parallel light configuration architecture instead of current field programmable gate arrays with a serial configuration architecture [10–12]. The results of this demonstration confirm 1.9 MGy radiation tolerance on the optoelectronic programmable device using a non-radiation-hardened standard complementary metal oxide semiconductor process, which is at least 190 times higher radiation tolerance than any currently available radiation-hardened VLSI.
2. Probability of permanent failure of VLSIs
Actually, VLSIs are well known to be vulnerable to radiation. With current VLSIs, even if a single transistor fails on them, the VLSI causes severe system trouble. With an integrated circuit that includes a billion transistors, the condition in which not even one transistor can ever be allowed to be broken is overly strict. That constraint must be removed because the radiation tolerances of current radiation-weak integrated circuits can be increased drastically if their operations could be sustained even after destruction of 1,000–10,000 transistors by radiation. When allowing a certain number of transistors on an integrated circuit to be damaged, the survival probability Pf for which the number of failure transistors on the integrated circuit is less than a certain number Nmax is estimated as presented below.
Therein, m is the number of transistors on the integrated circuit, n is the number of failed transistors, p stands for the failure probability of one transistor, and Nmax represents the allowable number of failure transistors on the integrated circuit. Here, mCn represents a combination. Probability Pf becomes much higher than the probabilities, estimated as (1 − p)m, of integrated circuits on which not even one transistor is allowed to be broken. Such VLSIs that can be repaired can greatly enhance radiation tolerance.3. Optically reconfigurable gate array architecture
Field programmable gate arrays (FPGAs) cannot be used as repairable VLSIs because their serial configuration functions invariably fail immediately, even if only a few transistors malfunction. Programming itself would become impossible at the onset of permanent failure. To achieve repairable VLSIs, a parallel light configuration must be used for programmable devices. After introducing such parallel light configuration architecture onto a programmable device, then even if a part of the configuration circuit is damaged by radiation, programming for the remaining non-damaged programmable gate array region can be executed correctly. To date, various optically reconfigurable gate arrays (ORGAs) which can support such a parallel light configuration have been proposed [13–18]. A fiber-remote parallel configuration [13], a multi-context parallel configuration [14], a parallel configuration architecture using a rewritable holographic memory [15], and a 65.5 ns-period high-speed parallel reconfiguration procedure [16] have been demonstrated to realize a practical multi-context high-speed reconfigurable FPGA. Based on these studies, the fastest 20 MHz high-speed scrubbing operation has been demonstrated so that the most radiation-vulnerable point of current FPGAs or a soft-error issue arising on their configuration memories was removed perfectly [17]. Moreover, optical parts on ORGAs are reportedly robust against radiation [18]. Therefore, ORGAs with such parallel configurations are useful architectures for repairable use in high-radiation environments.
3.1. Radiation-hardened optically reconfigurable gate array
To confirm the radiation tolerance of optically reconfigurable gate arrays with a parallel light configuration, an optically reconfigurable gate array with a single configuration context has been developed as presented in Fig. 1. The optically reconfigurable gate array comprises a holographic memory film (Recording IR; Agfa-Gevaert NV), a 650 nm, 5 mW semiconductor laser diode (DL-3247-165; Tottori Sanyo Electric Co. Ltd.), and an optically reconfigurable gate array VLSI fabricated using a commercial 0.18 µm standard CMOS process (Rohm Co. Ltd.). Although the basic architecture is the same as that of conventional optically reconfigurable gate arrays, to increase the radiation tolerance, a radiation-hardened semiconductor laser was selected among commercial semiconductor lasers. In addition, a new optically reconfigurable gate array VLSI using larger buffers for common clock signals and configuration control signals than those of conventional optically reconfigurable gate array VLSIs was fabricated [13–18]. The three components were constructed using a plastic plate framework. The 650 nm 5 mW semiconductor laser was mounted 50 mm distant from and over the holographic memory film. Circuit information is stored on the holographic memory film. When the semiconductor laser turns on, the configuration context is programmed onto an optically reconfigurable gate array VLSI placed 100 mm distant from the holographic memory film perfectly in parallel. The photograph is presented as Fig. 2.
Fig. 1 Block diagram of the constructed optically reconfigurable gate array system consisting of a laser, a film, and an optically reconfigurable gate array very large scale integration (VLSI).
3.2. Context recording method for holographic memory films
Currently, a logic synthesis and a place and route tools that are useful for optically reconfigurable gate arrays are not available. Therefore, in this experiment, each time a circuit is designed, the logic synthesis and place and route operations for the circuit were executed manually based on the programmable gate array architecture of the optically reconfigurable gate array VLSI. Moreover, the manually generated configuration context is converted to a two-dimensional binary configuration context pattern by following the map of photodiodes on the optically reconfigurable gate array VLSI. Here, binary state highs and binary state lows of the two-dimensional binary optical configuration context pattern are represented respectively as bright points and dark points. The manually generated two-dimensional optical configuration context is finally converted to a corresponding binary fringe pattern to be stored on a holographic memory film as shown in Fig. 3(a). Assuming that each bright point can be regarded as a delta function δ(x, y) and defining the coordinates of the i-th bright bit as xi and yi, the conversion equation is shown in the following equations as
where r1 and r2 are the following. The first term in the summation equation of Eq. 2 is a context pattern light wave. The second term is a reference beam used when reading a configuration context. The reference beam is assumed as a diffusion light. In those equations, BN stands for the number of bright bits included in a configuration context, k denotes the wavenumber of the laser beam used for reading the holographic memory, α and β are the coordinates of the holographic memory, and L and D respectively represent the distance between the holographic memory film and the chip and between the holographic memory film and the laser. After the threshold operation presented above, a binary fringe pattern is obtained. As presented in Fig. 1, in this experiment, D and L were defined respectively as 50 mm and 100 mm. The laser wavelength is 650 nm. Figure 3 shows a binary fringe pattern for the holographic memory film consisting of 1,200 × 1,200 pixels, as calculated using a personal computer. The holographic memory pattern was written in the 7.62 mm × 7.62 mm center region of the film with 4,000 dots per inch using an image setter (DTR-3100; Screen Holdings Co. Ltd.).Fig. 3 (a) Binary holographic memory pattern consisting of 1,200 × 1,200 pixels, calculated using a personal computer. (b) Photograph showing its recorded film (Recording IR; Agfa-Gevaert NV). The aperture size of the film is 34 mm × 23 mm. The 7.62 mm × 7.62 mm center region was used to record the binary holographic memory pattern. The other region was masked to opaque. The binary holographic memory pattern was recorded at 4,000 dots per inch using an image setter (DTR-3100; Screen Holdings Co. Ltd.).
3.3. Optically reconfigurable gate array VLSI
An optically reconfigurable gate array VLSI was fabricated using a non-radiation-hardened 0.18 µm standard complementary metal oxide semiconductor (CMOS) process technology. Photographs of the chip die, a configurable logic block, a configurable switching matrix, and a configurable I/O block are presented in Fig. 4. The die is 5 mm × 5 mm. The optically reconfigurable gate array VLSI has a fine-grained programmable gate array consisting of 128 logic blocks, 144 switching matrices, and 64 input–output (I/O) bits. A cell map showing the locations of the configurable logic blocks, configurable switching matrices, and configurable I/O blocks is presented in Fig. 5. The functionality is fundamentally identical to those of typical field programmable gate arrays. Each logic block consists of two 4-input look-up tables used for implementing Boolean functions and two delay-type flip-flops with a reset function. A block diagram of an optically reconfigurable logic block is presented in Fig. 6(a). In all, 60 photodiodes are used for programming an optically reconfigurable logic block. The optically reconfigurable logic block can be reconfigured perfectly in parallel. A block diagram of an optically reconfigurable switching matrix is portrayed in Fig. 6(b). Four-directional switching matrices controlled by 64 photodiodes were implemented in the gate array. In addition, the optically reconfigurable switching matrix can be reconfigured perfectly in parallel. Programming elements of all logic blocks, switching matrices, and I/O blocks of the chip are connected to 17,664 photodiodes. For that reason, the gate array can be reconfigured optically and perfectly in parallel. The photodiodes were constructed using junctions between the P-substrate and N-wells. Figure 4 shows that the photodiode was designed to 4.40 × 4.45 µm size. Horizontal and vertical spaces between photodiodes are, respectively, 30.08 µm and 30.24 µm. The total chip gate count is 8,704. The chip specifications are shown in Table 1. The new optically reconfigurable gate array VLSI has larger buffers for common clock signals and configuration control signals than those of conventional optically reconfigurable gate array VLSIs [13–18].
Fig. 4 Die photograph of the 5 mm × 5 mm optically reconfigurable gate array VLSI chip and magnified photographs of a configurable logic block, a configurable switching matrix, a configurable I/O block, and a photodiode cell.
Fig. 5 Cell map of the optically reconfigurable gate array VLSI chip showing locations of the configurable logic blocks (L), configurable switching matrices (S), and configurable I/O blocks (I).
Table 1. Summary of chip characteristics.
4. Radiation experiment
To confirm the total ionizing dose tolerance of the optically reconfigurable gate array, a gamma radiation experiment was done using a 60Co gamma radiation source at the Radio Science Research Laboratory of Shizuoka University. The radiation intensity was 3.7–4.2 kGy/h. The optically reconfigurable gate array VLSI was exposed completely to a 1.9 MGy total ionizing dose, which is a 190-times higher total-ionizing dose than the 10 kGy of Vertex-5QV. To confirm the degradation of the optically reconfigurable gate array, a 2-bit adder circuit and test circuits using a logic block and switching matrices were implemented. The initial and 1.9 MGy total ionizing dose conditions were measured.
In the 2-bit adder circuit operation, it was confirmed whether a 14.3 MHz high-speed scrubbing operation can be executed or not. The holographic memory pattern, CCD-captured configuration context pattern, and waveform of the 2-bit adder circuit are presented in Fig. 7. Consequently, the 14.3 MHz high-speed scrubbing operation could be executed at both conditions of the initial and 1.9 MGy total ionizing dose. At the initial condition, the core current of the 14.3 MHz high-speed scrubbing operation was 29.395 mA. At 1.9 MGy total ionizing dose, the core current was increased slightly to 39.68 mA. Additionally, the current of 3.3 V I/O of the optically reconfigurable gate array VLSI was increased from 1.73 mA to 4.271 mA. In addition, the propagation delay of the 2-bit adder circuit were measured using a 2 GHz 16903A Logic Analysis System including a 68 Channel 4 GHz Timing/600 MHz State Logic Analysis Module (16950A; Agilent Technologies Inc.). Control signals applied for the optically reconfigurable gate array VLSI were sent from a commercially available field programmable gate array (APEX20KC EP20K200C8; Altera Corp.). The propagation delay of the 2-bit adder circuit was increased from 11.667 ns to 20.000 ns. The currents and propagation delays of the optically reconfigurable gate array VLSI are increased slightly with increase of the total ionizing dose. However, the circuit worked correctly.
Fig. 7 Detailed deterioration analysis. Panel (a) portrays a holographic memory pattern including a 2-bit adder circuit implemented on a liquid crystal spatial light modulator. Panel (b) depicts the CCD-captured configuration context pattern. Panel (c) displays a waveform of the 2-bit adder circuit implemented on the 1.9 MGy total ionizing dose optically reconfigurable gate array VLSI. Panels (d) and (e) depict detailed deterioration analysis results of propagation delays of configurable logics (c), switching matrices (S), and I/O blocks (I).
Moreover, a detailed deterioration analysis was done for 16 configurable logic blocks, 24 switching matrices, and 8 I/O blocks on the optically reconfigurable gate array VLSI. 16 test circuits were prepared. The four test circuits, ICI0, ICI1, ICI2, and ICI3, consist of a logic block and two I/O blocks. The ICI0, ICI1, ICI2, and ICI3 were implemented individually onto different logic blocks and I/O blocks. The other four test circuits, ISCSI0, ISCSI1, ISCSI2, and ISCSI3, consist of a logic block, two switching matrices, and two I/O blocks. In the ISSCSSI0, ISSCSSI1, ISSCSSI2, and ISSCSSI3, a signal was applied to an I/O block, the I/O block received signal propagates through two switching matrices to a logic block. Then, the output signal of the logic block propagates through two switching matrices to an I/O block. Figure 7 shows that the degradations or propagation delays of the test circuits on the optically reconfigurable gate array VLSI have been confirmed at initial and 1.9 MGy total ionizing dose conditions. Even after the optically reconfigurable gate array was exposed to a 1.9 MGy total ionizing dose, the responses of logic blocks and switching matrices took 1.17–1.25 times longer than those at the initial condition. All 32 look-up tables functioned correctly. If the degradation of the programmable gate array is accepted, then the programmable gate array is useful continuously.
Although extremely low radiation tolerances must be applied to current integrated circuits that never allow even one transistor on them to be broken, the optically reconfigurable gate array VLSI is useful even after a 1.9 MGy total ionizing dose, which is at least 190 times higher radiation tolerance than those of radiation-hardened FPGAs. To date, only such degradation has been confirmed. No permanent failure has ever been confirmed. Therefore, the radiation tolerance can be estimated as a higher than 1.9 MGy total ionizing dose. When a partial region of the optically reconfigurable gate array VLSI becomes permanently broken, then the holographic memory film is replaced with another one having the same function, but it avoids damaged regions and instead uses non-damaged regions. The parallel configuration is extremely useful to increase the radiation tolerance of FPGAs.
5. Conclusion
Total ionizing dose tolerances of current integrated circuits are limited to 3–10 kGy because semiconductor devices are fundamentally vulnerable to radiation. However, using programmable architecture, the total ionizing dose tolerances of integrated circuits could be increased if the integrated circuits could be repaired each time a permanent failure occurs. Nevertheless, current programmable devices cannot allow such repairable use because their serial programming functions fail immediately, even if only a few transistors on the devices are damaged. To increase the radiation tolerance of integrated circuits, this paper has presented a proposal of a new optically reconfigurable gate array with a parallel light configuration architecture instead of current field programmable gate arrays which have a serial configuration architecture. This demonstration confirmed the achievement of at least 1.9 MGy radiation tolerance on an optically reconfigurable gate array using a non-radiation-hardened standard complementary metal oxide semiconductor process. That degree of radiation tolerance is 190 times greater than those of currently available VLSIs and FPGAs.
Funding
Initiatives for Atomic Energy Basic and Generic Strategic Research (283101); the Ministry of Education, Science, Sports and Culture, Grant-in-Aid for JSPS Research Fellow (16J12063);Grant-in-Aid for Scientific Research(B) (15H02676).
Acknowledgments
The VLSI chip in this study was fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Rohm Co. Ltd. and Toppan Printing Co. Ltd.
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