1. Introduction

Current off-chip electronic random access memories (RAM) still exhibit insufficiently long access times and limited bandwidth compared to Chip-Multiprocessors (CMP) technology processing speed, significantly decreasing overall computational power [1]. To overcome the limited throughput between powerful CPUs and slow off-chip memory units, the so called Von Neumann bottleneck, on-chip cache memory schemes were introduced at the expense of allocating up to 40% chip real-estate for caching purposes [2]. However, with processor chip size being fragmented due to cost and heat dissipation related issues [3], on-chip memory solutions counteract the exploitation of the entire processor die for accommodating more processor cores and increasing the per chip processing power. A recent study [4] has shown a possible way to relax the Von Neumann bottleneck while simultaneously releasing precious on-chip real-estate by combining optical interconnect technologies [5] and an all-optical bit-level memory configuration towards allowing off-chip, high-speed optical cache memory architectures. Moving towards the realization of such radically new architectural schemes suggests a highly challenging operational framework for optical memory technology: optical interconnects have to smoothly synergize with highly integrable and as such low-footprint and low-energy optical memory layouts that can provenly perform with true high-speed data signals and support WDM-based functional schemes.

Although several optical memory devices have been reported over the last few years underlining the potential of optical memory technology [6–11], no solution has managed to comply with the demanding requirements with respect to size, energy and high-speed data operation. Among them, devices that exploit light polarization bistability in VCSELs [6], integrated InP ring-lasers on SOI that exploit light direction bistability [7], coupled laser-based [8] and switch-based [8,9] “master-slave” configurations. Coupled switch-based layouts have been also utilized towards fully functional optical RAM cell layouts [11] that form the basic modules in practical optical cache implementations. Their potential for speed capabilities even beyond 40GHz has been confirmed at least theoretically [12], complying also with the necessary optical memory peripherals that exploit WDM [13]. Despite the RAM-functional and speed credentials of coupled switch memory layouts demonstrated so far, photonic crystal (PhC) nanocavities have become probably the dominant candidate technology when coming to size and energy metrics [14–18] and have already managed to confirm their large scale integration capabilities [17]. Optical memory devices were among the first to take advantage of this technology, with the demonstration of devices based on the InGaAsP/InP platform and relying on the bistability of PhC nanocavity lasers [15] with 60ps switch times at 70μW switching power. Alternatively, optical memory devices based on the bistability of InGaAsP/InP PhC switches [16–18] have demonstrated switching energy of 13fJ/bit and <10μm² footprint [16], coming however at a cost of a slower fall time of 7.4ns. The long fall times being in the order of nanoseconds [16] can probably promote the use of these memory implementations in buffering schemes for routing applications but can certainly not comply with the bit-level high-speed caching for compute environments. Although hybrid InP-on-Silicon photonic crystal cavities have indicated their up to 20Gb/s speed characteristics in single-rail switch and wavelength conversion setups [14], photonic crystal-based memory schemes have still not confirmed their Gb/s-scale credentials in real data traffic environments.

In this article, we report on a record low-size III-V on SOI photonic crystal nanolaser operating as SR-FF at a data repetition rate of 5Gb/s and being the first, to our knowledge, PhC nanocavity-based memory element that performs under true data traffic conditions. Its operation is based on the bistability behavior of the PhC laser during injection locking. The device relies on the heterogeneous integration of a InP-based PhC nanocavity with SOI passive waveguides circuitry, utilizing evanescent wave coupling between the 2 optical levels and enabling efficient interfacing of active nanophotonic elements densely integrated in a circuit with direct compatibility to CMOS electronics. The footprint of the device was a record 6.2μm², achieving significant reduction compared to previous PhC nanocavity-based optical memory implementations. Memory state switching-ON and switching-OFF occur at time constants lower than 50ps, indicating operation capabilities up to 20Gb/s. The memory operation of the PhC nanocavity laser SR-FF was evaluated at 5Gb/s with data patterns simulating true data traffic, revealing an extinction ratio (ER) value of 12.7dB, switching energies as low as 6.4fJ/bit and error-free operation with a negative power penalty of −0.2 dB.

2. Concept of PhC-based nanolaser flip-flop

The operation of the device as a memory element relies on exploiting the bistability behavior of the PhC laser emission state between a free-running mode (unlocked state) and an injection-controlled mode (injection-locked state), occurring when the laser is injected with a wavelength detuned external optical signal. The laser bistability is expressed by means of wavelength emission detuning that is controlled by the optical power of the injection signal. Specifically, the PhC laser is powered by an optical pump at 1180 nm perpendicular to the direction of the PhC laser beam to generate a laser output called free-running state signal, at a given wavelength shown in red color in Fig. 1(a)(i). At the presence of a wavelength detuned input injection signal, called control signal and shown in blue color in Fig. 1(a), the laser starts emitting at the injection wavelength and not at its free-running mode wavelength when the control power increases above a specific threshold. This instance can be seen in Fig. 1(a)(ii), where the laser “locks” its wavelength emission to the injection wavelength. While at this state, the laser can exhibit a certain bistability behavior for specific injection signal input powers, entering a hysteresis loop and retaining this emission state even when the injected signal optical power is decreased to a certain cut-off level. However, when the optical power of the injected signal falls below this cut-off level, the laser emission returns to its free running state. This instance is depicted in Fig. 1(a)(iii), where we can see the decrease in amplitude in the injection signal. Consequently, the laser emission output has two states – locked and unlocked –, which depend on the ascending or descending direction of the injection signal power and memory operation can be achieved when operating within the bistable range of the device.

 

Fig. 1 (a) Process of injection locking of the bistable PhC nanolaser b) Hysteresis loop of the bistable PhC laser.

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Figure 1(b) shows an indicative hysteresis loop formed by the PhC laser device for a given wavelength detuning. The laser operates as a SR flip-flop taking advantage of the three discrete areas of injection power levels shown in Fig. 1(b): i) Area I injection power levels allow for Set flip-flop operation, as the laser output is changed from free-running (unlocked) to injection-controlled (locked) state. Arrow 1 indicates this transition from the unlocked to the locked state as an effect of the sufficient power of the injected pulse. ii) Area II injection power levels enable Reset flip-flop operation as the laser output returns to the free-running (unlocked) state. Arrow 3 indicates this transition, as the injection power levels are below the cut-off level, allowing for the return of the device’s emission in the free-running wavelength. iii) Area III injection power levels cover the bistable range and enable storing operation, as the laser emission retains its previous state. In case the previous state of the device was the locked state (Area I), a reduction of the injected power in a value above the cut-off power level will keep the device in the locked state, as indicated with arrow 2. On the other hand, if the previous state of the device was the unlocked state (Area II), an increase in the injected power not sufficient for locking will keep the device in the unlocked state, as indicated with arrow 4. Based on these three injection power areas, the Set and Reset signals that drive an SR flip-flop can be simultaneously encoded on the same injection signal, as shown in Fig. 2(a). The Set signal is being represented by the high-level logical ‘1’ pulses exceeding the bias threshold and the Reset signal by reversely biased pulses that appear as logical ‘0’s and correspond to the absence of any optical power level. An offset power level of the injection signal acts as the biasing threshold and is employed to enable operation in the bistable regime so that the laser retains its state.

 

Fig. 2 (a) Representation of the SR-FF operation of the bistable PhC nanolaser, (b) SEM image of the photonic crystal nanolaser, (c) schematic view of the layers stack, (d) E_y field distribution in the hybrid structure.

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Figure 2(a) shows a schematic diagram of the injected signal covering all possible states of the SR flip-flop. When a Set pulse inputs the device, the FF enters its locked state so that no optical power exits the FF at the wavelength of its free-running emission state, corresponding to a logical ‘0’ output. When a Reset signal is being inserted, the device returns to its unlocked state emitting a high-power level and as such a logical ‘1’ at its output. Whenever the incoming signal has a power level equal to the bias threshold, the FF retains its previous state operating in its storage regime.

3. PhC nanocavity laser

The structures under investigation are InP-based 1D PhC nanobeam cavities which are heterogeneously integrated onto 500nm × 220nm (width × thickness) SOI wire waveguides. The cavities consist of 650nm × 285nm (width × thickness) InP-based wires embedding 4 InGaAsP strained quantum wells, drilled with a row of equally-sized holes (radius = 123nm). The distance between the holes is varied according to [19] in order to obtain a Gaussian field profile for the resonant mode which enables Q factors higher than 10⁴ (10⁶ in simulations) with V~(λ/n)³. The thickness of the BCB layer is 260nm. Besides energy efficiency and ultra-fast dynamics, these cavities are also particularly interesting as they exhibit the smallest footprint of all PhC cavities and because of their natural ability to be coupled efficiently with wire waveguides. The cavity is positioned on top of a SOI waveguide whose width was chosen properly to enable a coupling efficiency greater than 90%. The structures are encapsulated in SiO₂ in order to improve heat sinking as well as the robustness of the systems.

The fabrication of these InP-on-SOI hybrid nanolasers starts with the adhesive bonding using DVS-benzocyclobutene (BCB) of a 1cm² of the InP-based heterostructure grown by molecular beam epitaxy, onto an SOI die processed with waveguides into a CMOS pilot line (Epixfab). In order to set the distance between the SOI waveguides and the III-V materials to a value enabling an efficient evanescent wave coupling, the InP material is covered with a 400nm thick SiO₂ layer before the bonding. The cavities are then patterned right on top of the SOI wires [20] using electron beam lithography followed by inductively coupled plasma etching. An SEM picture of such a fabricated cavity is shown on Fig. 2(b). The etched sidewalls of the cavity are then chemically passivated using ammonium sulfide in order to reduce non radiative surface recombination of electron-hole pairs and allow CW operation of the nanolasers [21]. Finally, the sample is fully encapsulated in a 1µm-thick silica layer which decreases the overall thermal resistance of the devices and increases their robustness [22]. The total length of the device is 9.54µm, while its width is 650nm, resulting in a total footprint of 6.2μm² that is the smallest value among all PhC cavity-based optical memories reported so far. The laser was integrated with silicon photonic wire waveguides and Transverse Electric (TE) grating couplers at both input and output ends to enable fiber-to-fiber data transmission. Figure 2(d) depicts the distribution of the E_y field in the hybrid structure, obtained using 3D finite different time domain calculations.

4. Experimental setup

The experimental setup used for evaluating the nanolaser as a SR-FF is shown in Fig. 3. The device was powered with an optical pump signal at 1180 nm, which was injected vertically to the nanolaser using a 10x microscope objective, so as to adjust aperture and enhance the absorption of the pump signal. We chose to set the pump power at 103.5µW corresponding to 4.5 times the laser threshold. This value refers to the estimated absorbed pump power in the quantum wells. For the generation of optical input signal that encodes the Set and Reset signals of the SR Flip-Flop, two individual lasers emitting light at λ1 = 1552.15 nm (Injection signal) and λ2 = 1557.71 nm, respectively, were modulated by custom patterns at 5Gb/s Non-Return-to-Zero line-rate in a Ti:LiNbO₃ Mach-Zehnder modulator, as can be seen in Fig. 3. These custom patterns was programmed appropriately, so as to evaluate its performance in fast memory state switching at a 5GHz repetition rate employing a PRBS-resembling 5Gb/s data stream and also induce long periods of ‘1’ or ‘0’ to demonstrate the device’s capability for long memory state holding. The two signals were then injected into a Semiconductor Optical Amplifier (SOA) which acts as a gating element, with λ2 being the stronger one and as such acting as the SOA Control signal, inducing a Cross Gain Modulation(XGM) process in the SOA and reducing its gain. Consequently, the amplitude of any Injection signal pulse that coincides in the SOA with a Control signal pulse is reduced. The pulses with reduced amplitude act as the bias signal that maintains the memory state of the device. The Control signal was specifically programmed and synchronized to coincide with specific parts of the Injection signal and produce bias pulses in the desired positions that prove the fast response and long memory state holding of the proposed device. The ratio between the amplitude of the unaffected Injection signal pulses and the suppressed bias pulses was set to follow the hysteresis loop of the device. This amplitude ratio was properly adjusted through the optical power of both input signals of the SOA. An optical bandpass filter with a 3-dB bandwidth of 1nm was used the output of the SOA to select only the Injection Signal at λ1. Variable Optical Attenuators (VOA) and Polarization Controllers (PC) were employed to ensure proper signal input powers and to compensate for the SOA’s polarization gain dependence.

 

Fig. 3 Experimental setup.

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The PhC injection signal – now consisting of three levels, corresponding to Set, Reset and Bias- was then launched into the SOI motherboard through the input grating coupler (GC1) and into the bistable photonic crystal nanolaser. Again, a polarization controller was employed to compensate for the polarization dependence of the grating coupler, while a VOA sufficiently attenuated the signal. The output signal of the bistable photonic crystal was then received at the output grating coupler (GC2). Lensed fibers with a spot size diameter of 5μm and anti-reflection coatings were used for injecting and collecting light at both grating couplers. The coupling loss between the lensed fibers and and each of the grating couplers was 7dB. The output signal was then filtered in a bandpass filter with a 3-dB bandwidth of 0.02nm centered at the laser’s free-running mode wavelength prior to being amplified through an Erbium Doped Fiber Amplifier (EDFA) and recorded at a sampling oscilloscope. Finally, an Error Detector was used for performing Bit Error Rate (BER) measurements.

5. Experimental results

Successful experimental demonstration of the PhC-based laser operating as a SR Flip-Flop was achieved for several data patterns. Figure 4 a and b) show experimentally obtained data traces at the a) input and b) output of the Flip Flop confirming the successful SR-FF operation at 5Gb/s. Figure 4a) shows the input signal as obtained at the output of the SOA with three logical levels, the logical one, bias and the logical zero imprinted at 1552.15nm. Figure 4b) shows the final FF memory content as it is imprinted in the lasing wavelength at 1551.75nm. When a bit of logical ‘1’ Set signal is injected into the PhC laser, the FF enters its locked state, resulting in a logical ‘0’ state the output of the FF. When a bit of logical “0” Reset pulse is inserted into the laser, it unblocks the free-running transmission state and the laser is switched back to its initial state of logical ‘1’. In case of a bias pulse, the FF memory content remains unaltered retaining its last value. This situation is evident in the bias pulses that are highlighted with blue color in Fig. 4a and b), depicting four different cases of memory operation provided by the PhC laser: the first highlighted area depicts two Bias pulses following a Set pulse resulting in a logical zero state for three consecutive bit slots at the FF output, as shown in Fig. 4b). The second highlighted area presents three Bias pulses after a single Reset pulse that result in logical one state for four bits at the output of the FF as shown in Fig. 4b). The third and the fourth highlighted areas show the retention time of the FF memory after one Set and seven Reset pulses. Successful memory operation is observed in both cases in Fig. 4b) where memory output stays constant to a logical zero state for a duration of 8 bits, approximately 1.6ns, and to a logical one state for 15 bits corresponding to a memory time duration of 3ns, respectively. Figure 4 c and d) illustrate the rise and fall times of the FF output pulses with 10%-to-90% values being approximately 50ps. Figure 4 (g) shows the BER curves obtained for the PhC-based SR Flip Flop operation at 5GHz. Back-to-Back (B2B) measurement was obtained by using the same custom-made 127-bit pattern, employed to demonstrate FF operation, transmitted through the system without entering the PhC-based laser, with no bias level.

 

Fig. 4 a) Input pulse trace with three logical levels (logical one, bias, logical zero) inserted into the PhC-based SR-FF, b) Output pulse trace obtained at the exit of the SR-FF, c) Rising and d) Falling time of the FF output pulses, e) Set/Reset/Bias eye diagram, f) SR-FF output eye diagram, g) BER curves for PhC-based SR-FF operation at 5Gb/s.

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Error free operation at 10⁻⁹ BER was achieved for the FF device at 5GHz revealing a negative power penalty of −0.2dB. The regenerative properties of the demonstrated laser device are mainly due to the improvement of noise in the“0” level, induced by the SOA used to construct the Set/Reset signal. Figures 4(e) and (f) depict the eye diagrams for the Set/Reset signal and the SR-FF output -corresponding to the BER curve- respectively, providing a more detailed look into the performance of the demonstrated device. Clear open eye diagram is obtained for the SR-FF operation at 5GHz with an ER of 12.7dB and an Amplitude Modulation (AM) equal to 1dB. The input eye diagram exhibits three logical levels corresponding to the three logical states, the logical one, the bias and the logical zero level as shown in the right inset and corresponds to an ER of 11.7dB and an AM of 0.8dB. The average optical bias power was 8μW, the input optical power was measured to be 20μW and the average output power of the laser was 19.9μW taking into account the grating coupler losses in both cases. In the absence of any input signal, the laser emission was 34.6μW. To this end, memory operation was achieved with a switching energy of 6.4fJ/bit at 5GHz at the pump power of 103.5μW, for a given memory output ER of 12.7dB, with the sum of the Injection and Bias peak powers being 32μW. The device was also examined in terms of maximum memory holding time and was found to achieve continuous operation with a memory state holding time of 2s [23].

6. Conclusion

We presented, for the first time to our knowledge, an InP-on-Silicon PhC-based nanolaser performing as a SR-FF at a true data rate of 5Gb/s. The device was tested with PRBS-resembling data patterns revealing 10⁻⁹ error free operation with −0.2dB power penalty. The presented PhC laser device exhibits the smallest size among all PhC cavity-based optical memory implementations with a total footprint of 6.2μm², raising expectations for densely integrated optical memories. The device also exhibits ultra-fast dynamics and excellent energy efficiency, demonstrating switching times of <50ps for switching energy of 6.4fJ/bit, indicating operational capability in the order of 20Gb/s.