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This paper presents optimized design and measurement results for a low-loss broadband vertical interlayer transition (VIT) device located between lower and upper Si nano-photonic waveguides. The device comprises the lower c-Si taper, the upper a-Si:H taper, and a wide and thin SiON secondary core with a 0.6-μm-thick SiO2 interlayer. The device structure facilitates the low loss VIT, giving insertion losses of 0.87 and 0.79 dB for quasi-TE and TM modes, respectively, at 1550 nm. Also, the evanescent coupling nature of the VIT device renders it wavelength- and polarization-insensitive, leading to loss variation of within 0.5 dB in the C-band.
© 2015 Optical Society of America
1. Introduction
Three-dimensional (3D) photonic integrated circuits (PICs) would obviously be advantageous in the way that they could greatly enhance scalability in terms of integration density, make it relatively straightforward to fabricate a low-crosstalk waveguide crossing, and provide greater flexibility for the layout and design of photonic circuits [1,2]. In particular, 3D integrated Si photonics would have an enormous impact because this technology could potentially meet the ferocious performance demands of Si nanoelectronics in terms of aggregate bandwidth in intra-chip data communication [3]. 3D Si PICs might be constructed by repeated vertical stacking of Si waveguides clad with amorphous insulating materials such as SiO2, but would be inherently infeasible with crystalline Si (c-Si) technology because it is virtually impossible to deposit c-Si on an amorphous substrate. The only remedy for this is wafer bonding technology, but this would be much more expensive than simple monolithic integration. These technological difficulties can be greatly circumvented by using low temperature Si thin film technology, such as hydrogenated amorphous Si (a-Si:H) [4–8], hydrogenated microcrystalline Si (μc-Si:H) [9] and laser crystallized poly-Si [10]. Above all, a-Si:H is an attractive material that can form waveguides because the lowest defect density can be achieved at a low deposition temperature of less than 300°C by plasma-enhanced chemical vapor deposition (PECVD). Our sub-micron scale a-Si:H waveguide showed record low propagation losses of 0.6 dB/cm [11], which is almost comparable to the performance of a c-Si waveguide in the telecommunication wavelength range. Also, the entirely low-temperature processing makes it compatible with backend processing.
To realize 3D integrated Si photonics, one important element is an optical link between each layer of the vertically stacked 3D Si PICs, i.e., a device that can optically couple each lower and upper Si waveguide pair. To date, an a-Si:H vertical directional coupler has been demonstrated, and showed excellent performance with high fabrication accuracy tolerance. The 200-nm-thick spacer layer adopted in [12], however, is too small to prevent optical crosstalk between vertically adjacent Si waveguides [12]. A pair of a-Si:H waveguides with grating couplers at their ends combined with reflective mirrors have been also reported, and demonstrated high-efficiency interlayer coupling, but the structure is intrinsically dependent on both wavelength and polarization [13].
In this paper, we demonstrate a vertical interlayer transition (VIT) device with a 0.6-μm-thick separation layer that could sufficiently suppress any optical crosstalk between stacked Si PIC layers, according to our simulation results. The VIT device is composed of two Si waveguides that are terminated with both horizontally and vertically inverse tapers, located at the lower and upper layers, and a SiON secondary core that only covers the upper waveguide and permits efficient coupling between the vertically separated Si waveguides. The fabricated device showed sufficiently low insertion losses, even when compared with our record low-loss a-Si:H waveguide, along with low dependence on both wavelength and polarization.
2. Device structure and design
Figure 1 shows the VIT device structure. The lower silicon-on-insulator (SOI) waveguide is optically coupled to the vertically stacked upper a-Si:H waveguide through the SiON secondary core (SC). The SiON SC is deposited on the upper a-Si:H taper, which means that the SiON SC directly covers the upper a-Si:H layer, whereas it simply overlies the lower SOI taper, but with an insertion layer of SiO2 between these two layers.
The VIT presented here is based on evanescent coupling of the SiON SC to the two inverse tapers. Here, we adopt a wider and thinner (2-μm-wide and 0.4-μm-thick) SiON SC that enables efficient optical transfer from the lower SOI taper to the overlying SiON SC, despite the presence of the thick SiO2 interlayer. This SiON SC has weak optical confinement properties when compared with the conventional SiON waveguide, e.g., a 1 × 1 μm square waveguide, and the evanescent field of the SiON SC is developed well away from the SiON SC core, meaning that the SiON SC is strongly coupled to the lower SOI tapers. With regard to the coupling of the SiON SC with the upper a-Si:H taper, the coupling mechanism is based on evanescent coupling and is similar to that of a typical inverse taper spot-size converter [14–16]. This ensures an efficient, broadband and polarization-insensitive VIT.
The dimensions of the SiON SC were optimized to minimize the insertion losses at a wavelength of 1550 nm using a numerical analysis based on an eigenmode expansion (EME) method. In the optimization procedure, horizontally inverse tapers were used instead of both horizontally and vertically inverse tapers, which we call knife-edge tapers [18], for calculation efficiency. The validity to use horizontally inverse taper is discussed in the end of this section. The structural parameters used in the simulation are shown in Figs. 2(a) and 2(b). The width and height of the Si waveguide are 400 nm and 220 nm, respectively, while a distance between the two taper tips is 50 μm. The SiON SC is gradually reduced to a width of 0.8 μm, which is a critical dimension for processing, as it approaches the end of the core to reduce excess losses due to refractive index discontinuity. The refractive indices of Si, SiON, and SiO2 were set to be 3.48, 1.62, and 1.44, respectively. The SiO2 interlayer thickness is chosen to be 0.6 μm because of design requirements for optical loss and crosstalk at orthogonal crossings between vertically adjacent Si waveguides [17]. The device is covered with SiO2 as upper cladding.
Fig. 2 (a) Top view and (b) side view of the simulation model. The dimensions in these views are in μm. Calculated transmittances of the VIT device as function of (c) Hsc when Wsc = 2.0 μm, (d) Wsc when Hsc = 0.4 μm, (e) Lt when Wsc = 2.0 and Hsc = 0.4 μm, and (f) Wt when Wsc = 2.0 and Hsc = 0.4 μm. Lt is fixed at 200 μm except for (e) while Wt at 0 μm except for (f). Solid lines and circles show the transmittances for the quasi-TE mode, and the dashed lines and diamonds show the transmittances for the quasi-TM mode.
Figure 2(c) shows the transmittances calculated with varying SiON SC height (Hsc) when its width (Wsc) is fixed at 2.0 μm. Si taper length (Lt) is set to be 200 μm while a tip width of the Si tapers (Wt) is fixed at 0 μm, i.e. ideal horizontally inverse tapers were assumed. Maximum transmittances are obtained for both the quasi-TE and TM modes at an Hsc of around 0.4 μm. At an Hsc of more than 0.6 μm, the transmittance is dramatically reduced, especially for the quasi-TE mode, as a result of the smaller overlap of the optical mode fields between the SC and the lower SOI taper. Figure 2(d) shows the transmittance dependence on Wsc at the Hsc of 0.4 μm, the Lt of 200 μm, and the Wt of 0 μm, indicating that the transmittance is independent of Wsc. According to the EME simulations, the transition losses between the lower and the upper Si waveguides are minimized to 0.013 dB and 0.025 dB for the quasi-TE and TM modes, respectively, at an Hsc of 0.4 μm and a Wsc of 2.0 μm, assuming 200-μm-long ideal horizontally inverse tapers. Figure 2(e) shows the calculated transmittances as function of Lt at the Hsc of 0.4 μm, the Wsc of 2.0 μm, and the Wt of 0 μm. A more than 150-μm-long taper is required to achieve low-loss (< 1%) and polarization-independent operation. In this work, 200-μm-long inverse tapers were adopted for fabricating VIT devices in order to ensure sufficiently low transition loss. Figure 2(f) shows the transmittance dependence on Wt at the Wsc of 2.0 μm and the Hsc of 0.4 μm. The knife-edge taper structure could provide a tip width less than 50 nm [15, 18], so that the worst transition loss due to finite tip width of the knife-edge taper would be 0.054 and 0.18 dB for quasi-TE and TM modes, respectively, although a slight deviation of these losses may arise from the structural difference between horizontally inverse tapers and knife-edge tapers. In particular, the knife-edge tapers are expected to reduce transition loss for quasi-TM mode.
Figures 3(a) and 3(b) show simulation results for light propagation in the VIT device with the structural parameters optimized as above. The light in the lower Si waveguide is transferred to the upper Si waveguide with no apparent loss for both the quasi-TE and TM modes. Similarly, Figs. 3(c) and 3(d) show simulation results for light propagation in the VIT device with the knife-edge tapers. These results are almost same to that with the horizontally inverse tapers, indicating that the device structure optimized for horizontally inverse taper should be valid for the actual VIT device that incorporates the knife-edge tapers.
Fig. 3 Side and cross-sectional views of simulated light propagation of the VIT devices with horizontally inverse tapers for (a) quasi-TE and (b) TM modes, and knife-edge tapers for (c) quasi-TE and (d) TM modes. The figure above each cross-sectional view shows its position shown in the side view.
3. Fabrication and measurement
We fabricated the VIT devices on an SOI wafer with a 220-nm-thick Si device layer and a 2000-nm-thick BOX layer. Si nano-photonic waveguides that were terminated with the knife-edge tapers were fabricated on the SOI wafer using an i-line stepper and inductively-coupled plasma reactive ion etching (ICP-RIE). The knife-edge tapers were used to reduce the transition losses of the VIT device for both the quasi-TE and TM modes [18]. This step is followed by SiO2 deposition at 350°C by PECVD followed by top surface planarization by chemical mechanical polishing (CMP). SiO2 was again deposited by PECVD to adjust the SiO2 thickness to be precisely 0.6 μm. Subsequently, a 220-nm-thick a-Si:H film was deposited at 250°C by plasma decomposition of H2-diluted SiH4 [11], and then the a-Si:H waveguides were fabricated by the same procedure that was used for fabrication of the lower SOI layer. A 0.4-μm-thick SiON film was deposited at 350°C by PECVD, and 2-μm-wide SCs were then fabricated using an i-line stepper and CHF3-based dry etching. Refractive indices of the deposited a-Si:H and SiON were measure to be 3.50 and 1.62 using an ellipsometry. Finally, the upper a-Si:H and SiON waveguides were covered with a 1.5 μm-thick SiO2 film that served as a cladding layer.
The fabricated VIT devices were then optically characterized in the C-band wavelength range. Figure 4 shows a CAD layout together with the measurement setup that was used for the characterization process. The insertion losses were extracted from the transmittance differences among the optical paths, with different numbers of VITs involved. 2, 6, 10 and 14 VITs were inserted with each SOI layer and a-Si:H waveguide to keep the length the same for all paths. Polarized amplified spontaneous emission (ASE) light in the wavelength range from 1530 to 1565 nm was fed into the chip via an optical fiber and condenser lenses. The output light was collected by lenses and launched into an optical fiber, and was then transferred to an optical spectrum analyzer (OSA).
Fig. 4 Measurement setup and CAD layout of the fabricated device chip. (ASE: amplified spontaneous emission; Pol.: polarizer; OSA: optical spectrum analyzer.)
4. Results and discussion
The measured transmittances of the optical paths that contained 2, 6, 10 and 14 VITs were averaged from the same four optical paths and the results are shown in the upper parts of the graphs in Fig. 5. The difference between these transmittances is an integral multiple of the insertion losses of the VITs, so the insertion losses can be estimated. The lower parts of the graphs in Fig. 5 show the experimentally-estimated insertion losses at wavelengths in the C band. The insertion losses at 1550 nm were measured to be 0.87 ± 0.06 dB and 0.79 ± 0.06 dB for the quasi-TE and TM modes, respectively. These values correspond to 82% and 83% transition efficiencies, respectively, between the lower and upper waveguides. Also, the wavelength dependences of the insertion losses were less than ~0.5 dB in the C-band for both polarizations. In the shorter wavelength region, the insertion loss increases slightly for both the quasi-TE and TM modes. This tendency contrasts with the EME simulation results that predicted flat wavelength dependences in the C-band. The slight increase in the insertion loss is due to the absorption of the SiON film. Because hydrogen is incorporated in the SiON films grown at low temperature by PECVD, there is an absorption peak because of the higher order vibrational modes of the N-H bonds around 1510 nm. While this absorption tail is observed in Fig. 5, its effect is mitigated by the short (<~500 μm) length of the SiON SC. These results seem promising for practical applications, demonstrating low-loss, broadband, and polarization-insensitive performance.
Fig. 5 Measured insertion losses of the VIT device for (a) quasi-TE and (b) TM modes are shown on the lower parts of the graphs. The upper parts of the graphs show the measured transmittances of the optical paths when they contain 2, 6, 10 and 14 VITs. Each transmittance value is averaged from the same four optical paths. The colored areas in the lower graphs show the standard errors for the estimated insertion losses.
These experimental values, however, are still larger than those predicted by the EME simulation. To discuss these discrepancies, we performed numerical analyses with varying refractive indices (RIs) of the upper a-Si:H waveguide core and the SiON SC. It turned out that such discrepancies cannot be explained by RI variation of the a-Si:H film. Indeed, deposition of a-Si:H film is pretty reproducible, so that the RI variation is typically less than ± 2%. Even when the a-Si:H film deposition fluctuates in RI of ± 5%, loss deterioration of the VIT would be less than 0.01 dB according to our numerical analysis. The measured RI of the a-Si:H film is 3.50, so that deviation from the RI (3.48) used for the device design should be negligible. On the other hand, loss deterioration due to RI variation of the SiON SC would be somewhat significant when the RI of the SiON is less than 1.55, as shown in Fig. 6. However, as long as its RI exceeds 1.55, low transition loss can be obtained for both quasi-TE and TM modes. Since the SiON RI was 1.62 and is unlikely to drop below 1.55, RI variation of the SiON does not influence the performance of the VIT device. After all, the discrepancies cannot be explained either by RI variations of the a-Si:H or SiON films. Furthermore, additional loss of the VIT due to a finite tip width has a minor contribution. We, therefore, conclude that these discrepancies originate mainly from the waveguide losses of the Si and SiON waveguides. It should be noted that these numerical analyses indicate the VIT device is more robust against an unwanted variation of RI than interlayer coupling devices based on grating couplers which is sensitive to RI of waveguides and cladding materials.
Fig. 6 Calculated transmittances of the VIT device as function of a refractive index of SiON. The structural parameters are the followings: Hsc = 0.4, Wsc = 2.0, Lt = 200, and Wt = 0 μm. A refractive index of a-Si:H was set to be 3.48, which is same to that of SOI.
Table 1 shows a performance comparison between the optical link devices using low-temperature-deposited a-Si:H that have been reported to date. All the devices are significantly efficient. The vertical directional coupler is most compact device, and its fabrication is a simple process, but the layer isolation is insufficient for 3D PICs. The grating coupler satisfies the high layer isolation requirement, but its bandwidth is relatively narrow and grating couplers have strong polarization dependence. In addition, metal mirrors are required to enhance the efficiency of these couplers, resulting in a complex fabrication process. The VIT device showed broadband performance and insensitivity to polarization, but long tapers are required to suppress the losses and the fabrication process is complex because of the SC. Although it was 200 μm in this work, a length of the inverse tapers can be reduced to 150 μm with small excess loss (see Fig. 2(e)), resulting in a total device length of 350 μm. In addition, parabolic taper structure would be advantageous in order to make the taper length shorter while keeping a mode conversion loss low at the same time [19].
Table 1. Performance Comparison of Optical Link Devices
Besides, as the separation layer increases, the interlayer transition losses should be increased, for it is relying on the evanescent coupling. Even though our previous simulation shows that the 0.6-μm-thick separation layer is sufficient to suppress any optical crosstalk between stacked optical layers [17], transition losses would be 0.41 dB and 0.073 dB for quasi TE and TM modes, respectively, even at 1-μm-thick separation layer according to the EME simulation. These value are sufficiently low that the VIT device should be still useful when the thicker separation layer is necessary.
In this work, the VIT devices were demonstrated on SOI wafers. However, even if the lower Si layer on the BOX was replaced with a-Si:H on low-temperature-deposited SiO2, the VIT device performance could be equivalent to that of the VIT devices reported in this paper. This means that these VIT devices can be realized on SiO2-passivated CMOS chips. Therefore, 3D on-chip optical interconnects on the CMOS metal wiring layers are potentially available with efficient, broadband, and polarization-insensitive VIT functionality.
5. Conclusions
We demonstrated a low-loss, broadband, polarization-insensitive VIT device using a 0.6 μm-thick SiO2 interlayer that can provide sufficient optical isolation between vertically adjacent and orthogonally-crossed Si waveguides. The SiON SC couples the lower SOI waveguide to the upper a-Si:H waveguide via knife-edge tapers, and achieved insertion losses of 0.87 ± 0.06 dB and 0.79 ± 0.06 dB at a wavelength of 1550 nm for the quasi-TE and TM modes, respectively. The wavelength dependence of the insertion losses is less than 0.5 dB in the C-band region. While the lower Si waveguides were fabricated using a SOI wafer to demonstrate the vertical interlayer optical transition, equivalent performance levels should be obtained when the lower waveguide is fabricated using a-Si:H. We therefore believe that the VIT device presented here will be useful for construction of high-density 3D on-chip optical interconnects with low-cost CMOS backend processes.
Acknowledgments
This research was funded by the Japan Society for the Promotion of Science (JSPS) through the “Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program),” initiated by the Council for Science and Technology Policy (CSTP). Some of this work was conducted at the AIST Nano-Processing Facility, which is supported by the “Nanotechnology Support Project.”
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