1. Optical lithography: state-of-the-art and future challenges

Over the past 40 years, the increasing need for faster, lower power-consuming, and cost-effective integrated circuits (ICs) has forced the semiconductor industry to decrease circuit size and increase transistor density. The critical dimension (CD), the smallest size feature that a lithography system can print, is given by the well-known variation of the Rayleigh’s formula,$CD=k_1\lambda /NA$, where the k₁ factor depends on the imaging process, $\lambda$ is the source wavelength in vacuum, and $NA$ is the numerical aperture [1]. Advances in optical lithography have enabled the researchers and semiconductor industry to decrease considerably the CD through these three parameters. Ultraviolet (UV) exposure wavelengths have been reduced to 193nm and 157nm, while an extreme UV (EUV) exposure wavelength at 13.5nm is now being considered to produce sub-50nm features [2–5]. Using high refractive index fluids between the optics and the wafer, immersion lithography has pushed NA beyond its “dry” upper limit of 1.0 [6,7]. The k₁ factor has been continuously reduced due to photoresist improvements and resolution enhancement techniques (RETs) [8]. RETs include off-axis illumination [9,10], polarized illumination [11], optical proximity correction (OPC) [12], sub-resolution assist features [13], source-mask optimization [14], alternating phase-shifting masks (AltPSMs) and attenuated phase-shifting masks [15–17], double exposure (DE) [18,19], double patterning (DP) [20], and self-aligned double patterning (SADP) [21]. Now that conventional lithography is reaching its limit, further improvements to reduce circuit size in the sub-100nm regime are becoming increasingly challenging.

First, short wavelengths are economically doubtful. EUV source power and lifetime raise concerns about sufficient wafer throughput and cost of ownership [22,23]. Developing satisfactory UV optics becomes also more complex as high quality growth, excellent refractive index homogeneity, satisfactory transparent materials, and optical coatings with sufficient durability, smoothness and antireflective properties are required [23,24]. Faster degradation of UV photomasks is another significant challenge. Protection, handling, storage, inspection, and repair of UV and EUV photomasks have become major concerns as no tolerance for particle contamination is allowable [22,24]. At EUV wavelength exposure, photoresist materials need also to be improved in terms of sensitivity, resolution, and line edge roughness [22]. In addition, aggressive RETs such as AltPSM or OPC are not compliant with arbitrary layout topologies, imposing specific design restrictions that significantly impact the chip layout [25]. This layout complexity, in turn, tends to create failures in the circuit, requiring rework of chip design [26]. As a result, RETs have led to complex and expensive photomasks [27].

The semiconductor industry has experienced a dramatic growth, in large part due to optical lithography’s low cost of ownership and operation. However, increasing the density of transistors in nano- and microelectronic devices is becoming more and more expensive. Low-volume-production markets, such as application-specific integrated circuits, system on a chip, and photonics need a more cost-effective process. Thus new alternative approaches must be seriously considered.

2. Gridded design rules

A possible path toward a lithography-friendly process is to use extensively the design for manufacturing (DfM) concepts that aim at improving the printability and the manufacturability of a design. Liebmann et al. [28] suggested the use of radical design restrictions (RDR) to reduce the design complexity and dependence on aggressive RETs. Compared to conventional design rules, RDR have been shown to provide smaller linewidth variation; reduced sensitivity to variation of focus; simpler layout modifications; easier generation, inspection, and use of strong RETs; and no area penalty for simple structures, such as inverters or nands [28,29]. Through proper optimizations, logic and memory chip designs based on RDR have been demonstrated to have smaller circuit area and improved performance [26,30]. RDR have been further pushed to 1D gridded design rules (GDR), referring to a highly regular design with common orientation and pitch in 1D [21,31]. Although GDR add more design restrictions than RDR, 2D random layouts of six-transistor static random-access memory (SRAM) bitcells and logic functions have been successfully converted into highly regular 1D layout, leading to better uniformity and performance [31,32]. Due to their inherent advantages, Intel and IBM have begun to adopt RDR and GDR in their most advanced designs [25,33].

Fabrication of 1D GDR-based layouts can be performed by using IL [18] or AltPSM [27,34]. Double-step techniques together with DE, DP, and SADP have been added to the ITRS roadmap for both near-term and long-term potential solutions as well [19,21,22]. Yet, integrating a functional pattern within a 1D periodic structure requires a supplementary trim exposure step. These multiple-exposure approaches present serious challenges including overlay (mask-to-image and mask-to-mask matching and alignment), CD changes, and processing time [19,22]. Also, the cost associated with supplementary steps will dramatically increase. According to the ITRS Executive Summary, “lithography cost will almost double” with DP or DE, and possibly triple when the additional trim exposure is taken into account. Therefore, there is a significant need for a cost-effective lithography technique that produces highly regular patterns with embedded non-periodic elements in a single-exposure step.

3. Pattern-Integrated Interference Lithography

To address the above requirements, we recently introduced Pattern-Integrated Interference Lithography (PIIL) [35]. PIIL is the integration of superposed pattern imaging with IL, enabling the single-exposure fabrication of multi-dimensional periodic structures with integrated non-periodic mask elements.

The last column of Table 1 lists four example layer designs of a 1D regular-pitch SRAM bitcell proposed by Greenway et al. [32]. While these layouts were initially designed for DE or DP techniques, they are now appropriate for PIIL as well. The interference patterns required for four representative layers are listed in the second column of Table 1. The polysilicon and first metal layers are based on 1D gratings produced by two-beam PIIL, while the first and second via layers are based on 2D periodic structures produced by three-beam PIIL. Furthermore, periodicities, plane group symmetries, linewidth, contrast, as well as motif sizes and shapes can be controlled through judicious adjustment of the beam amplitudes and polarizations, wavevector orientations, exposure dose, and photoresist threshold [36,37]. Modification of the interference pattern also requires a blocking pattern mask, whose integration within the periodic structure can be improved through proper mask design optimization. Examples of geometric-minimum-size and geometric-maximum-size non-periodic blocking pattern designs are shown in Table 1. Mask design optimization will be further discussed in the next section. Shown in the last column of Table 1 are the resulting SRAM exposures, where the blocking elements have prevented the formation of specific portions of the interference fringes or motifs, effectively trimming the periodic pattern.

Table 1. Single-step combinations of 1D and 2D interference patterns with integrated blocking elements to produce SRAM bitcell exposures as implemented by PIIL. A single bitcell is indicated by the dashed line.

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Therefore, PIIL is a promising method for a fast and cost-effective fabrication of GDR-based semiconductor devices in a single-exposure step, thereby reducing the number of lithographic steps and thus mitigating the associated alignment, processing, and yield issues.

4. PIIL implementation: Pattern-Integrated Interference Exposure System

Implementation of PIIL as a Pattern-Integrated Interference Exposure System (PIIES) has been recently demonstrated and applied to photonic-crystal device fabrication [38,39]. PIIES incorporates a projection imaging capability in a novel three-beam interference configuration as depicted in Fig. 1 (the third wavevector, k₃, is not represented for clarity but is parallel to k₁ and k₂ and lies out of the plane of the page).

 

Fig. 1 Three-beam PIIES. This PIIES illumination system provides a coherent illumination of the blocking pattern mask located at the pattern mask plane. The PIIES compound objective lens images the blocking elements at the wafer plane. Simultaneously, the PIIES compound objective lens collimates the beams at the wafer plane, thereby integrating the blocking elements of the mask in a three-beam interference pattern in a single-exposure step.

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The illumination system and the compound objective lens are the two main elements of the PIIES. The present illumination system is composed of three mutually coherent laser beams, three expander lenses, and a condenser lens. In order to facilitate alignment, the expander lenses focus the multiple beams at the condenser lens front focal plane, thus providing multiple coherent beams that illuminate the blocking pattern mask. The polarization and amplitude of each beam can be individually adjusted upstream using a configuration that is not represented in Fig. 1 [40]. The area of overlap of the three expanded beams on the blocking pattern mask is maximized by placing the pattern mask plane at the condenser lens back focal plane. The compound objective lens consists of two large diameter aspheric lenses arranged in a 4f configuration. Its purpose is two-fold. The compound objective lens collimates, at the wafer plane, portions of the multiple beams that pass through the transparent areas of the blocking pattern mask. These unperturbed beams interfere and produce a uniform-periodic interference pattern at the wafer plane. For each beam, the PIIES compound objective lens also images the blocking elements at the wafer plane. The blocking elements, reduced by a factor $1/\left|m\right|$ where m is the magnification due to the compound objective lens, prevent the formation of specific portions of the interference fringes or motifs. Single-exposure fabrication through PIIES of 2D square-lattice interference patterns with integrated elements, such as a cavity and a waveguide, have been demonstrated as depicted in Fig. 2 and Fig. 3 [38].

 

Fig. 2 PIIES single-exposure fabrication result. (a) 600.0 μm x 600.0 μm Greek-cross blocking element; (b) SEM image of the single-exposure integration of the reduced Greek cross within a three-beam interference pattern; (c) Magnified SEM view of the top-right corner of the Greek cross integrated within a 2D square-lattice periodic pattern with a lattice constant $a=1.0\mu m$.

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Fig. 3 PIIES single-exposure fabrication result. (a) 20.0 μm x 2.0 μm line segment blocking element; (b) SEM image of the single-exposure integration of the reduced line segment within a three-beam interference pattern; (c) Magnified SEM view of the line segment integrated within a 2D square-lattice periodic pattern with a lattice constant $a=1.0\mu m$.

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In order to improve the integrated projection-imaging capability, more refined optical systems may be designed to produce higher-quality collimated interfering beams at the wafer plane. In practice, PIIL should be capable of similar CD feature sizes as conventional optical lithography with proper NA and source wavelength. Furthermore, the present PIIES configuration can be modified to enhance the system printability through optimization of the sources at the aperture source plane, spatial filters at the pattern mask plane and spatial-frequency filters at the Fourier plane. Taken together, the source, the pattern mask, and the Fourier filter provide multiple degrees of freedom in the design of the lithography system.

4.1. Aperture source plane

As an element of the illumination system, the aperture source plane plays a fundamental role in the formation of the interference pattern and the integration of the illuminated blocking elements. In order to define a desired interference-pattern periodicity a at the wafer plane, the incidence angle $\theta$ of the beams with respect to the wafer-plane normal can be modified by adjusting the common beam displacement d_beam at the aperture source plane. Source positions at the aperture source plane also determine the wavevector configuration at the wafer plane and, therefore, the plane group symmetry of the resulting interference pattern. For the two-dimensional interference patterns required for the first and second via layer examples in the first column of Table 1, square motifs are desired. Through judicious selection of individual-beam polarizations, amplitudes, and phases, recent research has shown that motif geometries that vary between a circle and square can be obtained [41]. Of course, the resulting patterns may vary from the ideal square geometry provided that the resulting electrical characteristics of the bitcell meet the IC performance requirements.

In the present PIIES configuration, multiple highly coherent beams illuminate the blocking pattern mask. However, coherent illumination is particularly sensitive to optical imperfections, and may lead to speckle due to surface roughness and “ringing” effects at the edge of a projected mask feature [42]. Thus blocking elements illuminated by coherent light may distort the formation of the nearest-neighbor fringes or motifs in the interference pattern when projected. Partially coherent illumination mitigates these effects and may improve the integration of the blocking pattern within the interference pattern. In the present PIIES configuration, partial coherence can be introduced by adjusting the position of expander lenses while collimation of the interfering beams at the wafer plane is maintained through proper arrangement of PIIES objective lenses. However, the area of interference at the wafer plane may be reduced since it is proportional to the collimated beam diameter D, which is related to the size of the source at the aperture source plane.

4.2. Pattern mask plane

The aim of PIIL is to prevent the formation of specific portions of the interference pattern. Analogous to OPC, modification of the interference pattern can be improved by considering blocking pixels with modified shapes (e.g. squares, circles, diamonds, octagons, stars, etc.) and features with adjusted size (e.g. oversize or undersize). More generally, RETs-optimized designs that are more amenable to GDR-based layouts may be considered to enhance PIIL performance. An appropriate merit function, typically a combination of performance metrics, such as the intensity and lattice-vector metrics for unaltered and altered interference pattern presented in [38], would describe the integration of the mask pattern. This merit function would be minimized using a standard optimization procedure such as simulated annealing or the genetic algorithm.

4.3. Fourier plane

4.3.1. Periodic-cell circuit

Due to the two-dimensional periodic repetition of bitcells in the example SRAM designs shown in Table 1, the spatial frequencies corresponding to these periodicities (typically much larger than the interference periodicities) occur at discrete locations in the Fourier plane of each beam. A filter in the Fourier plane can efficiently use this periodicity to improve further the modified interference pattern at the wafer plane. The physical positions x_f and y_f as measured in the Fourier plane are related to the spatial frequencies in the mask plane through $x_f=\lambda f_{OL1}{f}_x$and$y_f=\lambda f_{OL1}{f}_y$. The blocking elements in the pattern mask, of course, are also repeated with the same periodicities. In the wafer plane, the residual light at the locations of the blocking elements due to diffraction can be further attenuated by judicious spatial filtering in the Fourier plane. Thus the contrast and resolution in the wafer plane interference image can be enhanced. The distribution of attenuating elements in the Fourier plane that is needed to reduce the light associated with blocking elements in the pattern mask plane is shown schematically in Fig. 4 . In the Fourier plane, due to the periodic repetition of bitcells in the SRAM design, the attenuating elements occur at the fundamental spatial frequency and harmonics of the fundamental as shown in Fig. 4. The relatively large period in the x direction in the example SRAM design in Table 1 produces the relatively small spatial frequency f_x in the x direction. Likewise, the small period in the y direction produces the large value of f_y.

 

Fig. 4 Distribution of attenuating elements in the Fourier plane that is needed to reduce further light in the modified interference pattern in the wafer plane associated with blocking elements in the pattern mask plane. The quantities f_x and f_y represent the spatial frequencies in the x and y directions respectively in the pattern mask plane. Due to the periodic repetition of bitcells in the SRAM design, the attenuating elements occur at corresponding fundamental and harmonic spatial frequencies in the Fourier plane as shown in this figure.

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The use of a Fourier filter can increase the contrast and resolution achievable at the wafer plane over that which is obtained without a filter. Of course, blocking a pattern that occurs in each bitcell in the pattern mask also blocks the same periodic pattern in the desired wafer plane image. The effectiveness of the Fourier filter will be greatest when the blocking pattern (with bitcell periodicity) in the pattern mask differs from the desired circuit pattern (with bitcell periodicity) to the largest extent possible. Thus, in this case, the Fourier components associated with the blocking pattern differ significantly from those of the desired circuit pattern and these unwanted Fourier components can be attenuated in the Fourier plane with a suitable Fourier filter. Using standard optimization methods, Fourier filters (magnitude and phase) can be designed to enhance maximally the set of characteristics needed in the wafer plane which again would be typically described by the appropriate merit function introduced above. The optimal Fourier filter can be determined by numerically calculating the Fourier transform of the blocking pattern in the mask plane. Alternatively, it can be constructed by inserting a negative of the blocking pattern (transparent at the blocked pixels and opaque elsewhere) in the mask plane and suitably recording the Fourier transform amplitude pattern in the Fourier plane. Subsequently that recording can be used as the Fourier filter in the Fourier plane.

4.3.2. Non-periodic cell circuit

In the case when the circuit is not periodic, there will no longer be distinct spatial frequency locations in the Fourier plane that correspond to circuit periodicities. The two-dimensional Fourier transform will be continuous in nature and spread over the Fourier spatial-frequency plane. For this situation, the form of a useful Fourier filter is less obvious. The spatial frequencies to be attenuated will be overlapping with the spatial frequencies to be passed. Nevertheless, using the same standard optimization methods and merit function mentioned above, a Fourier filter (magnitude and phase) can again be designed to enhance the characteristics desired in the wafer plane. The level of improvement with a Fourier filter would be dependent case-by-case on the particular circuit configuration. As before, the optimal Fourier filter could be determined by numerically calculating the Fourier transform of the blocking pattern in the mask plane. Also, as before, it could be constructed by inserting a negative of the blocking pattern in the mask plane and suitably recording the Fourier transform amplitude pattern.

5. PIIL implementation: diffractive photo-mask

In spite of PIIES capability to modify interference pattern selectively, the present PIIES configuration may have interferometric stability issues due to its opto-mechanical components and positioners. The PIIES is appropriate for development, prototyping, and small-volume manufacture but may be less suitable for large-volume production of GDR-based semiconductor devices. To address this issue, we consider a diffractive photo-mask (DPM) as an alternative approach for cost-effective fabrication of semiconductor devices in a commercial setting [43].

An example DPM consists of a holographic recording substrate together with a zero-order beam blocking element in its center. As depicted in Fig. 5(a) , the DPM is placed between the PIIES second objective lens and the wafer plane. Also, a reference beam derived from the same laser source as the PIIES beams is focused at the front focal plane of the second objective lens using an additional lens and a beam-splitting pellicle. The reference beam is therefore collimated at the DPM where the integrated-pattern-mask information of the PIIES multiple beams are incident. Once the holographic recording is processed, appropriate illumination of the DPM by a collimated reference beam reproduces the original PIIES beams whereas the reference beam is blocked by the zero-order beam blocking element, as depicted in Fig. 5(b). The reproduced beams will, in turn, create the designed pattern-integrated optical-intensity distribution.

 

Fig. 5 Example implementation of PIIL through DPM. (a) A reference beam is added to the PIIES using a lens and a pellicle to record interferometrically the integrated-pattern-mask information at the DPM surface. (b) Once developed and properly illuminated, the DPM duplicates the PIIES interfering beams, which, in turn, form the designed pattern-integrated optical-intensity distribution.

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A DPM would have several advantages over the PIIES. First, the DPM is phase-locked and thus is more interferometrically stable. Second, the position of the integrated-blocking-elements relative to the interference remains unchanged for each new exposure. Third, there is no metallic pattern prone to degrade upon repeated exposure like in contact lithography. All the diffractive elements are at the top of the DPM and/or within the DPM. Consequently, the DPM provides a simple and cost-effective method for large-volume single-exposure fabrication of GDR-based semiconductor devices.

6. Summary and discussion

For the past forty years, the semiconductor industry has been capable of increasing the transistor density significantly due to optical lithography performance. As conventional lithography is reaching its limit, EUV exposure wavelengths, immersion lithography, and aggressive RETs are being considered to produce ever smaller semiconductor devices. However, these methods are extremely challenging and economically doubtful, raising concerns particularly for low-volume-production markets that require cost-effective techniques. Alternative DfM approaches, such as RDR and GDR, have been demonstrated to provide less design failures, easier implementation of strong RETs, as well as improved performance compared to 2D random layouts. Semiconductor industry leaders Intel and IBM have started to adopt GDR in their device designs. Fabrication of GDR-based layouts, however, requires multiple-exposure steps techniques that raise concerns regarding overlay, processing time, and supplementary costs.

We address this issue by presenting PIIL, a potentially simple, fast, and cost-effective fabrication technique for GDR-based logic or memory chips. PIIL enables, through the integration of superposed pattern imaging with IL, the selective modification of 1D or 2D interference patterns. PIIL has been implemented in a PIIES that incorporates a projection imaging capability in a novel three-beam interference configuration. Experimental fabrication of pattern-integrated periodic structures in a single-exposure step has been demonstrated. In addition, large-volume production of GDR-based devices in a commercial setting could take advantage of the proposed DPM, a more interferometrically stable PIIL implementation.

Specific control of the PIIES beam amplitudes, polarizations, and directions at the aperture source plane allows for a wide range of periodicities, plane group symmetries, and contrast, as well as various motif sizes and shapes. Integration of a blocking pattern design may be enhanced through partially coherent illumination, optimization of the blocking pattern mask and Fourier filter. These optimizations can be performed separately and then combined. However, this may not yield an overall optimization of the aerial image characteristics needed at the wafer plane. The best blocking pattern mask and the best Fourier filter individually found may not yield the overall best performance. To achieve a global optimization of the image at the wafer plane these individual optimization processes would be combined into a single overall global optimization. Thus the features in the pattern mask plane and the features in the Fourier plane are simultaneously and jointly optimized in this global process. Further, if other than point sources are used in the aperture source plane, the shapes and sizes of these sources can also be optimized separately or included in a global three-way source-mask-filter optimization.

In constructing GDR-based devices, the interference recording step and the trim step have always been considered to be separate, distinct steps. PIIL is “unexpected” in that it combines these steps which in the past have been considered to be mutually exclusive. They have been viewed as inherently differing steps, in part, because interference and imaging cannot be done simultaneously perfectly. There is an inherent trade-off between them. However, in practice, it has been shown that interference and imaging can be done simultaneously to a high level of fidelity. Thus the theoretical limitation is not a practical limitation. In PIIL, neither interference nor imaging is done perfectly. However, in periodic-pattern-based devices inherently imperfect-quality interference and imaging can be completely acceptable in terms of resulting device performance.

In summary, combining processing steps can make manufacturing simpler and reduce costs. In addition, the degrees of freedom associated with the source, pattern mask, and Fourier filter provide broad design flexibility. Thus PIIL offers a potentially simple, fast, and cost-effective lithographic technique for regular-layout nano- and microelectronics chips.