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Demonstration of optical computing logics based on binary decision diagram

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Abstract

Optical circuits are low power consumption and fast speed alternatives for the current information processing based on transistor circuits. However, because of no transistor function available in optics, the architecture for optical computing should be chosen that optics prefers. One of which is Binary Decision Diagram (BDD), where signal is processed by sending an optical signal from the root through a serial of switching nodes to the leaf (terminal). Speed of optical computing is limited by either transmission time of optical signals from the root to the leaf or switching time of a node. We have designed and experimentally demonstrated 1-bit and 2-bit adders based on the BDD architecture. The switching nodes are silicon ring resonators with a modulation depth of 10 dB and the states are changed by the plasma dispersion effect. The quality, Q of the rings designed is 1500, which allows fast transmission of signal, e.g., 1.3 ps calculated by a photon escaping time. A total processing time is thus analyzed to be ~9 ps for a 2-bit adder and would scales linearly with the number of bit. It is two orders of magnitude faster than the conventional CMOS circuitry, ~ns scale of delay. The presented results show the potential of fast speed optical computing circuits.

©2012 Optical Society of America

1. Introduction

Current CMOS based silicon electronics have dominated information processing which will not change in the foreseeable future. However, increasing the density of transistors and metal interconnects following the Moore’s law is facing a limitation mainly due to power dissipation problem [1]. Actually, processor industries have adopted multi-core architecture instead of single core with higher frequencies and ended up better performances. Fast data communications between cores are critical in this architecture. Optical interconnection has been widely acknowledged to be a promising alternative for its electronic counterpart to achieve high transmission speed and reduce power consumption [2]. The incomparable speed, low loss, and crosstalk-free nature of light can effectively solve the problems caused by the metal interconnection.

In addition to optical interconnects, some special-purpose computing tasks could also benefit from the parallelism friendly and ultrafast optical circuits. Parallel processing is possible by using lights with different frequencies. The cross talk free and fast speed of light make it a superior alternative for electron to do intense digital processing tasks like video processing [3].

However, a low power consumption and small footprint optical transistor has been proved to be challenging due to the weak light-matter interaction [4]. The existing platform based on von Neumann Architecture and Boolean algebra conceived and developed for CMOS as in Table 1 cannot be adopted in optical circuits. Several alternative architectures have been proposed without competing with electronic transistor, including vector matrix multiplier [5], directed logic (DL) [6], virtual gate logic [7], [8] and even a reconfigurable logic [9]. Several theoretical and experimental works have been reported recently based on the DL architectures, and has shown their potential application in video encodings [10,11].

Tables Icon

Table 1. Comparison of the architectures for information processing

Similar to the directed logic, the BDD is also an optics friendly architecture to do optical logic computing. A scalar signal like an optical pulse is launched into the root of a circuit as a messenger. Each input bit is represented by a binary switch with one input and two output terminals. The messenger entering the node is switched to one of the output terminals depending on the gate signal. Cascading computing is achieved by integrating many switching nodes in appropriated ways. One messenger starts from the root, and transmits the nodes defined by the function of the circuit. Different output terminals represent different results of the processing. Asahi and his associates have demonstrated the single-electron logic circuits based on the BDD in which a single electron is used as the messenger. They have also proposed the designs of several basic logic circuits and predicted that using photons instead of a single-electron as the signal could also achieve the same functionality [12]. However, there is still no experimental demonstration of optical circuits due to the difficulty of finding a feasible switching device.

Recent research effort on optical switching especially in Si photonics has achieved tremendous performance improvements [13]. Resonator based optical switches modulated by electrical [1415], thermal [16], or optical [17] signals have been widely investigated. 30Gbit/s all-optical switching has been reported by two-photon absorption in ring resonators [18]. Comparing to Mach-Zehnder interferometers [19], ring resonators have small footprints, and reduced switching threshold due to a high field enhancement. A few tens of pico-joules per pulse lead to 1.2 nm resonance shift in a ring resonator, sufficient for switching in high-Q resonators [17]. Certainly, there are still remained issues like fabrication tolerance, temperature stability, etc. We think the time to start investigating systems as well as devices has come.

Addition is considered as the basic operation of computing systems. Achieving a photonic adder is a primary step towards developing more complex optical computing circuits. Here, we redesign and optimize the BDD logic circuits for optical implementation and experimentally demonstrate 1-bit and 2-bit adders on a silicon-on-insulator (SOI) chip. Optical pumping of ring resonators has been used as the switching nodes in our demonstration as a proof of concept. To the best of our knowledge, this is the first demonstration of optical computing circuits based on BDD architecture.

2. Design

Figure 1 (a) shows the symbol of a switching node in our BDD circuits. Optical signal called messenger from the root is switched to the left or right terminal when the gate signal X is 0 or 1, respectively. The processed result of the circuit is obtained by detecting light from one of the output terminals: light coming out from the right terminal represents logic value 1, and left represents 0. In this paper, we choose ring resonators as the switching nodes as in Fig. 1(b). Instead of electron injection from electrodes, we use top-optical pumping of the ring to switch the resonance of ring and the output of the messenger. The pumping introduces extra electron-hole pairs in the ring resonator and change refractive index of the ring resonator due to plasma dispersion effect of Si.

 figure: Fig. 1

Fig. 1 (a) Symbol of the switching node, (b) schematic diagram of an optical pumping switch using ring resonator on SOI wafer.

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Any logic circuits can be constructed by connecting nodes to represent different input variables. For examples, Fig. 2(a) shows the architecture of a 1-bit adder. Gate signals are sent by pumping these rings with value 1. All variables have to be set prior to the processing. Light pulses are launched from the root and propagate through certain routes. For example, the route of light with input a0 = 1 and b0 = 0 is shown as a red line in Fig. 2(a). The first and second digits of the sum are determined by detecting the light from output terminal S0 and C0, respectively. Therefore, the results of red line case are s0 = 1 and c0 = 0. The schematic diagram of our 1-bit adder using ring resonators is shown in Fig. 2(b).

 figure: Fig. 2

Fig. 2 (a) Architecture of a 1-bit adder, (b) Schematic diagram of 1-bit adder using ring resonators, (c) Architecture of a 2-bit adder. The red line shows the optical route when a0 = 1, and b0 = 0.

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Similarly, a 2-bit adder could be constructed by adding additional switching nodes to the circuit as in Fig. 2(c). Pulse signals with different wavelengths (λ02) representing different digits are launched from roots with symbols S0-S1 and C1. At the terminal, light signals are split into different wavelengths and converted back to electrical signals. The value of different digits of the sum is decided by measuring signals assigned with different wavelengths. For example, the value of S1 is 1, only when light with the wavelength of λ1 arrive the terminal, otherwise, S1 is 0. Higher bit adders could be designed by adding additional nodes and using more frequencies.

A quality factor (Q) of the ring resonators is critical to determine the processing time of the circuits. Using the ring resonator as the node would increase the propagating time since there is a delay before light leaving the resonating cavity. High-Q resonators significantly increase the total processing time due to a longer photon lifetime in the cavity. Meanwhile, low-Q cavities have broader resonance peaks, and a large peak shift is required to maintain a functional extinction ratio of the switches. Therefore, modulating the switches needs a stronger driven signal, which will increase the power consumption of the circuits.

Aiming at a processing time of 100 ps for a 64-bit calculation, we have designed microrings with a delay of ~1ps. The cavity photon lifetime can be calculated by τcav = λ2/(2πcΔλ), where c is the speed of light in vacuum, Δλ is the FWHM of the resonance peak. A photon lifetime of 1 ps corresponds to a Q of 1200 (Q = Δλ/λ) at the wavelength of 1550 nm, which has been achieved by carefully engineering the structures between the bus waveguides and the microrings.

3. Experiment

Figure 3 is a microscope image of the 2-bit adder portion of the chip. The lower bit sub-circuit surrounded by the black broken line is identical to the design of a 1-bit adder. The optical circuits were fabricated on a SOI wafer with a 0.34 μm top Si layer and a 1 μm buried oxide layer. Designed structures were fabricated by electron beam lithography followed by a reactive ion etching (RIE) dry etching. The switching rings have a radius of 5 μm and a width of 0.4 μm. Light is coupled into the rings from bus waveguides with a gap of 0.2μm between them. Spot size converters (SSC) with an inverse Si taper were fabricated on both input and output of the waveguides, which can reduce the coupling loss to <0.5 dB/port [20]. Light from New Focus 6300 tunable laser with wavelength of 1520-1570 nm was coupled into waveguides using a lens fiber. Power of transmitted light was measured by a Germanium detector. A green laser with wavelength of 532 nm was used to pump the rings from the top of the chip. Pumping beam was focused to a spot of ~10 μm in diameter with a pumping power of 56 mW. Transmission spectra and responses from the output ports were measured.

 figure: Fig. 3

Fig. 3 Optical microscope image of the fabricated 2-bit adder circuit following the architecture of Fig. 2(c), the lower bit sub-circuit in the black broken line is identical to a 1-bit adder as in Fig. 2(b).

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There are several unused output terminals in the design. In more complicated circuits, we may need to introduce additional design like a taper to eliminate the reflection at the end of these unused terminals. Due to the simplicity of our current circuit, no particular treatment has been taken to reduce the reflection, which won’t affect the meaningful output results since all the reflected light goes back to the light source.

Transmission spectrum from the drop port (S0) in the 1-bit adder was measured. The ring has a free-spectrum range (FSR) of 20 nm. The full width of half maximum (FWHM) of the resonance is 1 nm measured from the spectrum, corresponding to a Q of 1500. The measured Q is very close to the designed value (1200) considering the fabrication uncertainties. Transmission spectra in Fig. 4 show different resonance peaks for a0 and b0 rings due to the fabrication error. The difference of resonance wavelengths would limit the performance of high bit circuits, which require multiple identical rings in series. The improvement of nanofabrication techniques could ease this limitation in the future. Other tuning mechanisms could also be implemented to control the resonance frequencies of each ring individually. By measuring the peak shift when pumping rings separately, we can identify the peaks of a0 and b0 resonators.

 figure: Fig. 4

Fig. 4 Transmission spectrum of s0 output port in the 1-bit adder.

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We first demonstrated the add operation when changing the input a0 and fixing b0 to 0. The dynamic responds of the S0 port is shown in Fig. 5(a) when manually pumping the a0 ring. The resonance wavelength of a0 ring (1550.9 nm) was used as a messenger. Therefore, input a0 equals to 1 and b0 equals to 0 without optical pumping. Light is coupled to S0 port, corresponding to a sum of 1. When switching a0 to 0 by exciting a0 ring using green laser with power 56 mW, signal intensity from S0 port dropped, which corresponding to a sum of 0. A 2 dB power switching has been measured. When s0 is 0, we still see a non-zero output power. This is due to the light coupled through the b0 ring following a0. By optimizing the fabrication process and reducing the resonance wavelength difference for different rings, this background can be suppressed, which has been verified by switching the b0 as in Fig. 5(b). The resonance wavelength of b0 ring: 1548.5 nm was used. Similar to previous case, output S0 can be tuned corresponding to the sum s0 when switching b0 between 0 and 1 by exciting b0 ring. The output signal from S0 port is near zero when the sum s0 is zero. A >10 dB switching depth has been achieved.

 figure: Fig. 5

Fig. 5 Transmitted power from S0 port when (a) b0 = 0, and manually switch a0, (b) a0 = 0, and manually switch b0.

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Similar add operations for the 2-bit adder have also been verified by switching a1 and b1. However, due to our instrument limitation, only one ring can be excited at a time. More complicated add operations are not available in our current setup.

4. Discussion

The speed is one of the most important figures of merit for optical computing. The total processing speed depends on the time for light to propagate through the circuit and the electrical-optical (EO) and optical-electrical (OE) conversions times including time for switching the states of nodes, and response time of photodetectors. The EO and OE conversion times do not scale with the number of bit, and can be eliminated in the future all optical circuits. Our discussion will focus on the computing time, during which light propagates from the root to the terminals of the circuits. A relatively low Q (~1500) structure in our experiment takes 1.3 ps for signal to pass through each switch. A ~100 µm waveguide session between two adjacent rings takes an extra 1 ps. One adding calculation takes ~9 ps for the messenger to pass through a 2-bit circuit. The propagating time is linearly scaling with the number of bits. Using different wavelength optical signals also improves processing speed since the computing of different bits can be processed in parallel. All optical nonlinear switch devices, although still in the early stage, could provide further speed boost in the future by reducing the optical response time and eliminating the EO conversion [21,22].

5. Conclusion

We have designed and experimentally demonstrated 1-bit and 2-bit adder optical circuits based on the concept of BDD on Si CMOS platform. Add operations on both 1-bit and 2-bit adders have been verified in our experiment. A switching depth of >10dB for the optical pumping ring has been confirmed. The optical processing time is analyzed to be 9 ps for the 2-bit adder, which is 100 times faster than the current electronics. The optical adder circuits demonstrated open up the opportunities for optical computing platform.

References and links

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Figures (5)

Fig. 1
Fig. 1 (a) Symbol of the switching node, (b) schematic diagram of an optical pumping switch using ring resonator on SOI wafer.
Fig. 2
Fig. 2 (a) Architecture of a 1-bit adder, (b) Schematic diagram of 1-bit adder using ring resonators, (c) Architecture of a 2-bit adder. The red line shows the optical route when a0 = 1, and b0 = 0.
Fig. 3
Fig. 3 Optical microscope image of the fabricated 2-bit adder circuit following the architecture of Fig. 2(c), the lower bit sub-circuit in the black broken line is identical to a 1-bit adder as in Fig. 2(b).
Fig. 4
Fig. 4 Transmission spectrum of s0 output port in the 1-bit adder.
Fig. 5
Fig. 5 Transmitted power from S0 port when (a) b0 = 0, and manually switch a0, (b) a0 = 0, and manually switch b0.

Tables (1)

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Table 1 Comparison of the architectures for information processing

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