All-optical processing is envisioned for future communication networks to overcome the bandwidth limitations of electronics, avoid inefficient optical-to-electrical-to-optical (OEO) conversion, and thus facilitate the increase in communication rates to beyond a Tb/s [1,2]. Much research has focused on components for high-speed all-optical processing, including devices for wavelength conversion [2,3], logical operations [4], signal regeneration [5], and channel multiplexing and demultiplexing [1,6]. Components essential to building extremely large bandwidth all-optical networks include optical devices for digital signal processing, data storage, and data encryption. Notably, all these devices rely on all-optical logic gates, and thus all-optical logic gates have attracted much attention recently.

In addition to the demonstration of individual all-optical logic gates such as XOR, XNOR, AND, NOR, and NAND [7–11], all-optical logic blocks, including half adders/subtracters [12,13], flip-flop memory [14], and data encryption [15], have been theoretically proposed and experimentally realized over the past decade. Specifically, all-optical logic gates, including AND, NAND, XOR, XNOR, and NOR, via on–off keying (OOK) have been demonstrated based on single [16] or cascaded [17] microring resonators using either thermo-optic effect or carrier effects, two-photon absorption (TPA) [18], and the Raman effect [19]. However, the operating speeds of these demonstrations are restricted to less than 1 Gb/s due to a combination of the bandwidth limitation of ring resonators and speed limitations imposed by the employed nonlinearities. High-speed all-optical XOR, XNOR, AND, and NOR gates using parametric nonlinear effects such as four-wave mixing (FWM) have been realized via polarization-shift keying (PolSK) [7,8] and differential phase-shift keying (DPSK) [9]. However, the high-speed modulation and detection of polarization state or phase make the practical implementation of these systems more complex. Although high-speed all-optical OOK A AND $\overline{\mathrm{B}}$, $\overline{\mathrm{A}}$ AND B logic functions [4], and signal regenerators [5] have been demonstrated via pump depletion in periodically poled lithium niobate (PPLN) waveguides, they are not elementary logic gate operations. A high-speed all-optical OOK NAND gate has been realized using cross-gain modulation in semiconductor optical amplifiers (SOA) [11], but the need for two SOAs and optical inputs from two opposite directions make the system complex and difficult to integrate. To the best of our knowledge, high-speed all-optical NAND logic gates via OOK using a single device or Kerr-nonlinearity have not been reported.

In this Letter, we exploit a parametric nonlinear process termed four-wave mixing Bragg scattering (FWM-BS) [20] to experimentally realize a high-speed all-optical NAND logic gate via OOK in highly nonlinear fiber (HNLF). We demonstrate 10-Gb/s NAND/AND logic operations in the time domain with open eye diagrams. Notably, the NAND gate is a universal logic gate and therefore can serve as a basic building block for all other logic gates. Additionally, our approach can be readily extended to higher data rates and potentially transferred to on–chip platforms, making it possible in the future to realize high-speed cascaded logical operation in integrated all-optical systems.

As shown in Fig. 1, FWM-BS is an ultrafast third-order nonlinear optical process in which a signal photon and a single pump photon (pump 2) are annihilated to produce a different pump (pump 1) and idler photon (see Fig. 1(a)). During FWM-BS, the signal is depleted; and in the case when the input signal power is much less than that of the pumps, see Fig. 1(b), this depletion can be significant and therefore exploited for logic operation. FWM-BS is a parametric process and thus energy is conserved among the interacting photons. To achieve phase matching and thus enhance the efficiency, pump 2 and the signal are equally spaced in frequency from the zero-group velocity dispersion (zGVD) wavelength, as depicted in Fig. 1(b). Previous research on the FWM-BS effect has demonstrated low-noise frequency conversion [21,22], translation of quantum states [20,23], and optical isolation [24]. By encoding the logical inputs on the two pump waves of the FWM-BS process via OOK, we deplete the continuous wave signal to yield the NAND optical logic gate operation on the signal wave at the output. Interestingly, the AND logic operation is concurrently achieved on the generated FWM-BS idler, as depicted in Fig. 1(c).

 

Fig. 1. (a) Energy diagram of the FWM-BS process, a signal photon and a pump 2 photon can be converted into a pump 1 photon and an idler photon; (b) spectrum of the FWM-BS process, the zero group velocity dispersion (zGVD) wavelength is generally placed in the center of the four waves to achieve phase matching; (c) NAND/AND logic gates design based on FWM-BS via OOK and the corresponding truth table.

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To demonstrate the feasibility of the NAND logic function, the spectra and signal depletion ratio are measured as a function of total input pump power, and Fig. 2(a) shows the experimental setup for these measurements. An 800-m HNLF (OFS HNLF standard) with zGVD wavelength near 1552 nm is used as the nonlinear element for the logic operation. The signal (1540.4 nm) and pump 2 (1564.3 nm) are equally spaced in frequency from the zGVD wavelength of the fiber to achieve phase matching, and pump 1 is set to 1549.2 nm. The two pumps and the signal are generated with continuous-wave (CW) lasers. The two pumps are combined by a wavelength-division multiplexing (WDM) coupler. For the preliminary signal depletion measurement, the combined pump waves are then phase-modulated to suppress the stimulated Brillouin scattering (SBS) in the HNLF. The two pumps are then separated with a WDM and amplified by two erbium-doped fiber amplifiers (EDFA), followed by a polarization controller (PC) to match the polarizations, and subsequently combined with the signal using a series of two WDMs for launching into the HLNF where the NAND logic gate operation occurs. A 99/1 splitter is used to monitor the input pump power, and the optical spectra are obtained using an optical spectrum analyzer (OSA) at the output of the HNLF.

 

Fig. 2. (a) Experimental setup for measuring optical spectra and signal depletion ratio versus input pump power; (b) Optical spectra: black solid line is the spectrum with both pumps on, while light purple dashed line is the spectrum with both pumps off; (c) Signal depletion ratio as a function of total input pump power demonstrating 15.2 dB depletion.

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Figure 2(b) shows the measured spectra, where the black solid line represents the spectrum with both pumps ON, and the light purple-dashed line depicts the signal with both pumps OFF. A 15.2-dB maximum depletion of the signal can be seen, which will be used in the high-speed NAND gate operation to distinguish the logic 1 and logic 0 levels. The FWM-BS idler is generated at 1554.5 nm and will be employed for the AND gate operation. Additional waves are generated due to the cascaded FWM process between the FWM-BS idler and the pumps, and can be seen in the black trace of Fig. 2(b). Specifically, the “degenerate FWM idler” is generated at 1543 nm from the pump-degenerate FWM process between pump 1 and the FWM-BS idler, and the “non-degenerate FWM idler” is generated at 1557.5 nm from the non-degenerate FWM process among pump 1, pump 2, and the FWM-BS idler. These two cascaded idlers are not required and do not directly affect signal depletion; however, they can enhance the FWM-BS idler through amplification.

Figure 2(c) shows the pump-power dependence of the signal’s measured depletion ratio as expected as a result of the FWM-BS process. The maximum combined pump power used in the experiment is 31.6 dBm, providing a depletion of 15.2 dB corresponding to the spectra shown in Fig. 2(b).

To demonstrate the NAND gate operating on high-speed data signals, we perform time domain measurements. The experimental setup is shown in Fig. 3(a). Here we replace the phase modulator (PM) with an Optilab IM-1550-20 20-GHz bandwidth intensity modulator (IM) to encode the logical inputs on the two pumps. A 1000-bit-long 10-Gb/s pseudo random binary sequence (PRBS) is generated by Anritsu BERTWave MP2101A (operating up to 11.32 Gb/s) and amplified by a Multilink modulator driver (11-GHz bandwidth). This 1000 PRBS sequence was chosen to synchronize to our sampling oscilloscope in our specific experimental setup and does not represent any limitations in our nonlinear logic operation. A tunable optical delay line (TODL) is used to align the bit slots of the two pump channels, and the paths are mismatched by $\sim 2\mathrm{m}$ (100 bits) to randomize the relative data on the two pumps. The output of the HNLF is sent into a tunable filter and a photodiode to isolate and measure the pumps, signal, and idler individually in the time domain.

 

Fig. 3. (a) Experimental setup for time domain logic operation measurements; (b) time domain inputs (pump 1, pump 2), output logic functions (signal, idler), and their corresponding eye diagrams.

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Figure 3(b) shows the results of time domain logic demonstrations. As shown, the signal exhibits a low level (logic 0) when both pumps are at high levels (logic 1) due to the FWM-BS process, while for all other cases the signal maintains a high output level (logic 1), thereby validating the NAND optical logic gate operation at 10 Gb/s. Also shown, the idler behaves in the inverse manner thereby yielding an AND logic output at the idler wavelength. Both eye diagrams of the signal and the idler are open. The logic 1 level of the signal eye diagram is more densely populated, a result of three times more logic 1s than logic 0s in NAND operation. Conversely, the logic 0 level of the idler eye diagram is more densely filled, since there are three times more logic 0s than logic 1s in AND operation.

To better understand the variations on the logic 1 level of the signal (see Fig. 4(a)), we measure the signal trace in the time domain with only one pump at a time to see how each pump affects the signal level. As seen in Fig. 4(b), pump 1 (1549.2 nm) slightly amplifies the signal by approximately 0.3 dB; this can also be seen in Fig. 4(a) in the time slot 3020–3120 ps, when pump 1 is at high power level (logic 1) and pump 2 is at low power level (logic 0). This is a result of parametric amplification from the partially degenerate FWM process between pump 1 and the signal. In the other case, pump 2 (1564.3 nm) slightly depletes the signal by approximately 1 dB (see Fig. 4(c) and is also visible in Fig. 4(a) in the time slot 3220–3320 ps). This depletion likely results from stimulated Raman scattering, in which the power of signal is transferred to pump 2 and excites the crystal to a vibrational state. These combined effects result in the observed power level variation of the signal logic 1 level, as seen in Fig. 3(b). However, their impact is kept sufficiently small relative to the FWM-BS process, and an open eye is maintained. Notably, these effects result from the dispersive and Raman properties attributed by the HNLF, and can be overcome by better dispersive design of the fiber, a different choice of operating wavelengths, and/or the use of different nonlinear materials in, for example, dispersion-engineered integrated waveguides.

 

Fig. 4. Variation in level of signal logic 1 due to the presence of each individual pump. (a) Example time domain logic operations; (b) signal showing slight amplification when only pump 1 is present; (c) signal showing slight depletion when only pump 2 is present.

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To estimate the maximum operating rate of the HNLF-based logic gate demonstrated here, the bandwidth of the NAND logic operation is measured by observing the depletion of the signal in the time domain while fixing the two pump wavelengths and scanning the signal wavelength. Figure 5(a) shows the signal traces in the time domain for several signal wavelengths. The depletion of the signal is obtained by calculating the difference of the average power and the dip power (as indicated in Fig. 5(a) by the circled regions) where logic 0 occurs. The result is summarized in Fig. 5(b). As is shown, the maximum signal depletion is obtained when the signal is at 1540.4 nm, and the bandwidth is estimated to be around 1 nm, corresponding to 120 GHz. This serves as a first-order approximation of the signal bandwidth, and further investigation will explore the experimental data bandwidth. We expect that the operating bandwidth can be increased by improved dispersive design and the use of other nonlinear media such as integrated waveguides to both improve the phase-matching of the FWM-BS process as well as avoid the effects of parametric amplification and Raman depletion.

 

Fig. 5. Bandwidth measurements. (a) Signal traces in the time domain; the wavelength of the signal is indicated for each trace. (b) Bandwidth measurement of the NAND logic operation.

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Despite the wavelength conversion inherent to this approach, our NAND gate design facilitates cascaded logic operations since the phase-matching condition of the FWM-BS process is insensitive to interchanging the strong and weak waves between the four predefined wavelengths. Thus simply amplifying the output waves will allow them to serve as inputs to subsequent gates without any additional wavelength conversion. By design, each nonlinear element in a cascaded logic circuit can therefore be identical since the element itself is blind to the exact configuration of the waves. Furthermore, considering all waves are maintained in the telecommunications C-band, amplification and filtering can readily be added to each stage to enable cascaded gates and achieve FAN-OUT.

In summary, we demonstrate the first high-speed all-optical NAND logic gate with a single device using the FWM-BS process. We realize this device using 800 m of HNLF, but this approach is readily extended to other FWM platforms. We observe a maximum 15.2-dB extinction of the signal from the FWM-BS process in the HNLF, and the time domain measurements validate the NAND/AND gates’ operation on high-speed (10 Gb/s) data signals with open eye diagrams. Furthermore, we characterize the impact of ancillary nonlinear processes of parametric amplification and stimulated Raman scattering on the performance of the gate. We also measure the bandwidth of the NAND logic operation to be around 120 GHz. Notably, this approach extends to even higher data rates with improved design of the nonlinear FWM device, and we anticipate this method can be readily transferred to on-chip waveguide platforms, showing the promise for extremely high-speed cascaded logical operation in integrated all-optical systems.