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Circuit Implementation of Pilot-Based Dynamic MIMO Equalization for Coupled-Core Fibers

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Abstract

We explore ASIC implementation for pilot-based MIMO equalizers for coupled-core transmission, considering chip area scaling trends and performance impact of time-dependent drift. For a system with 28-GBd subcarriers, an equalizer for 8 ×8 is 5.3 times larger than for 2 × 2.

© 2024 The Author(s)

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