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Toward 1.6T Low-Power Coherent DSP: Challenges, and Lessons Learned from Preceding Generations

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Abstract

We review the progression of coherent DSP ASIC technology since 40nm silicon and identify the critical path toward beyond-terabit-per-wavelength pluggable modules. Challenges in various aspects of ASIC design and optical components are explored.

© 2024 The Author(s)

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