Challenges in implementing high-speed, low-power ADCs in CMOS

Lukas Kull

doi:10.1364/OFC.2015.Th1B.2

Optical Fiber Communication Conference
OSA Technical Digest (online) (Optica Publishing Group, 2015),
paper Th1B.2
•https://doi.org/10.1364/OFC.2015.Th1B.2

Challenges in implementing high-speed, low-power ADCs in CMOS

Lukas Kull

Optical Fiber Communication Conference 2015

Los Angeles, California United States
22–26 March 2015
ISBN: 978-1-55752-937-4

From the session
Practical ASIC Implementation (Th1B)

Not Accessible

Your library or personal account may give you access

Get PDF
Email
Share
Get Citation
Copy Citation Text
L. Kull, "Challenges in implementing high-speed, low-power ADCs in CMOS," in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optica Publishing Group, 2015), paper Th1B.2.

Export Citation
- BibTex
- Endnote (RIS)
- HTML
- Plain Text
Citation alert
Save article

Abstract

Challenges of CMOS ADC implementations for 100 Gb/s optical communication systems and beyond are highlighted. Limitations and opportunities of architectures and circuits are discussed based on a 56–90 GS/s 8 bit ADC in 32 nm SOI CMOS.

PDF Article

More Like This

CMOS ADC Developments for 100G Networks

Bernd Germann and Ian Dedic
SPTuC2 Signal Processing in Photonic Communications (SPPCom) 2010

High-Speed DACs and ADCs for Next Generation Flexible Transceivers

Charles Laperle and Maurice O’Sullivan
SM3E.1 Signal Processing in Photonic Communications (SPPCom) 2014

56Gs/s ADC : Enabling 100GbE

Ian Dedic
OThT6 Optical Fiber Communication Conference (OFC) 2010

Previous Article Next Article